1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64-gnu-linux < %s | FileCheck -check-prefixes=CHECK %s 3 4define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) { 5; CHECK-LABEL: test_frexp_v2f16_v2i32: 6; CHECK: // %bb.0: 7; CHECK-NEXT: sub sp, sp, #64 8; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill 9; CHECK-NEXT: .cfi_def_cfa_offset 64 10; CHECK-NEXT: .cfi_offset w19, -8 11; CHECK-NEXT: .cfi_offset w30, -16 12; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 13; CHECK-NEXT: mov h1, v0.h[1] 14; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill 15; CHECK-NEXT: add x0, sp, #36 16; CHECK-NEXT: add x19, sp, #36 17; CHECK-NEXT: fcvt s0, h1 18; CHECK-NEXT: bl frexpf 19; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload 20; CHECK-NEXT: fcvt h0, s0 21; CHECK-NEXT: add x0, sp, #32 22; CHECK-NEXT: fcvt s1, h1 23; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill 24; CHECK-NEXT: fmov s0, s1 25; CHECK-NEXT: bl frexpf 26; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload 27; CHECK-NEXT: fcvt h2, s0 28; CHECK-NEXT: add x0, sp, #40 29; CHECK-NEXT: mov h1, v1.h[2] 30; CHECK-NEXT: fcvt s0, h1 31; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 32; CHECK-NEXT: mov v2.h[1], v1.h[0] 33; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill 34; CHECK-NEXT: bl frexpf 35; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload 36; CHECK-NEXT: fcvt h2, s0 37; CHECK-NEXT: add x0, sp, #44 38; CHECK-NEXT: mov h1, v1.h[3] 39; CHECK-NEXT: fcvt s0, h1 40; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 41; CHECK-NEXT: mov v1.h[2], v2.h[0] 42; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill 43; CHECK-NEXT: bl frexpf 44; CHECK-NEXT: fcvt h2, s0 45; CHECK-NEXT: ldr s1, [sp, #32] 46; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload 47; CHECK-NEXT: ld1 { v1.s }[1], [x19] 48; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload 49; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1 50; CHECK-NEXT: mov v0.h[3], v2.h[0] 51; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 52; CHECK-NEXT: add sp, sp, #64 53; CHECK-NEXT: ret 54 %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a) 55 ret { <2 x half>, <2 x i32> } %result 56} 57 58define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) { 59; CHECK-LABEL: test_frexp_v3f16_v3i32: 60; CHECK: // %bb.0: 61; CHECK-NEXT: sub sp, sp, #80 62; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill 63; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill 64; CHECK-NEXT: .cfi_def_cfa_offset 80 65; CHECK-NEXT: .cfi_offset w19, -8 66; CHECK-NEXT: .cfi_offset w20, -16 67; CHECK-NEXT: .cfi_offset w30, -32 68; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill 69; CHECK-NEXT: mov s0, v0.s[1] 70; CHECK-NEXT: add x0, sp, #56 71; CHECK-NEXT: add x19, sp, #56 72; CHECK-NEXT: bl frexpf 73; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 74; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill 75; CHECK-NEXT: add x0, sp, #44 76; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload 77; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 78; CHECK-NEXT: bl frexpf 79; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 80; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 81; CHECK-NEXT: add x0, sp, #60 82; CHECK-NEXT: add x20, sp, #60 83; CHECK-NEXT: mov v0.s[1], v1.s[0] 84; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill 85; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload 86; CHECK-NEXT: mov s0, v0.s[2] 87; CHECK-NEXT: bl frexpf 88; CHECK-NEXT: ldr s1, [sp, #44] 89; CHECK-NEXT: ldr q2, [sp] // 16-byte Folded Reload 90; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 91; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload 92; CHECK-NEXT: ld1 { v1.s }[1], [x19] 93; CHECK-NEXT: mov v2.s[2], v0.s[0] 94; CHECK-NEXT: ld1 { v1.s }[2], [x20] 95; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload 96; CHECK-NEXT: mov v0.16b, v2.16b 97; CHECK-NEXT: add sp, sp, #80 98; CHECK-NEXT: ret 99 %result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3float.v3i32(<3 x float> %a) 100 ret { <3 x float>, <3 x i32> } %result 101} 102