1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5define i64 @i64_i64(i64 %a, i64 %b, i64 %d, i64 %e) { 6; CHECK-LABEL: i64_i64: 7; CHECK: // %bb.0: // %entry 8; CHECK-NEXT: cmp x0, x1 9; CHECK-NEXT: csel x0, x2, x3, lt 10; CHECK-NEXT: ret 11entry: 12 %c = icmp slt i64 %a, %b 13 %s = select i1 %c, i64 %d, i64 %e 14 ret i64 %s 15} 16 17define i32 @i32_i32(i32 %a, i32 %b, i32 %d, i32 %e) { 18; CHECK-LABEL: i32_i32: 19; CHECK: // %bb.0: // %entry 20; CHECK-NEXT: cmp w0, w1 21; CHECK-NEXT: csel w0, w2, w3, lt 22; CHECK-NEXT: ret 23entry: 24 %c = icmp slt i32 %a, %b 25 %s = select i1 %c, i32 %d, i32 %e 26 ret i32 %s 27} 28 29define i16 @i16_i16(i16 %a, i16 %b, i16 %d, i16 %e) { 30; CHECK-LABEL: i16_i16: 31; CHECK: // %bb.0: // %entry 32; CHECK-NEXT: sxth w8, w0 33; CHECK-NEXT: cmp w8, w1, sxth 34; CHECK-NEXT: csel w0, w2, w3, lt 35; CHECK-NEXT: ret 36entry: 37 %c = icmp slt i16 %a, %b 38 %s = select i1 %c, i16 %d, i16 %e 39 ret i16 %s 40} 41 42define i8 @i8_i8(i8 %a, i8 %b, i8 %d, i8 %e) { 43; CHECK-LABEL: i8_i8: 44; CHECK: // %bb.0: // %entry 45; CHECK-NEXT: sxtb w8, w0 46; CHECK-NEXT: cmp w8, w1, sxtb 47; CHECK-NEXT: csel w0, w2, w3, lt 48; CHECK-NEXT: ret 49entry: 50 %c = icmp slt i8 %a, %b 51 %s = select i1 %c, i8 %d, i8 %e 52 ret i8 %s 53} 54 55define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) { 56; CHECK-LABEL: test_v2i64_eq: 57; CHECK: // %bb.0: 58; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d 59; CHECK-NEXT: xtn v0.2s, v0.2d 60; CHECK-NEXT: ret 61 %cmp = icmp eq <2 x i64> %v1, %v2 62 ret <2 x i1> %cmp 63} 64 65define <4 x i1> @test_v4i64_eq(<4 x i64> %v1, <4 x i64> %v2) { 66; CHECK-SD-LABEL: test_v4i64_eq: 67; CHECK-SD: // %bb.0: // %entry 68; CHECK-SD-NEXT: cmeq v1.2d, v1.2d, v3.2d 69; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, v2.2d 70; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 71; CHECK-SD-NEXT: xtn v0.4h, v0.4s 72; CHECK-SD-NEXT: ret 73; 74; CHECK-GI-LABEL: test_v4i64_eq: 75; CHECK-GI: // %bb.0: // %entry 76; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d 77; CHECK-GI-NEXT: cmeq v1.2d, v1.2d, v3.2d 78; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 79; CHECK-GI-NEXT: xtn v0.4h, v0.4s 80; CHECK-GI-NEXT: ret 81entry: 82 %cmp = icmp eq <4 x i64> %v1, %v2 83 ret <4 x i1> %cmp 84} 85 86define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) { 87; CHECK-LABEL: test_v4i32_eq: 88; CHECK: // %bb.0: 89; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s 90; CHECK-NEXT: xtn v0.4h, v0.4s 91; CHECK-NEXT: ret 92 %cmp = icmp eq <4 x i32> %v1, %v2 93 ret <4 x i1> %cmp 94} 95 96define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) { 97; CHECK-LABEL: test_v2i32_eq: 98; CHECK: // %bb.0: 99; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s 100; CHECK-NEXT: ret 101 %cmp = icmp eq <2 x i32> %v1, %v2 102 ret <2 x i1> %cmp 103} 104 105define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) { 106; CHECK-SD-LABEL: test_v2i16_eq: 107; CHECK-SD: // %bb.0: 108; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff 109; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 110; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b 111; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s 112; CHECK-SD-NEXT: ret 113; 114; CHECK-GI-LABEL: test_v2i16_eq: 115; CHECK-GI: // %bb.0: 116; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff 117; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b 118; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 119; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s 120; CHECK-GI-NEXT: ret 121 %cmp = icmp eq <2 x i16> %v1, %v2 122 ret <2 x i1> %cmp 123} 124 125define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) { 126; CHECK-LABEL: test_v8i16_eq: 127; CHECK: // %bb.0: 128; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h 129; CHECK-NEXT: xtn v0.8b, v0.8h 130; CHECK-NEXT: ret 131 %cmp = icmp eq <8 x i16> %v1, %v2 132 ret <8 x i1> %cmp 133} 134 135define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) { 136; CHECK-LABEL: test_v4i16_eq: 137; CHECK: // %bb.0: 138; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h 139; CHECK-NEXT: ret 140 %cmp = icmp eq <4 x i16> %v1, %v2 141 ret <4 x i1> %cmp 142} 143 144define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) { 145; CHECK-LABEL: test_v16i8_eq: 146; CHECK: // %bb.0: 147; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b 148; CHECK-NEXT: ret 149 %cmp = icmp eq <16 x i8> %v1, %v2 150 ret <16 x i1> %cmp 151} 152 153define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) { 154; CHECK-LABEL: test_v8i8_eq: 155; CHECK: // %bb.0: 156; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b 157; CHECK-NEXT: ret 158 %cmp = icmp eq <8 x i8> %v1, %v2 159 ret <8 x i1> %cmp 160} 161 162define <2 x i1> @test_v2i64_ne(<2 x i64> %v1, <2 x i64> %v2) { 163; CHECK-LABEL: test_v2i64_ne: 164; CHECK: // %bb.0: 165; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d 166; CHECK-NEXT: mvn v0.16b, v0.16b 167; CHECK-NEXT: xtn v0.2s, v0.2d 168; CHECK-NEXT: ret 169 %cmp = icmp ne <2 x i64> %v1, %v2 170 ret <2 x i1> %cmp 171} 172 173define <4 x i1> @test_v4i64_ne(<4 x i64> %v1, <4 x i64> %v2) { 174; CHECK-SD-LABEL: test_v4i64_ne: 175; CHECK-SD: // %bb.0: // %entry 176; CHECK-SD-NEXT: cmeq v1.2d, v1.2d, v3.2d 177; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, v2.2d 178; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 179; CHECK-SD-NEXT: mvn v0.16b, v0.16b 180; CHECK-SD-NEXT: xtn v0.4h, v0.4s 181; CHECK-SD-NEXT: ret 182; 183; CHECK-GI-LABEL: test_v4i64_ne: 184; CHECK-GI: // %bb.0: // %entry 185; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d 186; CHECK-GI-NEXT: cmeq v1.2d, v1.2d, v3.2d 187; CHECK-GI-NEXT: mvn v0.16b, v0.16b 188; CHECK-GI-NEXT: mvn v1.16b, v1.16b 189; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 190; CHECK-GI-NEXT: xtn v0.4h, v0.4s 191; CHECK-GI-NEXT: ret 192entry: 193 %cmp = icmp ne <4 x i64> %v1, %v2 194 ret <4 x i1> %cmp 195} 196 197define <4 x i1> @test_v4i32_ne(<4 x i32> %v1, <4 x i32> %v2) { 198; CHECK-LABEL: test_v4i32_ne: 199; CHECK: // %bb.0: 200; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s 201; CHECK-NEXT: mvn v0.16b, v0.16b 202; CHECK-NEXT: xtn v0.4h, v0.4s 203; CHECK-NEXT: ret 204 %cmp = icmp ne <4 x i32> %v1, %v2 205 ret <4 x i1> %cmp 206} 207 208define <2 x i1> @test_v2i32_ne(<2 x i32> %v1, <2 x i32> %v2) { 209; CHECK-LABEL: test_v2i32_ne: 210; CHECK: // %bb.0: 211; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s 212; CHECK-NEXT: mvn v0.8b, v0.8b 213; CHECK-NEXT: ret 214 %cmp = icmp ne <2 x i32> %v1, %v2 215 ret <2 x i1> %cmp 216} 217 218define <2 x i1> @test_v2i16_ne(<2 x i16> %v1, <2 x i16> %v2) { 219; CHECK-SD-LABEL: test_v2i16_ne: 220; CHECK-SD: // %bb.0: 221; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff 222; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 223; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b 224; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s 225; CHECK-SD-NEXT: mvn v0.8b, v0.8b 226; CHECK-SD-NEXT: ret 227; 228; CHECK-GI-LABEL: test_v2i16_ne: 229; CHECK-GI: // %bb.0: 230; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff 231; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b 232; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 233; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s 234; CHECK-GI-NEXT: mvn v0.8b, v0.8b 235; CHECK-GI-NEXT: ret 236 %cmp = icmp ne <2 x i16> %v1, %v2 237 ret <2 x i1> %cmp 238} 239 240define <8 x i1> @test_v8i16_ne(<8 x i16> %v1, <8 x i16> %v2) { 241; CHECK-LABEL: test_v8i16_ne: 242; CHECK: // %bb.0: 243; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h 244; CHECK-NEXT: mvn v0.16b, v0.16b 245; CHECK-NEXT: xtn v0.8b, v0.8h 246; CHECK-NEXT: ret 247 %cmp = icmp ne <8 x i16> %v1, %v2 248 ret <8 x i1> %cmp 249} 250 251define <4 x i1> @test_v4i16_ne(<4 x i16> %v1, <4 x i16> %v2) { 252; CHECK-LABEL: test_v4i16_ne: 253; CHECK: // %bb.0: 254; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h 255; CHECK-NEXT: mvn v0.8b, v0.8b 256; CHECK-NEXT: ret 257 %cmp = icmp ne <4 x i16> %v1, %v2 258 ret <4 x i1> %cmp 259} 260 261define <16 x i1> @test_v16i8_ne(<16 x i8> %v1, <16 x i8> %v2) { 262; CHECK-LABEL: test_v16i8_ne: 263; CHECK: // %bb.0: 264; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b 265; CHECK-NEXT: mvn v0.16b, v0.16b 266; CHECK-NEXT: ret 267 %cmp = icmp ne <16 x i8> %v1, %v2 268 ret <16 x i1> %cmp 269} 270 271define <8 x i1> @test_v8i8_ne(<8 x i8> %v1, <8 x i8> %v2) { 272; CHECK-LABEL: test_v8i8_ne: 273; CHECK: // %bb.0: 274; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b 275; CHECK-NEXT: mvn v0.8b, v0.8b 276; CHECK-NEXT: ret 277 %cmp = icmp ne <8 x i8> %v1, %v2 278 ret <8 x i1> %cmp 279} 280 281define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) { 282; CHECK-LABEL: test_v2i64_ugt: 283; CHECK: // %bb.0: 284; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d 285; CHECK-NEXT: xtn v0.2s, v0.2d 286; CHECK-NEXT: ret 287 %cmp = icmp ugt <2 x i64> %v1, %v2 288 ret <2 x i1> %cmp 289} 290 291define <4 x i1> @test_v4i64_ugt(<4 x i64> %v1, <4 x i64> %v2) { 292; CHECK-SD-LABEL: test_v4i64_ugt: 293; CHECK-SD: // %bb.0: // %entry 294; CHECK-SD-NEXT: cmhi v1.2d, v1.2d, v3.2d 295; CHECK-SD-NEXT: cmhi v0.2d, v0.2d, v2.2d 296; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 297; CHECK-SD-NEXT: xtn v0.4h, v0.4s 298; CHECK-SD-NEXT: ret 299; 300; CHECK-GI-LABEL: test_v4i64_ugt: 301; CHECK-GI: // %bb.0: // %entry 302; CHECK-GI-NEXT: cmhi v0.2d, v0.2d, v2.2d 303; CHECK-GI-NEXT: cmhi v1.2d, v1.2d, v3.2d 304; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 305; CHECK-GI-NEXT: xtn v0.4h, v0.4s 306; CHECK-GI-NEXT: ret 307entry: 308 %cmp = icmp ugt <4 x i64> %v1, %v2 309 ret <4 x i1> %cmp 310} 311 312define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) { 313; CHECK-LABEL: test_v4i32_ugt: 314; CHECK: // %bb.0: 315; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s 316; CHECK-NEXT: xtn v0.4h, v0.4s 317; CHECK-NEXT: ret 318 %cmp = icmp ugt <4 x i32> %v1, %v2 319 ret <4 x i1> %cmp 320} 321 322define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) { 323; CHECK-LABEL: test_v2i32_ugt: 324; CHECK: // %bb.0: 325; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s 326; CHECK-NEXT: ret 327 %cmp = icmp ugt <2 x i32> %v1, %v2 328 ret <2 x i1> %cmp 329} 330 331define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) { 332; CHECK-SD-LABEL: test_v2i16_ugt: 333; CHECK-SD: // %bb.0: 334; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff 335; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 336; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b 337; CHECK-SD-NEXT: cmhi v0.2s, v0.2s, v1.2s 338; CHECK-SD-NEXT: ret 339; 340; CHECK-GI-LABEL: test_v2i16_ugt: 341; CHECK-GI: // %bb.0: 342; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff 343; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b 344; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 345; CHECK-GI-NEXT: cmhi v0.2s, v0.2s, v1.2s 346; CHECK-GI-NEXT: ret 347 %cmp = icmp ugt <2 x i16> %v1, %v2 348 ret <2 x i1> %cmp 349} 350 351define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) { 352; CHECK-LABEL: test_v8i16_ugt: 353; CHECK: // %bb.0: 354; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h 355; CHECK-NEXT: xtn v0.8b, v0.8h 356; CHECK-NEXT: ret 357 %cmp = icmp ugt <8 x i16> %v1, %v2 358 ret <8 x i1> %cmp 359} 360 361define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) { 362; CHECK-LABEL: test_v4i16_ugt: 363; CHECK: // %bb.0: 364; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h 365; CHECK-NEXT: ret 366 %cmp = icmp ugt <4 x i16> %v1, %v2 367 ret <4 x i1> %cmp 368} 369 370define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) { 371; CHECK-LABEL: test_v16i8_ugt: 372; CHECK: // %bb.0: 373; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b 374; CHECK-NEXT: ret 375 %cmp = icmp ugt <16 x i8> %v1, %v2 376 ret <16 x i1> %cmp 377} 378 379define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) { 380; CHECK-LABEL: test_v8i8_ugt: 381; CHECK: // %bb.0: 382; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b 383; CHECK-NEXT: ret 384 %cmp = icmp ugt <8 x i8> %v1, %v2 385 ret <8 x i1> %cmp 386} 387 388define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) { 389; CHECK-LABEL: test_v2i64_uge: 390; CHECK: // %bb.0: 391; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d 392; CHECK-NEXT: xtn v0.2s, v0.2d 393; CHECK-NEXT: ret 394 %cmp = icmp uge <2 x i64> %v1, %v2 395 ret <2 x i1> %cmp 396} 397 398define <4 x i1> @test_v4i64_uge(<4 x i64> %v1, <4 x i64> %v2) { 399; CHECK-SD-LABEL: test_v4i64_uge: 400; CHECK-SD: // %bb.0: // %entry 401; CHECK-SD-NEXT: cmhs v1.2d, v1.2d, v3.2d 402; CHECK-SD-NEXT: cmhs v0.2d, v0.2d, v2.2d 403; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 404; CHECK-SD-NEXT: xtn v0.4h, v0.4s 405; CHECK-SD-NEXT: ret 406; 407; CHECK-GI-LABEL: test_v4i64_uge: 408; CHECK-GI: // %bb.0: // %entry 409; CHECK-GI-NEXT: cmhs v0.2d, v0.2d, v2.2d 410; CHECK-GI-NEXT: cmhs v1.2d, v1.2d, v3.2d 411; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 412; CHECK-GI-NEXT: xtn v0.4h, v0.4s 413; CHECK-GI-NEXT: ret 414entry: 415 %cmp = icmp uge <4 x i64> %v1, %v2 416 ret <4 x i1> %cmp 417} 418 419define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) { 420; CHECK-LABEL: test_v4i32_uge: 421; CHECK: // %bb.0: 422; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s 423; CHECK-NEXT: xtn v0.4h, v0.4s 424; CHECK-NEXT: ret 425 %cmp = icmp uge <4 x i32> %v1, %v2 426 ret <4 x i1> %cmp 427} 428 429define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) { 430; CHECK-LABEL: test_v2i32_uge: 431; CHECK: // %bb.0: 432; CHECK-NEXT: cmhs v0.2s, v0.2s, v1.2s 433; CHECK-NEXT: ret 434 %cmp = icmp uge <2 x i32> %v1, %v2 435 ret <2 x i1> %cmp 436} 437 438define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) { 439; CHECK-SD-LABEL: test_v2i16_uge: 440; CHECK-SD: // %bb.0: 441; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff 442; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 443; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b 444; CHECK-SD-NEXT: cmhs v0.2s, v0.2s, v1.2s 445; CHECK-SD-NEXT: ret 446; 447; CHECK-GI-LABEL: test_v2i16_uge: 448; CHECK-GI: // %bb.0: 449; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff 450; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b 451; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 452; CHECK-GI-NEXT: cmhs v0.2s, v0.2s, v1.2s 453; CHECK-GI-NEXT: ret 454 %cmp = icmp uge <2 x i16> %v1, %v2 455 ret <2 x i1> %cmp 456} 457 458define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) { 459; CHECK-LABEL: test_v8i16_uge: 460; CHECK: // %bb.0: 461; CHECK-NEXT: cmhs v0.8h, v0.8h, v1.8h 462; CHECK-NEXT: xtn v0.8b, v0.8h 463; CHECK-NEXT: ret 464 %cmp = icmp uge <8 x i16> %v1, %v2 465 ret <8 x i1> %cmp 466} 467 468define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) { 469; CHECK-LABEL: test_v4i16_uge: 470; CHECK: // %bb.0: 471; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h 472; CHECK-NEXT: ret 473 %cmp = icmp uge <4 x i16> %v1, %v2 474 ret <4 x i1> %cmp 475} 476 477define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) { 478; CHECK-LABEL: test_v16i8_uge: 479; CHECK: // %bb.0: 480; CHECK-NEXT: cmhs v0.16b, v0.16b, v1.16b 481; CHECK-NEXT: ret 482 %cmp = icmp uge <16 x i8> %v1, %v2 483 ret <16 x i1> %cmp 484} 485 486define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) { 487; CHECK-LABEL: test_v8i8_uge: 488; CHECK: // %bb.0: 489; CHECK-NEXT: cmhs v0.8b, v0.8b, v1.8b 490; CHECK-NEXT: ret 491 %cmp = icmp uge <8 x i8> %v1, %v2 492 ret <8 x i1> %cmp 493} 494 495define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) { 496; CHECK-LABEL: test_v2i64_ult: 497; CHECK: // %bb.0: 498; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d 499; CHECK-NEXT: xtn v0.2s, v0.2d 500; CHECK-NEXT: ret 501 %cmp = icmp ult <2 x i64> %v1, %v2 502 ret <2 x i1> %cmp 503} 504 505define <4 x i1> @test_v4i64_ult(<4 x i64> %v1, <4 x i64> %v2) { 506; CHECK-SD-LABEL: test_v4i64_ult: 507; CHECK-SD: // %bb.0: // %entry 508; CHECK-SD-NEXT: cmhi v1.2d, v3.2d, v1.2d 509; CHECK-SD-NEXT: cmhi v0.2d, v2.2d, v0.2d 510; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 511; CHECK-SD-NEXT: xtn v0.4h, v0.4s 512; CHECK-SD-NEXT: ret 513; 514; CHECK-GI-LABEL: test_v4i64_ult: 515; CHECK-GI: // %bb.0: // %entry 516; CHECK-GI-NEXT: cmhi v0.2d, v2.2d, v0.2d 517; CHECK-GI-NEXT: cmhi v1.2d, v3.2d, v1.2d 518; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 519; CHECK-GI-NEXT: xtn v0.4h, v0.4s 520; CHECK-GI-NEXT: ret 521entry: 522 %cmp = icmp ult <4 x i64> %v1, %v2 523 ret <4 x i1> %cmp 524} 525 526define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) { 527; CHECK-LABEL: test_v4i32_ult: 528; CHECK: // %bb.0: 529; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s 530; CHECK-NEXT: xtn v0.4h, v0.4s 531; CHECK-NEXT: ret 532 %cmp = icmp ult <4 x i32> %v1, %v2 533 ret <4 x i1> %cmp 534} 535 536define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) { 537; CHECK-LABEL: test_v2i32_ult: 538; CHECK: // %bb.0: 539; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s 540; CHECK-NEXT: ret 541 %cmp = icmp ult <2 x i32> %v1, %v2 542 ret <2 x i1> %cmp 543} 544 545define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) { 546; CHECK-LABEL: test_v2i16_ult: 547; CHECK: // %bb.0: 548; CHECK-NEXT: movi d2, #0x00ffff0000ffff 549; CHECK-NEXT: and v0.8b, v0.8b, v2.8b 550; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 551; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s 552; CHECK-NEXT: ret 553 %cmp = icmp ult <2 x i16> %v1, %v2 554 ret <2 x i1> %cmp 555} 556 557define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) { 558; CHECK-LABEL: test_v8i16_ult: 559; CHECK: // %bb.0: 560; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h 561; CHECK-NEXT: xtn v0.8b, v0.8h 562; CHECK-NEXT: ret 563 %cmp = icmp ult <8 x i16> %v1, %v2 564 ret <8 x i1> %cmp 565} 566 567define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) { 568; CHECK-LABEL: test_v4i16_ult: 569; CHECK: // %bb.0: 570; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h 571; CHECK-NEXT: ret 572 %cmp = icmp ult <4 x i16> %v1, %v2 573 ret <4 x i1> %cmp 574} 575 576define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) { 577; CHECK-LABEL: test_v16i8_ult: 578; CHECK: // %bb.0: 579; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b 580; CHECK-NEXT: ret 581 %cmp = icmp ult <16 x i8> %v1, %v2 582 ret <16 x i1> %cmp 583} 584 585define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) { 586; CHECK-LABEL: test_v8i8_ult: 587; CHECK: // %bb.0: 588; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b 589; CHECK-NEXT: ret 590 %cmp = icmp ult <8 x i8> %v1, %v2 591 ret <8 x i1> %cmp 592} 593 594define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) { 595; CHECK-LABEL: test_v2i64_ule: 596; CHECK: // %bb.0: 597; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d 598; CHECK-NEXT: xtn v0.2s, v0.2d 599; CHECK-NEXT: ret 600 %cmp = icmp ule <2 x i64> %v1, %v2 601 ret <2 x i1> %cmp 602} 603 604define <4 x i1> @test_v4i64_ule(<4 x i64> %v1, <4 x i64> %v2) { 605; CHECK-SD-LABEL: test_v4i64_ule: 606; CHECK-SD: // %bb.0: // %entry 607; CHECK-SD-NEXT: cmhs v1.2d, v3.2d, v1.2d 608; CHECK-SD-NEXT: cmhs v0.2d, v2.2d, v0.2d 609; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 610; CHECK-SD-NEXT: xtn v0.4h, v0.4s 611; CHECK-SD-NEXT: ret 612; 613; CHECK-GI-LABEL: test_v4i64_ule: 614; CHECK-GI: // %bb.0: // %entry 615; CHECK-GI-NEXT: cmhs v0.2d, v2.2d, v0.2d 616; CHECK-GI-NEXT: cmhs v1.2d, v3.2d, v1.2d 617; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 618; CHECK-GI-NEXT: xtn v0.4h, v0.4s 619; CHECK-GI-NEXT: ret 620entry: 621 %cmp = icmp ule <4 x i64> %v1, %v2 622 ret <4 x i1> %cmp 623} 624 625define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) { 626; CHECK-LABEL: test_v4i32_ule: 627; CHECK: // %bb.0: 628; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s 629; CHECK-NEXT: xtn v0.4h, v0.4s 630; CHECK-NEXT: ret 631 %cmp = icmp ule <4 x i32> %v1, %v2 632 ret <4 x i1> %cmp 633} 634 635define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) { 636; CHECK-LABEL: test_v2i32_ule: 637; CHECK: // %bb.0: 638; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s 639; CHECK-NEXT: ret 640 %cmp = icmp ule <2 x i32> %v1, %v2 641 ret <2 x i1> %cmp 642} 643 644define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) { 645; CHECK-LABEL: test_v2i16_ule: 646; CHECK: // %bb.0: 647; CHECK-NEXT: movi d2, #0x00ffff0000ffff 648; CHECK-NEXT: and v0.8b, v0.8b, v2.8b 649; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 650; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s 651; CHECK-NEXT: ret 652 %cmp = icmp ule <2 x i16> %v1, %v2 653 ret <2 x i1> %cmp 654} 655 656define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) { 657; CHECK-LABEL: test_v8i16_ule: 658; CHECK: // %bb.0: 659; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h 660; CHECK-NEXT: xtn v0.8b, v0.8h 661; CHECK-NEXT: ret 662 %cmp = icmp ule <8 x i16> %v1, %v2 663 ret <8 x i1> %cmp 664} 665 666define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) { 667; CHECK-LABEL: test_v4i16_ule: 668; CHECK: // %bb.0: 669; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h 670; CHECK-NEXT: ret 671 %cmp = icmp ule <4 x i16> %v1, %v2 672 ret <4 x i1> %cmp 673} 674 675define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) { 676; CHECK-LABEL: test_v16i8_ule: 677; CHECK: // %bb.0: 678; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b 679; CHECK-NEXT: ret 680 %cmp = icmp ule <16 x i8> %v1, %v2 681 ret <16 x i1> %cmp 682} 683 684define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) { 685; CHECK-LABEL: test_v8i8_ule: 686; CHECK: // %bb.0: 687; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b 688; CHECK-NEXT: ret 689 %cmp = icmp ule <8 x i8> %v1, %v2 690 ret <8 x i1> %cmp 691} 692 693define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) { 694; CHECK-LABEL: test_v2i64_sgt: 695; CHECK: // %bb.0: 696; CHECK-NEXT: cmgt v0.2d, v0.2d, v1.2d 697; CHECK-NEXT: xtn v0.2s, v0.2d 698; CHECK-NEXT: ret 699 %cmp = icmp sgt <2 x i64> %v1, %v2 700 ret <2 x i1> %cmp 701} 702 703define <4 x i1> @test_v4i64_sgt(<4 x i64> %v1, <4 x i64> %v2) { 704; CHECK-SD-LABEL: test_v4i64_sgt: 705; CHECK-SD: // %bb.0: // %entry 706; CHECK-SD-NEXT: cmgt v1.2d, v1.2d, v3.2d 707; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, v2.2d 708; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 709; CHECK-SD-NEXT: xtn v0.4h, v0.4s 710; CHECK-SD-NEXT: ret 711; 712; CHECK-GI-LABEL: test_v4i64_sgt: 713; CHECK-GI: // %bb.0: // %entry 714; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v2.2d 715; CHECK-GI-NEXT: cmgt v1.2d, v1.2d, v3.2d 716; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 717; CHECK-GI-NEXT: xtn v0.4h, v0.4s 718; CHECK-GI-NEXT: ret 719entry: 720 %cmp = icmp sgt <4 x i64> %v1, %v2 721 ret <4 x i1> %cmp 722} 723 724define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) { 725; CHECK-LABEL: test_v4i32_sgt: 726; CHECK: // %bb.0: 727; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s 728; CHECK-NEXT: xtn v0.4h, v0.4s 729; CHECK-NEXT: ret 730 %cmp = icmp sgt <4 x i32> %v1, %v2 731 ret <4 x i1> %cmp 732} 733 734define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) { 735; CHECK-LABEL: test_v2i32_sgt: 736; CHECK: // %bb.0: 737; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s 738; CHECK-NEXT: ret 739 %cmp = icmp sgt <2 x i32> %v1, %v2 740 ret <2 x i1> %cmp 741} 742 743define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) { 744; CHECK-SD-LABEL: test_v2i16_sgt: 745; CHECK-SD: // %bb.0: 746; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16 747; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16 748; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #16 749; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16 750; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, v1.2s 751; CHECK-SD-NEXT: ret 752; 753; CHECK-GI-LABEL: test_v2i16_sgt: 754; CHECK-GI: // %bb.0: 755; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16 756; CHECK-GI-NEXT: shl v1.2s, v1.2s, #16 757; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16 758; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #16 759; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s 760; CHECK-GI-NEXT: ret 761 %cmp = icmp sgt <2 x i16> %v1, %v2 762 ret <2 x i1> %cmp 763} 764 765define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) { 766; CHECK-LABEL: test_v8i16_sgt: 767; CHECK: // %bb.0: 768; CHECK-NEXT: cmgt v0.8h, v0.8h, v1.8h 769; CHECK-NEXT: xtn v0.8b, v0.8h 770; CHECK-NEXT: ret 771 %cmp = icmp sgt <8 x i16> %v1, %v2 772 ret <8 x i1> %cmp 773} 774 775define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) { 776; CHECK-LABEL: test_v4i16_sgt: 777; CHECK: // %bb.0: 778; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h 779; CHECK-NEXT: ret 780 %cmp = icmp sgt <4 x i16> %v1, %v2 781 ret <4 x i1> %cmp 782} 783 784define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) { 785; CHECK-LABEL: test_v16i8_sgt: 786; CHECK: // %bb.0: 787; CHECK-NEXT: cmgt v0.16b, v0.16b, v1.16b 788; CHECK-NEXT: ret 789 %cmp = icmp sgt <16 x i8> %v1, %v2 790 ret <16 x i1> %cmp 791} 792 793define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) { 794; CHECK-LABEL: test_v8i8_sgt: 795; CHECK: // %bb.0: 796; CHECK-NEXT: cmgt v0.8b, v0.8b, v1.8b 797; CHECK-NEXT: ret 798 %cmp = icmp sgt <8 x i8> %v1, %v2 799 ret <8 x i1> %cmp 800} 801 802define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) { 803; CHECK-LABEL: test_v2i64_sge: 804; CHECK: // %bb.0: 805; CHECK-NEXT: cmge v0.2d, v0.2d, v1.2d 806; CHECK-NEXT: xtn v0.2s, v0.2d 807; CHECK-NEXT: ret 808 %cmp = icmp sge <2 x i64> %v1, %v2 809 ret <2 x i1> %cmp 810} 811 812define <4 x i1> @test_v4i64_sge(<4 x i64> %v1, <4 x i64> %v2) { 813; CHECK-SD-LABEL: test_v4i64_sge: 814; CHECK-SD: // %bb.0: // %entry 815; CHECK-SD-NEXT: cmge v1.2d, v1.2d, v3.2d 816; CHECK-SD-NEXT: cmge v0.2d, v0.2d, v2.2d 817; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 818; CHECK-SD-NEXT: xtn v0.4h, v0.4s 819; CHECK-SD-NEXT: ret 820; 821; CHECK-GI-LABEL: test_v4i64_sge: 822; CHECK-GI: // %bb.0: // %entry 823; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v2.2d 824; CHECK-GI-NEXT: cmge v1.2d, v1.2d, v3.2d 825; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 826; CHECK-GI-NEXT: xtn v0.4h, v0.4s 827; CHECK-GI-NEXT: ret 828entry: 829 %cmp = icmp sge <4 x i64> %v1, %v2 830 ret <4 x i1> %cmp 831} 832 833define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) { 834; CHECK-LABEL: test_v4i32_sge: 835; CHECK: // %bb.0: 836; CHECK-NEXT: cmge v0.4s, v0.4s, v1.4s 837; CHECK-NEXT: xtn v0.4h, v0.4s 838; CHECK-NEXT: ret 839 %cmp = icmp sge <4 x i32> %v1, %v2 840 ret <4 x i1> %cmp 841} 842 843define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) { 844; CHECK-LABEL: test_v2i32_sge: 845; CHECK: // %bb.0: 846; CHECK-NEXT: cmge v0.2s, v0.2s, v1.2s 847; CHECK-NEXT: ret 848 %cmp = icmp sge <2 x i32> %v1, %v2 849 ret <2 x i1> %cmp 850} 851 852define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) { 853; CHECK-SD-LABEL: test_v2i16_sge: 854; CHECK-SD: // %bb.0: 855; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16 856; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16 857; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #16 858; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16 859; CHECK-SD-NEXT: cmge v0.2s, v0.2s, v1.2s 860; CHECK-SD-NEXT: ret 861; 862; CHECK-GI-LABEL: test_v2i16_sge: 863; CHECK-GI: // %bb.0: 864; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16 865; CHECK-GI-NEXT: shl v1.2s, v1.2s, #16 866; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16 867; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #16 868; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s 869; CHECK-GI-NEXT: ret 870 %cmp = icmp sge <2 x i16> %v1, %v2 871 ret <2 x i1> %cmp 872} 873 874define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) { 875; CHECK-LABEL: test_v8i16_sge: 876; CHECK: // %bb.0: 877; CHECK-NEXT: cmge v0.8h, v0.8h, v1.8h 878; CHECK-NEXT: xtn v0.8b, v0.8h 879; CHECK-NEXT: ret 880 %cmp = icmp sge <8 x i16> %v1, %v2 881 ret <8 x i1> %cmp 882} 883 884define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) { 885; CHECK-LABEL: test_v4i16_sge: 886; CHECK: // %bb.0: 887; CHECK-NEXT: cmge v0.4h, v0.4h, v1.4h 888; CHECK-NEXT: ret 889 %cmp = icmp sge <4 x i16> %v1, %v2 890 ret <4 x i1> %cmp 891} 892 893define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) { 894; CHECK-LABEL: test_v16i8_sge: 895; CHECK: // %bb.0: 896; CHECK-NEXT: cmge v0.16b, v0.16b, v1.16b 897; CHECK-NEXT: ret 898 %cmp = icmp sge <16 x i8> %v1, %v2 899 ret <16 x i1> %cmp 900} 901 902define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) { 903; CHECK-LABEL: test_v8i8_sge: 904; CHECK: // %bb.0: 905; CHECK-NEXT: cmge v0.8b, v0.8b, v1.8b 906; CHECK-NEXT: ret 907 %cmp = icmp sge <8 x i8> %v1, %v2 908 ret <8 x i1> %cmp 909} 910 911define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) { 912; CHECK-LABEL: test_v2i64_slt: 913; CHECK: // %bb.0: 914; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d 915; CHECK-NEXT: xtn v0.2s, v0.2d 916; CHECK-NEXT: ret 917 %cmp = icmp slt <2 x i64> %v1, %v2 918 ret <2 x i1> %cmp 919} 920 921define <4 x i1> @test_v4i64_slt(<4 x i64> %v1, <4 x i64> %v2) { 922; CHECK-SD-LABEL: test_v4i64_slt: 923; CHECK-SD: // %bb.0: // %entry 924; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d 925; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d 926; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 927; CHECK-SD-NEXT: xtn v0.4h, v0.4s 928; CHECK-SD-NEXT: ret 929; 930; CHECK-GI-LABEL: test_v4i64_slt: 931; CHECK-GI: // %bb.0: // %entry 932; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d 933; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d 934; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 935; CHECK-GI-NEXT: xtn v0.4h, v0.4s 936; CHECK-GI-NEXT: ret 937entry: 938 %cmp = icmp slt <4 x i64> %v1, %v2 939 ret <4 x i1> %cmp 940} 941 942define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) { 943; CHECK-LABEL: test_v4i32_slt: 944; CHECK: // %bb.0: 945; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s 946; CHECK-NEXT: xtn v0.4h, v0.4s 947; CHECK-NEXT: ret 948 %cmp = icmp slt <4 x i32> %v1, %v2 949 ret <4 x i1> %cmp 950} 951 952define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) { 953; CHECK-LABEL: test_v2i32_slt: 954; CHECK: // %bb.0: 955; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s 956; CHECK-NEXT: ret 957 %cmp = icmp slt <2 x i32> %v1, %v2 958 ret <2 x i1> %cmp 959} 960 961define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) { 962; CHECK-LABEL: test_v2i16_slt: 963; CHECK: // %bb.0: 964; CHECK-NEXT: shl v0.2s, v0.2s, #16 965; CHECK-NEXT: shl v1.2s, v1.2s, #16 966; CHECK-NEXT: sshr v0.2s, v0.2s, #16 967; CHECK-NEXT: sshr v1.2s, v1.2s, #16 968; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s 969; CHECK-NEXT: ret 970 %cmp = icmp slt <2 x i16> %v1, %v2 971 ret <2 x i1> %cmp 972} 973 974define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) { 975; CHECK-LABEL: test_v8i16_slt: 976; CHECK: // %bb.0: 977; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h 978; CHECK-NEXT: xtn v0.8b, v0.8h 979; CHECK-NEXT: ret 980 %cmp = icmp slt <8 x i16> %v1, %v2 981 ret <8 x i1> %cmp 982} 983 984define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) { 985; CHECK-LABEL: test_v4i16_slt: 986; CHECK: // %bb.0: 987; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h 988; CHECK-NEXT: ret 989 %cmp = icmp slt <4 x i16> %v1, %v2 990 ret <4 x i1> %cmp 991} 992 993define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) { 994; CHECK-LABEL: test_v16i8_slt: 995; CHECK: // %bb.0: 996; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b 997; CHECK-NEXT: ret 998 %cmp = icmp slt <16 x i8> %v1, %v2 999 ret <16 x i1> %cmp 1000} 1001 1002define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) { 1003; CHECK-LABEL: test_v8i8_slt: 1004; CHECK: // %bb.0: 1005; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b 1006; CHECK-NEXT: ret 1007 %cmp = icmp slt <8 x i8> %v1, %v2 1008 ret <8 x i1> %cmp 1009} 1010 1011define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) { 1012; CHECK-LABEL: test_v2i64_sle: 1013; CHECK: // %bb.0: 1014; CHECK-NEXT: cmge v0.2d, v1.2d, v0.2d 1015; CHECK-NEXT: xtn v0.2s, v0.2d 1016; CHECK-NEXT: ret 1017 %cmp = icmp sle <2 x i64> %v1, %v2 1018 ret <2 x i1> %cmp 1019} 1020 1021define <4 x i1> @test_v4i64_sle(<4 x i64> %v1, <4 x i64> %v2) { 1022; CHECK-SD-LABEL: test_v4i64_sle: 1023; CHECK-SD: // %bb.0: // %entry 1024; CHECK-SD-NEXT: cmge v1.2d, v3.2d, v1.2d 1025; CHECK-SD-NEXT: cmge v0.2d, v2.2d, v0.2d 1026; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s 1027; CHECK-SD-NEXT: xtn v0.4h, v0.4s 1028; CHECK-SD-NEXT: ret 1029; 1030; CHECK-GI-LABEL: test_v4i64_sle: 1031; CHECK-GI: // %bb.0: // %entry 1032; CHECK-GI-NEXT: cmge v0.2d, v2.2d, v0.2d 1033; CHECK-GI-NEXT: cmge v1.2d, v3.2d, v1.2d 1034; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s 1035; CHECK-GI-NEXT: xtn v0.4h, v0.4s 1036; CHECK-GI-NEXT: ret 1037entry: 1038 %cmp = icmp sle <4 x i64> %v1, %v2 1039 ret <4 x i1> %cmp 1040} 1041 1042define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) { 1043; CHECK-LABEL: test_v4i32_sle: 1044; CHECK: // %bb.0: 1045; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s 1046; CHECK-NEXT: xtn v0.4h, v0.4s 1047; CHECK-NEXT: ret 1048 %cmp = icmp sle <4 x i32> %v1, %v2 1049 ret <4 x i1> %cmp 1050} 1051 1052define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) { 1053; CHECK-LABEL: test_v2i32_sle: 1054; CHECK: // %bb.0: 1055; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s 1056; CHECK-NEXT: ret 1057 %cmp = icmp sle <2 x i32> %v1, %v2 1058 ret <2 x i1> %cmp 1059} 1060 1061define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) { 1062; CHECK-LABEL: test_v2i16_sle: 1063; CHECK: // %bb.0: 1064; CHECK-NEXT: shl v0.2s, v0.2s, #16 1065; CHECK-NEXT: shl v1.2s, v1.2s, #16 1066; CHECK-NEXT: sshr v0.2s, v0.2s, #16 1067; CHECK-NEXT: sshr v1.2s, v1.2s, #16 1068; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s 1069; CHECK-NEXT: ret 1070 %cmp = icmp sle <2 x i16> %v1, %v2 1071 ret <2 x i1> %cmp 1072} 1073 1074define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) { 1075; CHECK-LABEL: test_v8i16_sle: 1076; CHECK: // %bb.0: 1077; CHECK-NEXT: cmge v0.8h, v1.8h, v0.8h 1078; CHECK-NEXT: xtn v0.8b, v0.8h 1079; CHECK-NEXT: ret 1080 %cmp = icmp sle <8 x i16> %v1, %v2 1081 ret <8 x i1> %cmp 1082} 1083 1084define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) { 1085; CHECK-LABEL: test_v4i16_sle: 1086; CHECK: // %bb.0: 1087; CHECK-NEXT: cmge v0.4h, v1.4h, v0.4h 1088; CHECK-NEXT: ret 1089 %cmp = icmp sle <4 x i16> %v1, %v2 1090 ret <4 x i1> %cmp 1091} 1092 1093define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) { 1094; CHECK-LABEL: test_v16i8_sle: 1095; CHECK: // %bb.0: 1096; CHECK-NEXT: cmge v0.16b, v1.16b, v0.16b 1097; CHECK-NEXT: ret 1098 %cmp = icmp sle <16 x i8> %v1, %v2 1099 ret <16 x i1> %cmp 1100} 1101 1102define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) { 1103; CHECK-LABEL: test_v8i8_sle: 1104; CHECK: // %bb.0: 1105; CHECK-NEXT: cmge v0.8b, v1.8b, v0.8b 1106; CHECK-NEXT: ret 1107 %cmp = icmp sle <8 x i8> %v1, %v2 1108 ret <8 x i1> %cmp 1109} 1110 1111define <2 x i64> @v2i64_i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %d, <2 x i64> %e) { 1112; CHECK-LABEL: v2i64_i64: 1113; CHECK: // %bb.0: // %entry 1114; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d 1115; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b 1116; CHECK-NEXT: ret 1117entry: 1118 %c = icmp slt <2 x i64> %a, %b 1119 %s = select <2 x i1> %c, <2 x i64> %d, <2 x i64> %e 1120 ret <2 x i64> %s 1121} 1122 1123define <3 x i64> @v3i64_i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %d, <3 x i64> %e) { 1124; CHECK-SD-LABEL: v3i64_i64: 1125; CHECK-SD: // %bb.0: // %entry 1126; CHECK-SD-NEXT: // kill: def $d4 killed $d4 def $q4 1127; CHECK-SD-NEXT: // kill: def $d3 killed $d3 def $q3 1128; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 1129; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 1130; CHECK-SD-NEXT: // kill: def $d6 killed $d6 def $q6 1131; CHECK-SD-NEXT: // kill: def $d7 killed $d7 def $q7 1132; CHECK-SD-NEXT: // kill: def $d5 killed $d5 def $q5 1133; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 1134; CHECK-SD-NEXT: ldr d16, [sp, #24] 1135; CHECK-SD-NEXT: ldr d17, [sp] 1136; CHECK-SD-NEXT: mov v3.d[1], v4.d[0] 1137; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] 1138; CHECK-SD-NEXT: mov v6.d[1], v7.d[0] 1139; CHECK-SD-NEXT: ldp d1, d4, [sp, #8] 1140; CHECK-SD-NEXT: mov v1.d[1], v4.d[0] 1141; CHECK-SD-NEXT: cmgt v0.2d, v3.2d, v0.2d 1142; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v1.16b 1143; CHECK-SD-NEXT: cmgt v1.2d, v5.2d, v2.2d 1144; CHECK-SD-NEXT: mov v2.16b, v1.16b 1145; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 1146; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 1147; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 1148; CHECK-SD-NEXT: bsl v2.16b, v17.16b, v16.16b 1149; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2 1150; CHECK-SD-NEXT: ret 1151; 1152; CHECK-GI-LABEL: v3i64_i64: 1153; CHECK-GI: // %bb.0: // %entry 1154; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 1155; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 1156; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3 1157; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4 1158; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 1159; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6 1160; CHECK-GI-NEXT: // kill: def $d5 killed $d5 def $q5 1161; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7 1162; CHECK-GI-NEXT: ldr x8, [sp] 1163; CHECK-GI-NEXT: ldr x10, [sp, #24] 1164; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] 1165; CHECK-GI-NEXT: mov v3.d[1], v4.d[0] 1166; CHECK-GI-NEXT: cmgt v2.2d, v5.2d, v2.2d 1167; CHECK-GI-NEXT: ldp d1, d4, [sp, #8] 1168; CHECK-GI-NEXT: mov v6.d[1], v7.d[0] 1169; CHECK-GI-NEXT: fmov x9, d2 1170; CHECK-GI-NEXT: mov v1.d[1], v4.d[0] 1171; CHECK-GI-NEXT: cmgt v0.2d, v3.2d, v0.2d 1172; CHECK-GI-NEXT: sbfx x9, x9, #0, #1 1173; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b 1174; CHECK-GI-NEXT: and x8, x8, x9 1175; CHECK-GI-NEXT: bic x9, x10, x9 1176; CHECK-GI-NEXT: orr x8, x8, x9 1177; CHECK-GI-NEXT: fmov d2, x8 1178; CHECK-GI-NEXT: mov d1, v0.d[1] 1179; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 1180; CHECK-GI-NEXT: ret 1181entry: 1182 %c = icmp slt <3 x i64> %a, %b 1183 %s = select <3 x i1> %c, <3 x i64> %d, <3 x i64> %e 1184 ret <3 x i64> %s 1185} 1186 1187define <4 x i64> @v4i64_i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %d, <4 x i64> %e) { 1188; CHECK-SD-LABEL: v4i64_i64: 1189; CHECK-SD: // %bb.0: // %entry 1190; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d 1191; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d 1192; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b 1193; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b 1194; CHECK-SD-NEXT: ret 1195; 1196; CHECK-GI-LABEL: v4i64_i64: 1197; CHECK-GI: // %bb.0: // %entry 1198; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d 1199; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d 1200; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b 1201; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b 1202; CHECK-GI-NEXT: ret 1203entry: 1204 %c = icmp slt <4 x i64> %a, %b 1205 %s = select <4 x i1> %c, <4 x i64> %d, <4 x i64> %e 1206 ret <4 x i64> %s 1207} 1208 1209define <2 x i32> @v2i32_i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %d, <2 x i32> %e) { 1210; CHECK-LABEL: v2i32_i32: 1211; CHECK: // %bb.0: // %entry 1212; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s 1213; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b 1214; CHECK-NEXT: ret 1215entry: 1216 %c = icmp slt <2 x i32> %a, %b 1217 %s = select <2 x i1> %c, <2 x i32> %d, <2 x i32> %e 1218 ret <2 x i32> %s 1219} 1220 1221define <3 x i32> @v3i32_i32(<3 x i32> %a, <3 x i32> %b, <3 x i32> %d, <3 x i32> %e) { 1222; CHECK-SD-LABEL: v3i32_i32: 1223; CHECK-SD: // %bb.0: // %entry 1224; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s 1225; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b 1226; CHECK-SD-NEXT: ret 1227; 1228; CHECK-GI-LABEL: v3i32_i32: 1229; CHECK-GI: // %bb.0: // %entry 1230; CHECK-GI-NEXT: mov w8, #31 // =0x1f 1231; CHECK-GI-NEXT: mov w9, #-1 // =0xffffffff 1232; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s 1233; CHECK-GI-NEXT: mov v4.s[0], w8 1234; CHECK-GI-NEXT: mov v5.s[0], w9 1235; CHECK-GI-NEXT: mov v4.s[1], w8 1236; CHECK-GI-NEXT: mov v5.s[1], w9 1237; CHECK-GI-NEXT: mov v4.s[2], w8 1238; CHECK-GI-NEXT: mov v5.s[2], w9 1239; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s 1240; CHECK-GI-NEXT: neg v1.4s, v4.4s 1241; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s 1242; CHECK-GI-NEXT: eor v1.16b, v0.16b, v5.16b 1243; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b 1244; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b 1245; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 1246; CHECK-GI-NEXT: ret 1247entry: 1248 %c = icmp slt <3 x i32> %a, %b 1249 %s = select <3 x i1> %c, <3 x i32> %d, <3 x i32> %e 1250 ret <3 x i32> %s 1251} 1252 1253define <4 x i32> @v4i32_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %d, <4 x i32> %e) { 1254; CHECK-LABEL: v4i32_i32: 1255; CHECK: // %bb.0: // %entry 1256; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s 1257; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b 1258; CHECK-NEXT: ret 1259entry: 1260 %c = icmp slt <4 x i32> %a, %b 1261 %s = select <4 x i1> %c, <4 x i32> %d, <4 x i32> %e 1262 ret <4 x i32> %s 1263} 1264 1265define <8 x i32> @v8i32_i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %d, <8 x i32> %e) { 1266; CHECK-SD-LABEL: v8i32_i32: 1267; CHECK-SD: // %bb.0: // %entry 1268; CHECK-SD-NEXT: cmgt v1.4s, v3.4s, v1.4s 1269; CHECK-SD-NEXT: cmgt v0.4s, v2.4s, v0.4s 1270; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b 1271; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b 1272; CHECK-SD-NEXT: ret 1273; 1274; CHECK-GI-LABEL: v8i32_i32: 1275; CHECK-GI: // %bb.0: // %entry 1276; CHECK-GI-NEXT: cmgt v0.4s, v2.4s, v0.4s 1277; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v1.4s 1278; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b 1279; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b 1280; CHECK-GI-NEXT: ret 1281entry: 1282 %c = icmp slt <8 x i32> %a, %b 1283 %s = select <8 x i1> %c, <8 x i32> %d, <8 x i32> %e 1284 ret <8 x i32> %s 1285} 1286 1287define <4 x i16> @v4i16_i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %d, <4 x i16> %e) { 1288; CHECK-LABEL: v4i16_i16: 1289; CHECK: // %bb.0: // %entry 1290; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h 1291; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b 1292; CHECK-NEXT: ret 1293entry: 1294 %c = icmp slt <4 x i16> %a, %b 1295 %s = select <4 x i1> %c, <4 x i16> %d, <4 x i16> %e 1296 ret <4 x i16> %s 1297} 1298 1299define <8 x i16> @v8i16_i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %d, <8 x i16> %e) { 1300; CHECK-LABEL: v8i16_i16: 1301; CHECK: // %bb.0: // %entry 1302; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h 1303; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b 1304; CHECK-NEXT: ret 1305entry: 1306 %c = icmp slt <8 x i16> %a, %b 1307 %s = select <8 x i1> %c, <8 x i16> %d, <8 x i16> %e 1308 ret <8 x i16> %s 1309} 1310 1311define <16 x i16> @v16i16_i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %d, <16 x i16> %e) { 1312; CHECK-SD-LABEL: v16i16_i16: 1313; CHECK-SD: // %bb.0: // %entry 1314; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h 1315; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h 1316; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b 1317; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b 1318; CHECK-SD-NEXT: ret 1319; 1320; CHECK-GI-LABEL: v16i16_i16: 1321; CHECK-GI: // %bb.0: // %entry 1322; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h 1323; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h 1324; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b 1325; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b 1326; CHECK-GI-NEXT: ret 1327entry: 1328 %c = icmp slt <16 x i16> %a, %b 1329 %s = select <16 x i1> %c, <16 x i16> %d, <16 x i16> %e 1330 ret <16 x i16> %s 1331} 1332 1333define <8 x i8> @v8i8_i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %d, <8 x i8> %e) { 1334; CHECK-LABEL: v8i8_i8: 1335; CHECK: // %bb.0: // %entry 1336; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b 1337; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b 1338; CHECK-NEXT: ret 1339entry: 1340 %c = icmp slt <8 x i8> %a, %b 1341 %s = select <8 x i1> %c, <8 x i8> %d, <8 x i8> %e 1342 ret <8 x i8> %s 1343} 1344 1345define <16 x i8> @v16i8_i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %d, <16 x i8> %e) { 1346; CHECK-LABEL: v16i8_i8: 1347; CHECK: // %bb.0: // %entry 1348; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b 1349; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b 1350; CHECK-NEXT: ret 1351entry: 1352 %c = icmp slt <16 x i8> %a, %b 1353 %s = select <16 x i1> %c, <16 x i8> %d, <16 x i8> %e 1354 ret <16 x i8> %s 1355} 1356 1357define <32 x i8> @v32i8_i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %d, <32 x i8> %e) { 1358; CHECK-SD-LABEL: v32i8_i8: 1359; CHECK-SD: // %bb.0: // %entry 1360; CHECK-SD-NEXT: cmgt v1.16b, v3.16b, v1.16b 1361; CHECK-SD-NEXT: cmgt v0.16b, v2.16b, v0.16b 1362; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b 1363; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b 1364; CHECK-SD-NEXT: ret 1365; 1366; CHECK-GI-LABEL: v32i8_i8: 1367; CHECK-GI: // %bb.0: // %entry 1368; CHECK-GI-NEXT: cmgt v0.16b, v2.16b, v0.16b 1369; CHECK-GI-NEXT: cmgt v1.16b, v3.16b, v1.16b 1370; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b 1371; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b 1372; CHECK-GI-NEXT: ret 1373entry: 1374 %c = icmp slt <32 x i8> %a, %b 1375 %s = select <32 x i1> %c, <32 x i8> %d, <32 x i8> %e 1376 ret <32 x i8> %s 1377} 1378 1379define <2 x i128> @v2i128_i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %d, <2 x i128> %e) { 1380; CHECK-SD-LABEL: v2i128_i128: 1381; CHECK-SD: // %bb.0: // %entry 1382; CHECK-SD-NEXT: add x10, sp, #32 1383; CHECK-SD-NEXT: mov x11, sp 1384; CHECK-SD-NEXT: cmp x0, x4 1385; CHECK-SD-NEXT: orr x12, x10, #0x8 1386; CHECK-SD-NEXT: orr x13, x11, #0x8 1387; CHECK-SD-NEXT: sbcs xzr, x1, x5 1388; CHECK-SD-NEXT: add x8, sp, #48 1389; CHECK-SD-NEXT: add x9, sp, #16 1390; CHECK-SD-NEXT: csel x12, x13, x12, lt 1391; CHECK-SD-NEXT: csel x10, x11, x10, lt 1392; CHECK-SD-NEXT: cmp x2, x6 1393; CHECK-SD-NEXT: orr x11, x8, #0x8 1394; CHECK-SD-NEXT: orr x13, x9, #0x8 1395; CHECK-SD-NEXT: sbcs xzr, x3, x7 1396; CHECK-SD-NEXT: ldr x0, [x10] 1397; CHECK-SD-NEXT: csel x8, x9, x8, lt 1398; CHECK-SD-NEXT: csel x9, x13, x11, lt 1399; CHECK-SD-NEXT: ldr x1, [x12] 1400; CHECK-SD-NEXT: ldr x2, [x8] 1401; CHECK-SD-NEXT: ldr x3, [x9] 1402; CHECK-SD-NEXT: ret 1403; 1404; CHECK-GI-LABEL: v2i128_i128: 1405; CHECK-GI: // %bb.0: // %entry 1406; CHECK-GI-NEXT: cmp x0, x4 1407; CHECK-GI-NEXT: ldp x9, x10, [sp] 1408; CHECK-GI-NEXT: cset w8, lo 1409; CHECK-GI-NEXT: cmp x1, x5 1410; CHECK-GI-NEXT: cset w11, lt 1411; CHECK-GI-NEXT: ldp x14, x15, [sp, #32] 1412; CHECK-GI-NEXT: csel w8, w8, w11, eq 1413; CHECK-GI-NEXT: cmp x2, x6 1414; CHECK-GI-NEXT: cset w11, lo 1415; CHECK-GI-NEXT: cmp x3, x7 1416; CHECK-GI-NEXT: ldp x12, x13, [sp, #16] 1417; CHECK-GI-NEXT: cset w16, lt 1418; CHECK-GI-NEXT: ldp x17, x18, [sp, #48] 1419; CHECK-GI-NEXT: csel w11, w11, w16, eq 1420; CHECK-GI-NEXT: tst w8, #0x1 1421; CHECK-GI-NEXT: csel x0, x9, x14, ne 1422; CHECK-GI-NEXT: csel x1, x10, x15, ne 1423; CHECK-GI-NEXT: tst w11, #0x1 1424; CHECK-GI-NEXT: csel x2, x12, x17, ne 1425; CHECK-GI-NEXT: csel x3, x13, x18, ne 1426; CHECK-GI-NEXT: ret 1427entry: 1428 %c = icmp slt <2 x i128> %a, %b 1429 %s = select <2 x i1> %c, <2 x i128> %d, <2 x i128> %e 1430 ret <2 x i128> %s 1431} 1432 1433; ===== ICMP Zero RHS ===== 1434 1435define <8 x i1> @icmp_eq_v8i8_Zero_RHS(<8 x i8> %a) { 1436; CHECK-LABEL: icmp_eq_v8i8_Zero_RHS: 1437; CHECK: // %bb.0: 1438; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 1439; CHECK-NEXT: ret 1440 %c = icmp eq <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1441 ret <8 x i1> %c 1442} 1443 1444define <16 x i1> @icmp_eq_v16i8_Zero_RHS(<16 x i8> %a) { 1445; CHECK-LABEL: icmp_eq_v16i8_Zero_RHS: 1446; CHECK: // %bb.0: 1447; CHECK-NEXT: cmeq v0.16b, v0.16b, #0 1448; CHECK-NEXT: ret 1449 %c = icmp eq <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1450 ret <16 x i1> %c 1451} 1452 1453define <4 x i1> @icmp_eq_v4i16_Zero_RHS(<4 x i16> %a) { 1454; CHECK-LABEL: icmp_eq_v4i16_Zero_RHS: 1455; CHECK: // %bb.0: 1456; CHECK-NEXT: cmeq v0.4h, v0.4h, #0 1457; CHECK-NEXT: ret 1458 %c = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0> 1459 ret <4 x i1> %c 1460} 1461 1462define <8 x i1> @icmp_eq_v8i16_Zero_RHS(<8 x i16> %a) { 1463; CHECK-LABEL: icmp_eq_v8i16_Zero_RHS: 1464; CHECK: // %bb.0: 1465; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 1466; CHECK-NEXT: xtn v0.8b, v0.8h 1467; CHECK-NEXT: ret 1468 %c = icmp eq <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 1469 ret <8 x i1> %c 1470} 1471 1472define <2 x i1> @icmp_eq_v2i32_Zero_RHS(<2 x i32> %a) { 1473; CHECK-LABEL: icmp_eq_v2i32_Zero_RHS: 1474; CHECK: // %bb.0: 1475; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 1476; CHECK-NEXT: ret 1477 %c = icmp eq <2 x i32> %a, <i32 0, i32 0> 1478 ret <2 x i1> %c 1479} 1480 1481define <4 x i1> @icmp_eq_v4i32_Zero_RHS(<4 x i32> %a) { 1482; CHECK-LABEL: icmp_eq_v4i32_Zero_RHS: 1483; CHECK: // %bb.0: 1484; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 1485; CHECK-NEXT: xtn v0.4h, v0.4s 1486; CHECK-NEXT: ret 1487 %c = icmp eq <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0> 1488 ret <4 x i1> %c 1489} 1490 1491define <2 x i1> @icmp_eq_v2i64_Zero_RHS(<2 x i64> %a) { 1492; CHECK-LABEL: icmp_eq_v2i64_Zero_RHS: 1493; CHECK: // %bb.0: 1494; CHECK-NEXT: cmeq v0.2d, v0.2d, #0 1495; CHECK-NEXT: xtn v0.2s, v0.2d 1496; CHECK-NEXT: ret 1497 %c = icmp eq <2 x i64> %a, <i64 0, i64 0> 1498 ret <2 x i1> %c 1499} 1500 1501define <8 x i1> @icmp_sge_v8i8_Zero_RHS(<8 x i8> %a) { 1502; CHECK-LABEL: icmp_sge_v8i8_Zero_RHS: 1503; CHECK: // %bb.0: 1504; CHECK-NEXT: cmge v0.8b, v0.8b, #0 1505; CHECK-NEXT: ret 1506 %c = icmp sge <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1507 ret <8 x i1> %c 1508} 1509 1510define <16 x i1> @icmp_sge_v16i8_Zero_RHS(<16 x i8> %a) { 1511; CHECK-LABEL: icmp_sge_v16i8_Zero_RHS: 1512; CHECK: // %bb.0: 1513; CHECK-NEXT: cmge v0.16b, v0.16b, #0 1514; CHECK-NEXT: ret 1515 %c = icmp sge <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1516 ret <16 x i1> %c 1517} 1518 1519define <4 x i1> @icmp_sge_v4i16_Zero_RHS(<4 x i16> %a) { 1520; CHECK-LABEL: icmp_sge_v4i16_Zero_RHS: 1521; CHECK: // %bb.0: 1522; CHECK-NEXT: cmge v0.4h, v0.4h, #0 1523; CHECK-NEXT: ret 1524 %c = icmp sge <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0> 1525 ret <4 x i1> %c 1526} 1527 1528define <8 x i1> @icmp_sge_v8i16_Zero_RHS(<8 x i16> %a) { 1529; CHECK-LABEL: icmp_sge_v8i16_Zero_RHS: 1530; CHECK: // %bb.0: 1531; CHECK-NEXT: cmge v0.8h, v0.8h, #0 1532; CHECK-NEXT: xtn v0.8b, v0.8h 1533; CHECK-NEXT: ret 1534 %c = icmp sge <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 1535 ret <8 x i1> %c 1536} 1537 1538define <2 x i1> @icmp_sge_v2i32_Zero_RHS(<2 x i32> %a) { 1539; CHECK-LABEL: icmp_sge_v2i32_Zero_RHS: 1540; CHECK: // %bb.0: 1541; CHECK-NEXT: cmge v0.2s, v0.2s, #0 1542; CHECK-NEXT: ret 1543 %c = icmp sge <2 x i32> %a, <i32 0, i32 0> 1544 ret <2 x i1> %c 1545} 1546 1547define <4 x i1> @icmp_sge_v4i32_Zero_RHS(<4 x i32> %a) { 1548; CHECK-LABEL: icmp_sge_v4i32_Zero_RHS: 1549; CHECK: // %bb.0: 1550; CHECK-NEXT: cmge v0.4s, v0.4s, #0 1551; CHECK-NEXT: xtn v0.4h, v0.4s 1552; CHECK-NEXT: ret 1553 %c = icmp sge <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0> 1554 ret <4 x i1> %c 1555} 1556 1557define <2 x i1> @icmp_sge_v2i64_Zero_RHS(<2 x i64> %a) { 1558; CHECK-LABEL: icmp_sge_v2i64_Zero_RHS: 1559; CHECK: // %bb.0: 1560; CHECK-NEXT: cmge v0.2d, v0.2d, #0 1561; CHECK-NEXT: xtn v0.2s, v0.2d 1562; CHECK-NEXT: ret 1563 %c = icmp sge <2 x i64> %a, <i64 0, i64 0> 1564 ret <2 x i1> %c 1565} 1566 1567define <8 x i1> @icmp_sgt_v8i8_Zero_RHS(<8 x i8> %a) { 1568; CHECK-LABEL: icmp_sgt_v8i8_Zero_RHS: 1569; CHECK: // %bb.0: 1570; CHECK-NEXT: cmgt v0.8b, v0.8b, #0 1571; CHECK-NEXT: ret 1572 %c = icmp sgt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1573 ret <8 x i1> %c 1574} 1575 1576define <16 x i1> @icmp_sgt_v16i8_Zero_RHS(<16 x i8> %a) { 1577; CHECK-LABEL: icmp_sgt_v16i8_Zero_RHS: 1578; CHECK: // %bb.0: 1579; CHECK-NEXT: cmgt v0.16b, v0.16b, #0 1580; CHECK-NEXT: ret 1581 %c = icmp sgt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1582 ret <16 x i1> %c 1583} 1584 1585define <4 x i1> @icmp_sgt_v4i16_Zero_RHS(<4 x i16> %a) { 1586; CHECK-LABEL: icmp_sgt_v4i16_Zero_RHS: 1587; CHECK: // %bb.0: 1588; CHECK-NEXT: cmgt v0.4h, v0.4h, #0 1589; CHECK-NEXT: ret 1590 %c = icmp sgt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0> 1591 ret <4 x i1> %c 1592} 1593 1594define <8 x i1> @icmp_sgt_v8i16_Zero_RHS(<8 x i16> %a) { 1595; CHECK-LABEL: icmp_sgt_v8i16_Zero_RHS: 1596; CHECK: // %bb.0: 1597; CHECK-NEXT: cmgt v0.8h, v0.8h, #0 1598; CHECK-NEXT: xtn v0.8b, v0.8h 1599; CHECK-NEXT: ret 1600 %c = icmp sgt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 1601 ret <8 x i1> %c 1602} 1603 1604define <2 x i1> @icmp_sgt_v2i32_Zero_RHS(<2 x i32> %a) { 1605; CHECK-LABEL: icmp_sgt_v2i32_Zero_RHS: 1606; CHECK: // %bb.0: 1607; CHECK-NEXT: cmgt v0.2s, v0.2s, #0 1608; CHECK-NEXT: ret 1609 %c = icmp sgt <2 x i32> %a, <i32 0, i32 0> 1610 ret <2 x i1> %c 1611} 1612 1613define <4 x i1> @icmp_sgt_v4i32_Zero_RHS(<4 x i32> %a) { 1614; CHECK-LABEL: icmp_sgt_v4i32_Zero_RHS: 1615; CHECK: // %bb.0: 1616; CHECK-NEXT: cmgt v0.4s, v0.4s, #0 1617; CHECK-NEXT: xtn v0.4h, v0.4s 1618; CHECK-NEXT: ret 1619 %c = icmp sgt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0> 1620 ret <4 x i1> %c 1621} 1622 1623define <2 x i1> @icmp_sgt_v2i64_Zero_RHS(<2 x i64> %a) { 1624; CHECK-LABEL: icmp_sgt_v2i64_Zero_RHS: 1625; CHECK: // %bb.0: 1626; CHECK-NEXT: cmgt v0.2d, v0.2d, #0 1627; CHECK-NEXT: xtn v0.2s, v0.2d 1628; CHECK-NEXT: ret 1629 %c = icmp sgt <2 x i64> %a, <i64 0, i64 0> 1630 ret <2 x i1> %c 1631} 1632 1633define <8 x i1> @icmp_sle_v8i8_Zero_RHS(<8 x i8> %a) { 1634; CHECK-LABEL: icmp_sle_v8i8_Zero_RHS: 1635; CHECK: // %bb.0: 1636; CHECK-NEXT: cmle v0.8b, v0.8b, #0 1637; CHECK-NEXT: ret 1638 %c = icmp sle <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1639 ret <8 x i1> %c 1640} 1641 1642define <16 x i1> @icmp_sle_v16i8_Zero_RHS(<16 x i8> %a) { 1643; CHECK-LABEL: icmp_sle_v16i8_Zero_RHS: 1644; CHECK: // %bb.0: 1645; CHECK-NEXT: cmle v0.16b, v0.16b, #0 1646; CHECK-NEXT: ret 1647 %c = icmp sle <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1648 ret <16 x i1> %c 1649} 1650 1651define <4 x i1> @icmp_sle_v4i16_Zero_RHS(<4 x i16> %a) { 1652; CHECK-LABEL: icmp_sle_v4i16_Zero_RHS: 1653; CHECK: // %bb.0: 1654; CHECK-NEXT: cmle v0.4h, v0.4h, #0 1655; CHECK-NEXT: ret 1656 %c = icmp sle <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0> 1657 ret <4 x i1> %c 1658} 1659 1660define <8 x i1> @icmp_sle_v8i16_Zero_RHS(<8 x i16> %a) { 1661; CHECK-LABEL: icmp_sle_v8i16_Zero_RHS: 1662; CHECK: // %bb.0: 1663; CHECK-NEXT: cmle v0.8h, v0.8h, #0 1664; CHECK-NEXT: xtn v0.8b, v0.8h 1665; CHECK-NEXT: ret 1666 %c = icmp sle <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 1667 ret <8 x i1> %c 1668} 1669 1670define <2 x i1> @icmp_sle_v2i32_Zero_RHS(<2 x i32> %a) { 1671; CHECK-LABEL: icmp_sle_v2i32_Zero_RHS: 1672; CHECK: // %bb.0: 1673; CHECK-NEXT: cmle v0.2s, v0.2s, #0 1674; CHECK-NEXT: ret 1675 %c = icmp sle <2 x i32> %a, <i32 0, i32 0> 1676 ret <2 x i1> %c 1677} 1678 1679define <4 x i1> @icmp_sle_v4i32_Zero_RHS(<4 x i32> %a) { 1680; CHECK-LABEL: icmp_sle_v4i32_Zero_RHS: 1681; CHECK: // %bb.0: 1682; CHECK-NEXT: cmle v0.4s, v0.4s, #0 1683; CHECK-NEXT: xtn v0.4h, v0.4s 1684; CHECK-NEXT: ret 1685 %c = icmp sle <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0> 1686 ret <4 x i1> %c 1687} 1688 1689define <2 x i1> @icmp_sle_v2i64_Zero_RHS(<2 x i64> %a) { 1690; CHECK-LABEL: icmp_sle_v2i64_Zero_RHS: 1691; CHECK: // %bb.0: 1692; CHECK-NEXT: cmle v0.2d, v0.2d, #0 1693; CHECK-NEXT: xtn v0.2s, v0.2d 1694; CHECK-NEXT: ret 1695 %c = icmp sle <2 x i64> %a, <i64 0, i64 0> 1696 ret <2 x i1> %c 1697} 1698 1699define <8 x i1> @icmp_slt_v8i8_Zero_RHS(<8 x i8> %a) { 1700; CHECK-LABEL: icmp_slt_v8i8_Zero_RHS: 1701; CHECK: // %bb.0: 1702; CHECK-NEXT: cmlt v0.8b, v0.8b, #0 1703; CHECK-NEXT: ret 1704 %c = icmp slt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1705 ret <8 x i1> %c 1706} 1707 1708define <16 x i1> @icmp_slt_v16i8_Zero_RHS(<16 x i8> %a) { 1709; CHECK-LABEL: icmp_slt_v16i8_Zero_RHS: 1710; CHECK: // %bb.0: 1711; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 1712; CHECK-NEXT: ret 1713 %c = icmp slt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 1714 ret <16 x i1> %c 1715} 1716 1717define <4 x i1> @icmp_slt_v4i16_Zero_RHS(<4 x i16> %a) { 1718; CHECK-LABEL: icmp_slt_v4i16_Zero_RHS: 1719; CHECK: // %bb.0: 1720; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 1721; CHECK-NEXT: ret 1722 %c = icmp slt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0> 1723 ret <4 x i1> %c 1724} 1725 1726define <8 x i1> @icmp_slt_v8i16_Zero_RHS(<8 x i16> %a) { 1727; CHECK-LABEL: icmp_slt_v8i16_Zero_RHS: 1728; CHECK: // %bb.0: 1729; CHECK-NEXT: cmlt v0.8h, v0.8h, #0 1730; CHECK-NEXT: xtn v0.8b, v0.8h 1731; CHECK-NEXT: ret 1732 %c = icmp slt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 1733 ret <8 x i1> %c 1734} 1735 1736define <2 x i1> @icmp_slt_v2i32_Zero_RHS(<2 x i32> %a) { 1737; CHECK-LABEL: icmp_slt_v2i32_Zero_RHS: 1738; CHECK: // %bb.0: 1739; CHECK-NEXT: cmlt v0.2s, v0.2s, #0 1740; CHECK-NEXT: ret 1741 %c = icmp slt <2 x i32> %a, <i32 0, i32 0> 1742 ret <2 x i1> %c 1743} 1744 1745define <4 x i1> @icmp_slt_v4i32_Zero_RHS(<4 x i32> %a) { 1746; CHECK-LABEL: icmp_slt_v4i32_Zero_RHS: 1747; CHECK: // %bb.0: 1748; CHECK-NEXT: cmlt v0.4s, v0.4s, #0 1749; CHECK-NEXT: xtn v0.4h, v0.4s 1750; CHECK-NEXT: ret 1751 %c = icmp slt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0> 1752 ret <4 x i1> %c 1753} 1754 1755define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) { 1756; CHECK-LABEL: icmp_slt_v2i64_Zero_RHS: 1757; CHECK: // %bb.0: 1758; CHECK-NEXT: cmlt v0.2d, v0.2d, #0 1759; CHECK-NEXT: xtn v0.2s, v0.2d 1760; CHECK-NEXT: ret 1761 %c = icmp slt <2 x i64> %a, <i64 0, i64 0> 1762 ret <2 x i1> %c 1763} 1764 1765; ===== ICMP Zero LHS ===== 1766 1767define <8 x i1> @icmp_eq_v8i8_Zero_LHS(<8 x i8> %a) { 1768; CHECK-LABEL: icmp_eq_v8i8_Zero_LHS: 1769; CHECK: // %bb.0: 1770; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 1771; CHECK-NEXT: ret 1772 %c = icmp eq <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1773 ret <8 x i1> %c 1774} 1775 1776define <16 x i1> @icmp_eq_v16i8_Zero_LHS(<16 x i8> %a) { 1777; CHECK-LABEL: icmp_eq_v16i8_Zero_LHS: 1778; CHECK: // %bb.0: 1779; CHECK-NEXT: cmeq v0.16b, v0.16b, #0 1780; CHECK-NEXT: ret 1781 %c = icmp eq <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1782 ret <16 x i1> %c 1783} 1784 1785define <4 x i1> @icmp_eq_v4i16_Zero_LHS(<4 x i16> %a) { 1786; CHECK-LABEL: icmp_eq_v4i16_Zero_LHS: 1787; CHECK: // %bb.0: 1788; CHECK-NEXT: cmeq v0.4h, v0.4h, #0 1789; CHECK-NEXT: ret 1790 %c = icmp eq <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a 1791 ret <4 x i1> %c 1792} 1793 1794define <8 x i1> @icmp_eq_v8i16_Zero_LHS(<8 x i16> %a) { 1795; CHECK-LABEL: icmp_eq_v8i16_Zero_LHS: 1796; CHECK: // %bb.0: 1797; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 1798; CHECK-NEXT: xtn v0.8b, v0.8h 1799; CHECK-NEXT: ret 1800 %c = icmp eq <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a 1801 ret <8 x i1> %c 1802} 1803 1804define <2 x i1> @icmp_eq_v2i32_Zero_LHS(<2 x i32> %a) { 1805; CHECK-LABEL: icmp_eq_v2i32_Zero_LHS: 1806; CHECK: // %bb.0: 1807; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 1808; CHECK-NEXT: ret 1809 %c = icmp eq <2 x i32> <i32 0, i32 0>, %a 1810 ret <2 x i1> %c 1811} 1812 1813define <4 x i1> @icmp_eq_v4i32_Zero_LHS(<4 x i32> %a) { 1814; CHECK-LABEL: icmp_eq_v4i32_Zero_LHS: 1815; CHECK: // %bb.0: 1816; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 1817; CHECK-NEXT: xtn v0.4h, v0.4s 1818; CHECK-NEXT: ret 1819 %c = icmp eq <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a 1820 ret <4 x i1> %c 1821} 1822 1823define <2 x i1> @icmp_eq_v2i64_Zero_LHS(<2 x i64> %a) { 1824; CHECK-LABEL: icmp_eq_v2i64_Zero_LHS: 1825; CHECK: // %bb.0: 1826; CHECK-NEXT: cmeq v0.2d, v0.2d, #0 1827; CHECK-NEXT: xtn v0.2s, v0.2d 1828; CHECK-NEXT: ret 1829 %c = icmp eq <2 x i64> <i64 0, i64 0>, %a 1830 ret <2 x i1> %c 1831} 1832 1833define <8 x i1> @icmp_sge_v8i8_Zero_LHS(<8 x i8> %a) { 1834; CHECK-LABEL: icmp_sge_v8i8_Zero_LHS: 1835; CHECK: // %bb.0: 1836; CHECK-NEXT: cmle v0.8b, v0.8b, #0 1837; CHECK-NEXT: ret 1838 %c = icmp sge <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1839 ret <8 x i1> %c 1840} 1841 1842define <16 x i1> @icmp_sge_v16i8_Zero_LHS(<16 x i8> %a) { 1843; CHECK-LABEL: icmp_sge_v16i8_Zero_LHS: 1844; CHECK: // %bb.0: 1845; CHECK-NEXT: cmle v0.16b, v0.16b, #0 1846; CHECK-NEXT: ret 1847 %c = icmp sge <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1848 ret <16 x i1> %c 1849} 1850 1851define <4 x i1> @icmp_sge_v4i16_Zero_LHS(<4 x i16> %a) { 1852; CHECK-LABEL: icmp_sge_v4i16_Zero_LHS: 1853; CHECK: // %bb.0: 1854; CHECK-NEXT: cmle v0.4h, v0.4h, #0 1855; CHECK-NEXT: ret 1856 %c = icmp sge <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a 1857 ret <4 x i1> %c 1858} 1859 1860define <8 x i1> @icmp_sge_v8i16_Zero_LHS(<8 x i16> %a) { 1861; CHECK-LABEL: icmp_sge_v8i16_Zero_LHS: 1862; CHECK: // %bb.0: 1863; CHECK-NEXT: cmle v0.8h, v0.8h, #0 1864; CHECK-NEXT: xtn v0.8b, v0.8h 1865; CHECK-NEXT: ret 1866 %c = icmp sge <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a 1867 ret <8 x i1> %c 1868} 1869 1870define <2 x i1> @icmp_sge_v2i32_Zero_LHS(<2 x i32> %a) { 1871; CHECK-LABEL: icmp_sge_v2i32_Zero_LHS: 1872; CHECK: // %bb.0: 1873; CHECK-NEXT: cmle v0.2s, v0.2s, #0 1874; CHECK-NEXT: ret 1875 %c = icmp sge <2 x i32> <i32 0, i32 0>, %a 1876 ret <2 x i1> %c 1877} 1878 1879define <4 x i1> @icmp_sge_v4i32_Zero_LHS(<4 x i32> %a) { 1880; CHECK-LABEL: icmp_sge_v4i32_Zero_LHS: 1881; CHECK: // %bb.0: 1882; CHECK-NEXT: cmle v0.4s, v0.4s, #0 1883; CHECK-NEXT: xtn v0.4h, v0.4s 1884; CHECK-NEXT: ret 1885 %c = icmp sge <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a 1886 ret <4 x i1> %c 1887} 1888 1889define <2 x i1> @icmp_sge_v2i64_Zero_LHS(<2 x i64> %a) { 1890; CHECK-LABEL: icmp_sge_v2i64_Zero_LHS: 1891; CHECK: // %bb.0: 1892; CHECK-NEXT: cmle v0.2d, v0.2d, #0 1893; CHECK-NEXT: xtn v0.2s, v0.2d 1894; CHECK-NEXT: ret 1895 %c = icmp sge <2 x i64> <i64 0, i64 0>, %a 1896 ret <2 x i1> %c 1897} 1898 1899define <8 x i1> @icmp_sgt_v8i8_Zero_LHS(<8 x i8> %a) { 1900; CHECK-LABEL: icmp_sgt_v8i8_Zero_LHS: 1901; CHECK: // %bb.0: 1902; CHECK-NEXT: cmlt v0.8b, v0.8b, #0 1903; CHECK-NEXT: ret 1904 %c = icmp sgt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1905 ret <8 x i1> %c 1906} 1907 1908define <16 x i1> @icmp_sgt_v16i8_Zero_LHS(<16 x i8> %a) { 1909; CHECK-LABEL: icmp_sgt_v16i8_Zero_LHS: 1910; CHECK: // %bb.0: 1911; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 1912; CHECK-NEXT: ret 1913 %c = icmp sgt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1914 ret <16 x i1> %c 1915} 1916 1917define <4 x i1> @icmp_sgt_v4i16_Zero_LHS(<4 x i16> %a) { 1918; CHECK-LABEL: icmp_sgt_v4i16_Zero_LHS: 1919; CHECK: // %bb.0: 1920; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 1921; CHECK-NEXT: ret 1922 %c = icmp sgt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a 1923 ret <4 x i1> %c 1924} 1925 1926define <8 x i1> @icmp_sgt_v8i16_Zero_LHS(<8 x i16> %a) { 1927; CHECK-LABEL: icmp_sgt_v8i16_Zero_LHS: 1928; CHECK: // %bb.0: 1929; CHECK-NEXT: cmlt v0.8h, v0.8h, #0 1930; CHECK-NEXT: xtn v0.8b, v0.8h 1931; CHECK-NEXT: ret 1932 %c = icmp sgt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a 1933 ret <8 x i1> %c 1934} 1935 1936define <2 x i1> @icmp_sgt_v2i32_Zero_LHS(<2 x i32> %a) { 1937; CHECK-LABEL: icmp_sgt_v2i32_Zero_LHS: 1938; CHECK: // %bb.0: 1939; CHECK-NEXT: cmlt v0.2s, v0.2s, #0 1940; CHECK-NEXT: ret 1941 %c = icmp sgt <2 x i32> <i32 0, i32 0>, %a 1942 ret <2 x i1> %c 1943} 1944 1945define <4 x i1> @icmp_sgt_v4i32_Zero_LHS(<4 x i32> %a) { 1946; CHECK-LABEL: icmp_sgt_v4i32_Zero_LHS: 1947; CHECK: // %bb.0: 1948; CHECK-NEXT: cmlt v0.4s, v0.4s, #0 1949; CHECK-NEXT: xtn v0.4h, v0.4s 1950; CHECK-NEXT: ret 1951 %c = icmp sgt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a 1952 ret <4 x i1> %c 1953} 1954 1955define <2 x i1> @icmp_sgt_v2i64_Zero_LHS(<2 x i64> %a) { 1956; CHECK-LABEL: icmp_sgt_v2i64_Zero_LHS: 1957; CHECK: // %bb.0: 1958; CHECK-NEXT: cmlt v0.2d, v0.2d, #0 1959; CHECK-NEXT: xtn v0.2s, v0.2d 1960; CHECK-NEXT: ret 1961 %c = icmp sgt <2 x i64> <i64 0, i64 0>, %a 1962 ret <2 x i1> %c 1963} 1964 1965define <8 x i1> @icmp_sle_v8i8_Zero_LHS(<8 x i8> %a) { 1966; CHECK-LABEL: icmp_sle_v8i8_Zero_LHS: 1967; CHECK: // %bb.0: 1968; CHECK-NEXT: cmge v0.8b, v0.8b, #0 1969; CHECK-NEXT: ret 1970 %c = icmp sle <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1971 ret <8 x i1> %c 1972} 1973 1974define <16 x i1> @icmp_sle_v16i8_Zero_LHS(<16 x i8> %a) { 1975; CHECK-LABEL: icmp_sle_v16i8_Zero_LHS: 1976; CHECK: // %bb.0: 1977; CHECK-NEXT: cmge v0.16b, v0.16b, #0 1978; CHECK-NEXT: ret 1979 %c = icmp sle <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 1980 ret <16 x i1> %c 1981} 1982 1983define <4 x i1> @icmp_sle_v4i16_Zero_LHS(<4 x i16> %a) { 1984; CHECK-LABEL: icmp_sle_v4i16_Zero_LHS: 1985; CHECK: // %bb.0: 1986; CHECK-NEXT: cmge v0.4h, v0.4h, #0 1987; CHECK-NEXT: ret 1988 %c = icmp sle <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a 1989 ret <4 x i1> %c 1990} 1991 1992define <8 x i1> @icmp_sle_v8i16_Zero_LHS(<8 x i16> %a) { 1993; CHECK-LABEL: icmp_sle_v8i16_Zero_LHS: 1994; CHECK: // %bb.0: 1995; CHECK-NEXT: cmge v0.8h, v0.8h, #0 1996; CHECK-NEXT: xtn v0.8b, v0.8h 1997; CHECK-NEXT: ret 1998 %c = icmp sle <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a 1999 ret <8 x i1> %c 2000} 2001 2002define <2 x i1> @icmp_sle_v2i32_Zero_LHS(<2 x i32> %a) { 2003; CHECK-LABEL: icmp_sle_v2i32_Zero_LHS: 2004; CHECK: // %bb.0: 2005; CHECK-NEXT: cmge v0.2s, v0.2s, #0 2006; CHECK-NEXT: ret 2007 %c = icmp sle <2 x i32> <i32 0, i32 0>, %a 2008 ret <2 x i1> %c 2009} 2010 2011define <4 x i1> @icmp_sle_v4i32_Zero_LHS(<4 x i32> %a) { 2012; CHECK-LABEL: icmp_sle_v4i32_Zero_LHS: 2013; CHECK: // %bb.0: 2014; CHECK-NEXT: cmge v0.4s, v0.4s, #0 2015; CHECK-NEXT: xtn v0.4h, v0.4s 2016; CHECK-NEXT: ret 2017 %c = icmp sle <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a 2018 ret <4 x i1> %c 2019} 2020 2021define <2 x i1> @icmp_sle_v2i64_Zero_LHS(<2 x i64> %a) { 2022; CHECK-LABEL: icmp_sle_v2i64_Zero_LHS: 2023; CHECK: // %bb.0: 2024; CHECK-NEXT: cmge v0.2d, v0.2d, #0 2025; CHECK-NEXT: xtn v0.2s, v0.2d 2026; CHECK-NEXT: ret 2027 %c = icmp sle <2 x i64> <i64 0, i64 0>, %a 2028 ret <2 x i1> %c 2029} 2030 2031define <8 x i1> @icmp_slt_v8i8_Zero_LHS(<8 x i8> %a) { 2032; CHECK-LABEL: icmp_slt_v8i8_Zero_LHS: 2033; CHECK: // %bb.0: 2034; CHECK-NEXT: cmgt v0.8b, v0.8b, #0 2035; CHECK-NEXT: ret 2036 %c = icmp slt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 2037 ret <8 x i1> %c 2038} 2039 2040define <16 x i1> @icmp_slt_v16i8_Zero_LHS(<16 x i8> %a) { 2041; CHECK-LABEL: icmp_slt_v16i8_Zero_LHS: 2042; CHECK: // %bb.0: 2043; CHECK-NEXT: cmgt v0.16b, v0.16b, #0 2044; CHECK-NEXT: ret 2045 %c = icmp slt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a 2046 ret <16 x i1> %c 2047} 2048 2049define <4 x i1> @icmp_slt_v4i16_Zero_LHS(<4 x i16> %a) { 2050; CHECK-LABEL: icmp_slt_v4i16_Zero_LHS: 2051; CHECK: // %bb.0: 2052; CHECK-NEXT: cmgt v0.4h, v0.4h, #0 2053; CHECK-NEXT: ret 2054 %c = icmp slt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a 2055 ret <4 x i1> %c 2056} 2057 2058define <8 x i1> @icmp_slt_v8i16_Zero_LHS(<8 x i16> %a) { 2059; CHECK-LABEL: icmp_slt_v8i16_Zero_LHS: 2060; CHECK: // %bb.0: 2061; CHECK-NEXT: cmgt v0.8h, v0.8h, #0 2062; CHECK-NEXT: xtn v0.8b, v0.8h 2063; CHECK-NEXT: ret 2064 %c = icmp slt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a 2065 ret <8 x i1> %c 2066} 2067 2068define <2 x i1> @icmp_slt_v2i32_Zero_LHS(<2 x i32> %a) { 2069; CHECK-LABEL: icmp_slt_v2i32_Zero_LHS: 2070; CHECK: // %bb.0: 2071; CHECK-NEXT: cmgt v0.2s, v0.2s, #0 2072; CHECK-NEXT: ret 2073 %c = icmp slt <2 x i32> <i32 0, i32 0>, %a 2074 ret <2 x i1> %c 2075} 2076 2077define <4 x i1> @icmp_slt_v4i32_Zero_LHS(<4 x i32> %a) { 2078; CHECK-LABEL: icmp_slt_v4i32_Zero_LHS: 2079; CHECK: // %bb.0: 2080; CHECK-NEXT: cmgt v0.4s, v0.4s, #0 2081; CHECK-NEXT: xtn v0.4h, v0.4s 2082; CHECK-NEXT: ret 2083 %c = icmp slt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a 2084 ret <4 x i1> %c 2085} 2086 2087define <2 x i1> @icmp_slt_v2i64_Zero_LHS(<2 x i64> %a) { 2088; CHECK-LABEL: icmp_slt_v2i64_Zero_LHS: 2089; CHECK: // %bb.0: 2090; CHECK-NEXT: cmgt v0.2d, v0.2d, #0 2091; CHECK-NEXT: xtn v0.2s, v0.2d 2092; CHECK-NEXT: ret 2093 %c = icmp slt <2 x i64> <i64 0, i64 0>, %a 2094 ret <2 x i1> %c 2095} 2096