1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5define i8 @rotl_i8(i8 %a, i8 %c) { 6; CHECK-SD-LABEL: rotl_i8: 7; CHECK-SD: // %bb.0: // %entry 8; CHECK-SD-NEXT: neg w8, w1 9; CHECK-SD-NEXT: and w9, w0, #0xff 10; CHECK-SD-NEXT: and w10, w1, #0x7 11; CHECK-SD-NEXT: and w8, w8, #0x7 12; CHECK-SD-NEXT: lsl w10, w0, w10 13; CHECK-SD-NEXT: lsr w8, w9, w8 14; CHECK-SD-NEXT: orr w0, w10, w8 15; CHECK-SD-NEXT: ret 16; 17; CHECK-GI-LABEL: rotl_i8: 18; CHECK-GI: // %bb.0: // %entry 19; CHECK-GI-NEXT: mov x8, xzr 20; CHECK-GI-NEXT: neg w9, w1 21; CHECK-GI-NEXT: and w10, w0, #0xff 22; CHECK-GI-NEXT: sub x8, x8, w9, uxtb 23; CHECK-GI-NEXT: and x9, x9, #0x7 24; CHECK-GI-NEXT: lsr w9, w10, w9 25; CHECK-GI-NEXT: and x8, x8, #0x7 26; CHECK-GI-NEXT: lsl w8, w0, w8 27; CHECK-GI-NEXT: orr w0, w9, w8 28; CHECK-GI-NEXT: ret 29entry: 30 %d = call i8 @llvm.fshl(i8 %a, i8 %a, i8 %c) 31 ret i8 %d 32} 33 34define i8 @rotr_i8(i8 %a, i8 %c) { 35; CHECK-SD-LABEL: rotr_i8: 36; CHECK-SD: // %bb.0: // %entry 37; CHECK-SD-NEXT: neg w8, w1 38; CHECK-SD-NEXT: and w9, w0, #0xff 39; CHECK-SD-NEXT: and w10, w1, #0x7 40; CHECK-SD-NEXT: and w8, w8, #0x7 41; CHECK-SD-NEXT: lsr w9, w9, w10 42; CHECK-SD-NEXT: lsl w8, w0, w8 43; CHECK-SD-NEXT: orr w0, w9, w8 44; CHECK-SD-NEXT: ret 45; 46; CHECK-GI-LABEL: rotr_i8: 47; CHECK-GI: // %bb.0: // %entry 48; CHECK-GI-NEXT: mov x8, xzr 49; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1 50; CHECK-GI-NEXT: and x9, x1, #0x7 51; CHECK-GI-NEXT: and w10, w0, #0xff 52; CHECK-GI-NEXT: sub x8, x8, w1, uxtb 53; CHECK-GI-NEXT: lsr w9, w10, w9 54; CHECK-GI-NEXT: and x8, x8, #0x7 55; CHECK-GI-NEXT: lsl w8, w0, w8 56; CHECK-GI-NEXT: orr w0, w9, w8 57; CHECK-GI-NEXT: ret 58entry: 59 %d = call i8 @llvm.fshr(i8 %a, i8 %a, i8 %c) 60 ret i8 %d 61} 62 63define i16 @rotl_i16(i16 %a, i16 %c) { 64; CHECK-SD-LABEL: rotl_i16: 65; CHECK-SD: // %bb.0: // %entry 66; CHECK-SD-NEXT: neg w8, w1 67; CHECK-SD-NEXT: and w9, w0, #0xffff 68; CHECK-SD-NEXT: and w10, w1, #0xf 69; CHECK-SD-NEXT: and w8, w8, #0xf 70; CHECK-SD-NEXT: lsl w10, w0, w10 71; CHECK-SD-NEXT: lsr w8, w9, w8 72; CHECK-SD-NEXT: orr w0, w10, w8 73; CHECK-SD-NEXT: ret 74; 75; CHECK-GI-LABEL: rotl_i16: 76; CHECK-GI: // %bb.0: // %entry 77; CHECK-GI-NEXT: mov x8, xzr 78; CHECK-GI-NEXT: neg w9, w1 79; CHECK-GI-NEXT: and w10, w0, #0xffff 80; CHECK-GI-NEXT: sub x8, x8, w9, uxth 81; CHECK-GI-NEXT: and x9, x9, #0xf 82; CHECK-GI-NEXT: lsr w9, w10, w9 83; CHECK-GI-NEXT: and x8, x8, #0xf 84; CHECK-GI-NEXT: lsl w8, w0, w8 85; CHECK-GI-NEXT: orr w0, w9, w8 86; CHECK-GI-NEXT: ret 87entry: 88 %d = call i16 @llvm.fshl(i16 %a, i16 %a, i16 %c) 89 ret i16 %d 90} 91 92define i16 @rotr_i16(i16 %a, i16 %c) { 93; CHECK-SD-LABEL: rotr_i16: 94; CHECK-SD: // %bb.0: // %entry 95; CHECK-SD-NEXT: neg w8, w1 96; CHECK-SD-NEXT: and w9, w0, #0xffff 97; CHECK-SD-NEXT: and w10, w1, #0xf 98; CHECK-SD-NEXT: and w8, w8, #0xf 99; CHECK-SD-NEXT: lsr w9, w9, w10 100; CHECK-SD-NEXT: lsl w8, w0, w8 101; CHECK-SD-NEXT: orr w0, w9, w8 102; CHECK-SD-NEXT: ret 103; 104; CHECK-GI-LABEL: rotr_i16: 105; CHECK-GI: // %bb.0: // %entry 106; CHECK-GI-NEXT: mov x8, xzr 107; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1 108; CHECK-GI-NEXT: and x9, x1, #0xf 109; CHECK-GI-NEXT: and w10, w0, #0xffff 110; CHECK-GI-NEXT: sub x8, x8, w1, uxth 111; CHECK-GI-NEXT: lsr w9, w10, w9 112; CHECK-GI-NEXT: and x8, x8, #0xf 113; CHECK-GI-NEXT: lsl w8, w0, w8 114; CHECK-GI-NEXT: orr w0, w9, w8 115; CHECK-GI-NEXT: ret 116entry: 117 %d = call i16 @llvm.fshr(i16 %a, i16 %a, i16 %c) 118 ret i16 %d 119} 120 121define i32 @rotl_i32(i32 %a, i32 %c) { 122; CHECK-LABEL: rotl_i32: 123; CHECK: // %bb.0: // %entry 124; CHECK-NEXT: neg w8, w1 125; CHECK-NEXT: ror w0, w0, w8 126; CHECK-NEXT: ret 127entry: 128 %d = call i32 @llvm.fshl(i32 %a, i32 %a, i32 %c) 129 ret i32 %d 130} 131 132define i32 @rotr_i32(i32 %a, i32 %c) { 133; CHECK-LABEL: rotr_i32: 134; CHECK: // %bb.0: // %entry 135; CHECK-NEXT: ror w0, w0, w1 136; CHECK-NEXT: ret 137entry: 138 %d = call i32 @llvm.fshr(i32 %a, i32 %a, i32 %c) 139 ret i32 %d 140} 141 142define i64 @rotl_i64(i64 %a, i64 %c) { 143; CHECK-SD-LABEL: rotl_i64: 144; CHECK-SD: // %bb.0: // %entry 145; CHECK-SD-NEXT: neg w8, w1 146; CHECK-SD-NEXT: ror x0, x0, x8 147; CHECK-SD-NEXT: ret 148; 149; CHECK-GI-LABEL: rotl_i64: 150; CHECK-GI: // %bb.0: // %entry 151; CHECK-GI-NEXT: neg x8, x1 152; CHECK-GI-NEXT: ror x0, x0, x8 153; CHECK-GI-NEXT: ret 154entry: 155 %d = call i64 @llvm.fshl(i64 %a, i64 %a, i64 %c) 156 ret i64 %d 157} 158 159define i64 @rotr_i64(i64 %a, i64 %c) { 160; CHECK-LABEL: rotr_i64: 161; CHECK: // %bb.0: // %entry 162; CHECK-NEXT: ror x0, x0, x1 163; CHECK-NEXT: ret 164entry: 165 %d = call i64 @llvm.fshr(i64 %a, i64 %a, i64 %c) 166 ret i64 %d 167} 168 169define i128 @rotl_i128(i128 %a, i128 %c) { 170; CHECK-SD-LABEL: rotl_i128: 171; CHECK-SD: // %bb.0: // %entry 172; CHECK-SD-NEXT: tst x2, #0x40 173; CHECK-SD-NEXT: mvn w12, w2 174; CHECK-SD-NEXT: csel x8, x1, x0, ne 175; CHECK-SD-NEXT: csel x9, x0, x1, ne 176; CHECK-SD-NEXT: lsr x10, x9, #1 177; CHECK-SD-NEXT: lsr x11, x8, #1 178; CHECK-SD-NEXT: lsl x8, x8, x2 179; CHECK-SD-NEXT: lsl x9, x9, x2 180; CHECK-SD-NEXT: lsr x10, x10, x12 181; CHECK-SD-NEXT: lsr x11, x11, x12 182; CHECK-SD-NEXT: orr x0, x8, x10 183; CHECK-SD-NEXT: orr x1, x9, x11 184; CHECK-SD-NEXT: ret 185; 186; CHECK-GI-LABEL: rotl_i128: 187; CHECK-GI: // %bb.0: // %entry 188; CHECK-GI-NEXT: mov w8, #64 // =0x40 189; CHECK-GI-NEXT: and x9, x2, #0x7f 190; CHECK-GI-NEXT: neg x10, x2 191; CHECK-GI-NEXT: sub x12, x8, x9 192; CHECK-GI-NEXT: sub x11, x9, #64 193; CHECK-GI-NEXT: lsl x14, x1, x9 194; CHECK-GI-NEXT: lsr x12, x0, x12 195; CHECK-GI-NEXT: lsl x13, x0, x9 196; CHECK-GI-NEXT: cmp x9, #64 197; CHECK-GI-NEXT: and x9, x10, #0x7f 198; CHECK-GI-NEXT: lsl x11, x0, x11 199; CHECK-GI-NEXT: orr x12, x12, x14 200; CHECK-GI-NEXT: sub x8, x8, x9 201; CHECK-GI-NEXT: sub x14, x9, #64 202; CHECK-GI-NEXT: csel x11, x12, x11, lo 203; CHECK-GI-NEXT: lsr x12, x0, x9 204; CHECK-GI-NEXT: lsl x8, x1, x8 205; CHECK-GI-NEXT: csel x13, x13, xzr, lo 206; CHECK-GI-NEXT: tst x2, #0x7f 207; CHECK-GI-NEXT: lsr x14, x1, x14 208; CHECK-GI-NEXT: csel x11, x1, x11, eq 209; CHECK-GI-NEXT: orr x8, x12, x8 210; CHECK-GI-NEXT: cmp x9, #64 211; CHECK-GI-NEXT: lsr x12, x1, x9 212; CHECK-GI-NEXT: csel x8, x8, x14, lo 213; CHECK-GI-NEXT: tst x10, #0x7f 214; CHECK-GI-NEXT: csel x8, x0, x8, eq 215; CHECK-GI-NEXT: cmp x9, #64 216; CHECK-GI-NEXT: csel x9, x12, xzr, lo 217; CHECK-GI-NEXT: orr x0, x13, x8 218; CHECK-GI-NEXT: orr x1, x11, x9 219; CHECK-GI-NEXT: ret 220entry: 221 %d = call i128 @llvm.fshl(i128 %a, i128 %a, i128 %c) 222 ret i128 %d 223} 224 225define i128 @rotr_i128(i128 %a, i128 %c) { 226; CHECK-SD-LABEL: rotr_i128: 227; CHECK-SD: // %bb.0: // %entry 228; CHECK-SD-NEXT: tst x2, #0x40 229; CHECK-SD-NEXT: mvn w12, w2 230; CHECK-SD-NEXT: csel x8, x0, x1, eq 231; CHECK-SD-NEXT: csel x9, x1, x0, eq 232; CHECK-SD-NEXT: lsl x10, x9, #1 233; CHECK-SD-NEXT: lsl x11, x8, #1 234; CHECK-SD-NEXT: lsr x8, x8, x2 235; CHECK-SD-NEXT: lsr x9, x9, x2 236; CHECK-SD-NEXT: lsl x10, x10, x12 237; CHECK-SD-NEXT: lsl x11, x11, x12 238; CHECK-SD-NEXT: orr x0, x10, x8 239; CHECK-SD-NEXT: orr x1, x11, x9 240; CHECK-SD-NEXT: ret 241; 242; CHECK-GI-LABEL: rotr_i128: 243; CHECK-GI: // %bb.0: // %entry 244; CHECK-GI-NEXT: mov w8, #64 // =0x40 245; CHECK-GI-NEXT: and x9, x2, #0x7f 246; CHECK-GI-NEXT: neg x13, x2 247; CHECK-GI-NEXT: sub x10, x8, x9 248; CHECK-GI-NEXT: sub x11, x9, #64 249; CHECK-GI-NEXT: lsr x12, x0, x9 250; CHECK-GI-NEXT: lsl x10, x1, x10 251; CHECK-GI-NEXT: lsr x11, x1, x11 252; CHECK-GI-NEXT: and x14, x13, #0x7f 253; CHECK-GI-NEXT: cmp x9, #64 254; CHECK-GI-NEXT: sub x8, x8, x14 255; CHECK-GI-NEXT: lsl x15, x1, x14 256; CHECK-GI-NEXT: orr x10, x12, x10 257; CHECK-GI-NEXT: lsr x12, x1, x9 258; CHECK-GI-NEXT: lsr x8, x0, x8 259; CHECK-GI-NEXT: csel x10, x10, x11, lo 260; CHECK-GI-NEXT: sub x11, x14, #64 261; CHECK-GI-NEXT: tst x2, #0x7f 262; CHECK-GI-NEXT: csel x10, x0, x10, eq 263; CHECK-GI-NEXT: cmp x9, #64 264; CHECK-GI-NEXT: lsl x9, x0, x14 265; CHECK-GI-NEXT: lsl x11, x0, x11 266; CHECK-GI-NEXT: csel x12, x12, xzr, lo 267; CHECK-GI-NEXT: orr x8, x8, x15 268; CHECK-GI-NEXT: cmp x14, #64 269; CHECK-GI-NEXT: csel x9, x9, xzr, lo 270; CHECK-GI-NEXT: csel x8, x8, x11, lo 271; CHECK-GI-NEXT: tst x13, #0x7f 272; CHECK-GI-NEXT: csel x8, x1, x8, eq 273; CHECK-GI-NEXT: orr x0, x10, x9 274; CHECK-GI-NEXT: orr x1, x12, x8 275; CHECK-GI-NEXT: ret 276entry: 277 %d = call i128 @llvm.fshr(i128 %a, i128 %a, i128 %c) 278 ret i128 %d 279} 280 281define i8 @fshl_i8(i8 %a, i8 %b, i8 %c) { 282; CHECK-SD-LABEL: fshl_i8: 283; CHECK-SD: // %bb.0: // %entry 284; CHECK-SD-NEXT: and w8, w2, #0x7 285; CHECK-SD-NEXT: ubfiz w9, w1, #23, #8 286; CHECK-SD-NEXT: mvn w10, w8 287; CHECK-SD-NEXT: lsl w8, w0, w8 288; CHECK-SD-NEXT: lsr w9, w9, w10 289; CHECK-SD-NEXT: orr w0, w8, w9 290; CHECK-SD-NEXT: ret 291; 292; CHECK-GI-LABEL: fshl_i8: 293; CHECK-GI: // %bb.0: // %entry 294; CHECK-GI-NEXT: mov w8, #7 // =0x7 295; CHECK-GI-NEXT: ubfx w9, w1, #1, #7 296; CHECK-GI-NEXT: and w10, w2, #0x7 297; CHECK-GI-NEXT: bic w8, w8, w2 298; CHECK-GI-NEXT: lsl w10, w0, w10 299; CHECK-GI-NEXT: lsr w8, w9, w8 300; CHECK-GI-NEXT: orr w0, w10, w8 301; CHECK-GI-NEXT: ret 302entry: 303 %d = call i8 @llvm.fshl(i8 %a, i8 %b, i8 %c) 304 ret i8 %d 305} 306 307define i8 @fshr_i8(i8 %a, i8 %b, i8 %c) { 308; CHECK-SD-LABEL: fshr_i8: 309; CHECK-SD: // %bb.0: // %entry 310; CHECK-SD-NEXT: mov w8, #24 // =0x18 311; CHECK-SD-NEXT: lsl w9, w1, #24 312; CHECK-SD-NEXT: mvn w10, w2 313; CHECK-SD-NEXT: bfxil w8, w2, #0, #3 314; CHECK-SD-NEXT: lsl w11, w0, #1 315; CHECK-SD-NEXT: and x10, x10, #0x7 316; CHECK-SD-NEXT: lsr w8, w9, w8 317; CHECK-SD-NEXT: lsl w9, w11, w10 318; CHECK-SD-NEXT: orr w0, w9, w8 319; CHECK-SD-NEXT: ret 320; 321; CHECK-GI-LABEL: fshr_i8: 322; CHECK-GI: // %bb.0: // %entry 323; CHECK-GI-NEXT: mov w8, #7 // =0x7 324; CHECK-GI-NEXT: lsl w9, w0, #1 325; CHECK-GI-NEXT: and w10, w2, #0x7 326; CHECK-GI-NEXT: bic w8, w8, w2 327; CHECK-GI-NEXT: and w11, w1, #0xff 328; CHECK-GI-NEXT: lsl w8, w9, w8 329; CHECK-GI-NEXT: lsr w9, w11, w10 330; CHECK-GI-NEXT: orr w0, w8, w9 331; CHECK-GI-NEXT: ret 332entry: 333 %d = call i8 @llvm.fshr(i8 %a, i8 %b, i8 %c) 334 ret i8 %d 335} 336 337define i16 @fshl_i16(i16 %a, i16 %b, i16 %c) { 338; CHECK-SD-LABEL: fshl_i16: 339; CHECK-SD: // %bb.0: // %entry 340; CHECK-SD-NEXT: and w8, w2, #0xf 341; CHECK-SD-NEXT: ubfiz w9, w1, #15, #16 342; CHECK-SD-NEXT: mvn w10, w8 343; CHECK-SD-NEXT: lsl w8, w0, w8 344; CHECK-SD-NEXT: lsr w9, w9, w10 345; CHECK-SD-NEXT: orr w0, w8, w9 346; CHECK-SD-NEXT: ret 347; 348; CHECK-GI-LABEL: fshl_i16: 349; CHECK-GI: // %bb.0: // %entry 350; CHECK-GI-NEXT: mov w8, #15 // =0xf 351; CHECK-GI-NEXT: ubfx w9, w1, #1, #15 352; CHECK-GI-NEXT: and w10, w2, #0xf 353; CHECK-GI-NEXT: bic w8, w8, w2 354; CHECK-GI-NEXT: lsl w10, w0, w10 355; CHECK-GI-NEXT: lsr w8, w9, w8 356; CHECK-GI-NEXT: orr w0, w10, w8 357; CHECK-GI-NEXT: ret 358entry: 359 %d = call i16 @llvm.fshl(i16 %a, i16 %b, i16 %c) 360 ret i16 %d 361} 362 363define i16 @fshr_i16(i16 %a, i16 %b, i16 %c) { 364; CHECK-SD-LABEL: fshr_i16: 365; CHECK-SD: // %bb.0: // %entry 366; CHECK-SD-NEXT: mov w8, #16 // =0x10 367; CHECK-SD-NEXT: lsl w9, w1, #16 368; CHECK-SD-NEXT: mvn w10, w2 369; CHECK-SD-NEXT: bfxil w8, w2, #0, #4 370; CHECK-SD-NEXT: lsl w11, w0, #1 371; CHECK-SD-NEXT: and x10, x10, #0xf 372; CHECK-SD-NEXT: lsr w8, w9, w8 373; CHECK-SD-NEXT: lsl w9, w11, w10 374; CHECK-SD-NEXT: orr w0, w9, w8 375; CHECK-SD-NEXT: ret 376; 377; CHECK-GI-LABEL: fshr_i16: 378; CHECK-GI: // %bb.0: // %entry 379; CHECK-GI-NEXT: mov w8, #15 // =0xf 380; CHECK-GI-NEXT: lsl w9, w0, #1 381; CHECK-GI-NEXT: and w10, w2, #0xf 382; CHECK-GI-NEXT: bic w8, w8, w2 383; CHECK-GI-NEXT: and w11, w1, #0xffff 384; CHECK-GI-NEXT: lsl w8, w9, w8 385; CHECK-GI-NEXT: lsr w9, w11, w10 386; CHECK-GI-NEXT: orr w0, w8, w9 387; CHECK-GI-NEXT: ret 388entry: 389 %d = call i16 @llvm.fshr(i16 %a, i16 %b, i16 %c) 390 ret i16 %d 391} 392 393define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) { 394; CHECK-SD-LABEL: fshl_i32: 395; CHECK-SD: // %bb.0: // %entry 396; CHECK-SD-NEXT: lsr w8, w1, #1 397; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2 398; CHECK-SD-NEXT: mvn w9, w2 399; CHECK-SD-NEXT: lsl w10, w0, w2 400; CHECK-SD-NEXT: lsr w8, w8, w9 401; CHECK-SD-NEXT: orr w0, w10, w8 402; CHECK-SD-NEXT: ret 403; 404; CHECK-GI-LABEL: fshl_i32: 405; CHECK-GI: // %bb.0: // %entry 406; CHECK-GI-NEXT: mov w8, #31 // =0x1f 407; CHECK-GI-NEXT: lsr w9, w1, #1 408; CHECK-GI-NEXT: and w10, w2, #0x1f 409; CHECK-GI-NEXT: bic w8, w8, w2 410; CHECK-GI-NEXT: lsl w10, w0, w10 411; CHECK-GI-NEXT: lsr w8, w9, w8 412; CHECK-GI-NEXT: orr w0, w10, w8 413; CHECK-GI-NEXT: ret 414entry: 415 %d = call i32 @llvm.fshl(i32 %a, i32 %b, i32 %c) 416 ret i32 %d 417} 418 419define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) { 420; CHECK-SD-LABEL: fshr_i32: 421; CHECK-SD: // %bb.0: // %entry 422; CHECK-SD-NEXT: lsl w8, w0, #1 423; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2 424; CHECK-SD-NEXT: mvn w9, w2 425; CHECK-SD-NEXT: lsr w10, w1, w2 426; CHECK-SD-NEXT: lsl w8, w8, w9 427; CHECK-SD-NEXT: orr w0, w8, w10 428; CHECK-SD-NEXT: ret 429; 430; CHECK-GI-LABEL: fshr_i32: 431; CHECK-GI: // %bb.0: // %entry 432; CHECK-GI-NEXT: mov w8, #31 // =0x1f 433; CHECK-GI-NEXT: lsl w9, w0, #1 434; CHECK-GI-NEXT: and w10, w2, #0x1f 435; CHECK-GI-NEXT: bic w8, w8, w2 436; CHECK-GI-NEXT: lsl w8, w9, w8 437; CHECK-GI-NEXT: lsr w9, w1, w10 438; CHECK-GI-NEXT: orr w0, w8, w9 439; CHECK-GI-NEXT: ret 440entry: 441 %d = call i32 @llvm.fshr(i32 %a, i32 %b, i32 %c) 442 ret i32 %d 443} 444 445define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) { 446; CHECK-SD-LABEL: fshl_i64: 447; CHECK-SD: // %bb.0: // %entry 448; CHECK-SD-NEXT: lsr x8, x1, #1 449; CHECK-SD-NEXT: mvn w9, w2 450; CHECK-SD-NEXT: lsl x10, x0, x2 451; CHECK-SD-NEXT: lsr x8, x8, x9 452; CHECK-SD-NEXT: orr x0, x10, x8 453; CHECK-SD-NEXT: ret 454; 455; CHECK-GI-LABEL: fshl_i64: 456; CHECK-GI: // %bb.0: // %entry 457; CHECK-GI-NEXT: mov w8, #63 // =0x3f 458; CHECK-GI-NEXT: lsr x9, x1, #1 459; CHECK-GI-NEXT: and x10, x2, #0x3f 460; CHECK-GI-NEXT: bic x8, x8, x2 461; CHECK-GI-NEXT: lsl x10, x0, x10 462; CHECK-GI-NEXT: lsr x8, x9, x8 463; CHECK-GI-NEXT: orr x0, x10, x8 464; CHECK-GI-NEXT: ret 465entry: 466 %d = call i64 @llvm.fshl(i64 %a, i64 %b, i64 %c) 467 ret i64 %d 468} 469 470define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) { 471; CHECK-SD-LABEL: fshr_i64: 472; CHECK-SD: // %bb.0: // %entry 473; CHECK-SD-NEXT: lsl x8, x0, #1 474; CHECK-SD-NEXT: mvn w9, w2 475; CHECK-SD-NEXT: lsr x10, x1, x2 476; CHECK-SD-NEXT: lsl x8, x8, x9 477; CHECK-SD-NEXT: orr x0, x8, x10 478; CHECK-SD-NEXT: ret 479; 480; CHECK-GI-LABEL: fshr_i64: 481; CHECK-GI: // %bb.0: // %entry 482; CHECK-GI-NEXT: mov w8, #63 // =0x3f 483; CHECK-GI-NEXT: lsl x9, x0, #1 484; CHECK-GI-NEXT: and x10, x2, #0x3f 485; CHECK-GI-NEXT: bic x8, x8, x2 486; CHECK-GI-NEXT: lsl x8, x9, x8 487; CHECK-GI-NEXT: lsr x9, x1, x10 488; CHECK-GI-NEXT: orr x0, x8, x9 489; CHECK-GI-NEXT: ret 490entry: 491 %d = call i64 @llvm.fshr(i64 %a, i64 %b, i64 %c) 492 ret i64 %d 493} 494 495define i128 @fshl_i128(i128 %a, i128 %b, i128 %c) { 496; CHECK-SD-LABEL: fshl_i128: 497; CHECK-SD: // %bb.0: // %entry 498; CHECK-SD-NEXT: tst x4, #0x40 499; CHECK-SD-NEXT: mvn w11, w4 500; CHECK-SD-NEXT: csel x8, x3, x0, ne 501; CHECK-SD-NEXT: csel x9, x2, x3, ne 502; CHECK-SD-NEXT: csel x12, x0, x1, ne 503; CHECK-SD-NEXT: lsr x9, x9, #1 504; CHECK-SD-NEXT: lsr x10, x8, #1 505; CHECK-SD-NEXT: lsl x8, x8, x4 506; CHECK-SD-NEXT: lsl x12, x12, x4 507; CHECK-SD-NEXT: lsr x9, x9, x11 508; CHECK-SD-NEXT: lsr x10, x10, x11 509; CHECK-SD-NEXT: orr x0, x8, x9 510; CHECK-SD-NEXT: orr x1, x12, x10 511; CHECK-SD-NEXT: ret 512; 513; CHECK-GI-LABEL: fshl_i128: 514; CHECK-GI: // %bb.0: // %entry 515; CHECK-GI-NEXT: and x9, x4, #0x7f 516; CHECK-GI-NEXT: mov w10, #64 // =0x40 517; CHECK-GI-NEXT: lsl x14, x3, #63 518; CHECK-GI-NEXT: sub x12, x10, x9 519; CHECK-GI-NEXT: lsl x13, x1, x9 520; CHECK-GI-NEXT: mov w8, #127 // =0x7f 521; CHECK-GI-NEXT: lsr x12, x0, x12 522; CHECK-GI-NEXT: bic x8, x8, x4 523; CHECK-GI-NEXT: sub x15, x9, #64 524; CHECK-GI-NEXT: cmp x9, #64 525; CHECK-GI-NEXT: lsl x9, x0, x9 526; CHECK-GI-NEXT: lsl x15, x0, x15 527; CHECK-GI-NEXT: orr x12, x12, x13 528; CHECK-GI-NEXT: orr x13, x14, x2, lsr #1 529; CHECK-GI-NEXT: lsr x14, x3, #1 530; CHECK-GI-NEXT: sub x10, x10, x8 531; CHECK-GI-NEXT: sub x16, x8, #64 532; CHECK-GI-NEXT: csel x9, x9, xzr, lo 533; CHECK-GI-NEXT: lsr x17, x13, x8 534; CHECK-GI-NEXT: lsl x10, x14, x10 535; CHECK-GI-NEXT: csel x12, x12, x15, lo 536; CHECK-GI-NEXT: tst x4, #0x7f 537; CHECK-GI-NEXT: lsr x15, x14, x16 538; CHECK-GI-NEXT: mvn x11, x4 539; CHECK-GI-NEXT: csel x12, x1, x12, eq 540; CHECK-GI-NEXT: orr x10, x17, x10 541; CHECK-GI-NEXT: cmp x8, #64 542; CHECK-GI-NEXT: lsr x14, x14, x8 543; CHECK-GI-NEXT: csel x10, x10, x15, lo 544; CHECK-GI-NEXT: tst x11, #0x7f 545; CHECK-GI-NEXT: csel x10, x13, x10, eq 546; CHECK-GI-NEXT: cmp x8, #64 547; CHECK-GI-NEXT: csel x8, x14, xzr, lo 548; CHECK-GI-NEXT: orr x0, x9, x10 549; CHECK-GI-NEXT: orr x1, x12, x8 550; CHECK-GI-NEXT: ret 551entry: 552 %d = call i128 @llvm.fshl(i128 %a, i128 %b, i128 %c) 553 ret i128 %d 554} 555 556define i128 @fshr_i128(i128 %a, i128 %b, i128 %c) { 557; CHECK-SD-LABEL: fshr_i128: 558; CHECK-SD: // %bb.0: // %entry 559; CHECK-SD-NEXT: tst x4, #0x40 560; CHECK-SD-NEXT: mvn w12, w4 561; CHECK-SD-NEXT: csel x8, x3, x0, eq 562; CHECK-SD-NEXT: csel x9, x0, x1, eq 563; CHECK-SD-NEXT: csel x10, x2, x3, eq 564; CHECK-SD-NEXT: lsl x11, x8, #1 565; CHECK-SD-NEXT: lsl x9, x9, #1 566; CHECK-SD-NEXT: lsr x10, x10, x4 567; CHECK-SD-NEXT: lsr x8, x8, x4 568; CHECK-SD-NEXT: lsl x11, x11, x12 569; CHECK-SD-NEXT: lsl x9, x9, x12 570; CHECK-SD-NEXT: orr x0, x11, x10 571; CHECK-SD-NEXT: orr x1, x9, x8 572; CHECK-SD-NEXT: ret 573; 574; CHECK-GI-LABEL: fshr_i128: 575; CHECK-GI: // %bb.0: // %entry 576; CHECK-GI-NEXT: lsr x8, x0, #63 577; CHECK-GI-NEXT: mov w9, #127 // =0x7f 578; CHECK-GI-NEXT: mov w10, #64 // =0x40 579; CHECK-GI-NEXT: bic x9, x9, x4 580; CHECK-GI-NEXT: lsl x11, x0, #1 581; CHECK-GI-NEXT: and x12, x4, #0x7f 582; CHECK-GI-NEXT: orr x8, x8, x1, lsl #1 583; CHECK-GI-NEXT: sub x14, x10, x9 584; CHECK-GI-NEXT: sub x17, x9, #64 585; CHECK-GI-NEXT: lsl x15, x11, x9 586; CHECK-GI-NEXT: lsr x14, x11, x14 587; CHECK-GI-NEXT: cmp x9, #64 588; CHECK-GI-NEXT: lsl x16, x8, x9 589; CHECK-GI-NEXT: sub x9, x10, x12 590; CHECK-GI-NEXT: lsl x10, x11, x17 591; CHECK-GI-NEXT: mvn x13, x4 592; CHECK-GI-NEXT: csel x11, x15, xzr, lo 593; CHECK-GI-NEXT: sub x15, x12, #64 594; CHECK-GI-NEXT: orr x14, x14, x16 595; CHECK-GI-NEXT: lsr x16, x2, x12 596; CHECK-GI-NEXT: lsl x9, x3, x9 597; CHECK-GI-NEXT: csel x10, x14, x10, lo 598; CHECK-GI-NEXT: tst x13, #0x7f 599; CHECK-GI-NEXT: lsr x13, x3, x15 600; CHECK-GI-NEXT: csel x8, x8, x10, eq 601; CHECK-GI-NEXT: orr x9, x16, x9 602; CHECK-GI-NEXT: cmp x12, #64 603; CHECK-GI-NEXT: lsr x10, x3, x12 604; CHECK-GI-NEXT: csel x9, x9, x13, lo 605; CHECK-GI-NEXT: tst x4, #0x7f 606; CHECK-GI-NEXT: csel x9, x2, x9, eq 607; CHECK-GI-NEXT: cmp x12, #64 608; CHECK-GI-NEXT: csel x10, x10, xzr, lo 609; CHECK-GI-NEXT: orr x0, x11, x9 610; CHECK-GI-NEXT: orr x1, x8, x10 611; CHECK-GI-NEXT: ret 612entry: 613 %d = call i128 @llvm.fshr(i128 %a, i128 %b, i128 %c) 614 ret i128 %d 615} 616 617define i8 @rotl_i8_c(i8 %a) { 618; CHECK-LABEL: rotl_i8_c: 619; CHECK: // %bb.0: // %entry 620; CHECK-NEXT: ubfx w8, w0, #5, #3 621; CHECK-NEXT: orr w0, w8, w0, lsl #3 622; CHECK-NEXT: ret 623entry: 624 %d = call i8 @llvm.fshl(i8 %a, i8 %a, i8 3) 625 ret i8 %d 626} 627 628define i8 @rotr_i8_c(i8 %a) { 629; CHECK-SD-LABEL: rotr_i8_c: 630; CHECK-SD: // %bb.0: // %entry 631; CHECK-SD-NEXT: lsl w8, w0, #5 632; CHECK-SD-NEXT: bfxil w8, w0, #3, #5 633; CHECK-SD-NEXT: mov w0, w8 634; CHECK-SD-NEXT: ret 635; 636; CHECK-GI-LABEL: rotr_i8_c: 637; CHECK-GI: // %bb.0: // %entry 638; CHECK-GI-NEXT: ubfx w8, w0, #3, #5 639; CHECK-GI-NEXT: orr w0, w8, w0, lsl #5 640; CHECK-GI-NEXT: ret 641entry: 642 %d = call i8 @llvm.fshr(i8 %a, i8 %a, i8 3) 643 ret i8 %d 644} 645 646define i16 @rotl_i16_c(i16 %a) { 647; CHECK-LABEL: rotl_i16_c: 648; CHECK: // %bb.0: // %entry 649; CHECK-NEXT: ubfx w8, w0, #13, #3 650; CHECK-NEXT: orr w0, w8, w0, lsl #3 651; CHECK-NEXT: ret 652entry: 653 %d = call i16 @llvm.fshl(i16 %a, i16 %a, i16 3) 654 ret i16 %d 655} 656 657define i16 @rotr_i16_c(i16 %a) { 658; CHECK-SD-LABEL: rotr_i16_c: 659; CHECK-SD: // %bb.0: // %entry 660; CHECK-SD-NEXT: lsl w8, w0, #13 661; CHECK-SD-NEXT: bfxil w8, w0, #3, #13 662; CHECK-SD-NEXT: mov w0, w8 663; CHECK-SD-NEXT: ret 664; 665; CHECK-GI-LABEL: rotr_i16_c: 666; CHECK-GI: // %bb.0: // %entry 667; CHECK-GI-NEXT: ubfx w8, w0, #3, #13 668; CHECK-GI-NEXT: orr w0, w8, w0, lsl #13 669; CHECK-GI-NEXT: ret 670entry: 671 %d = call i16 @llvm.fshr(i16 %a, i16 %a, i16 3) 672 ret i16 %d 673} 674 675define i32 @rotl_i32_c(i32 %a) { 676; CHECK-LABEL: rotl_i32_c: 677; CHECK: // %bb.0: // %entry 678; CHECK-NEXT: ror w0, w0, #29 679; CHECK-NEXT: ret 680entry: 681 %d = call i32 @llvm.fshl(i32 %a, i32 %a, i32 3) 682 ret i32 %d 683} 684 685define i32 @rotr_i32_c(i32 %a) { 686; CHECK-LABEL: rotr_i32_c: 687; CHECK: // %bb.0: // %entry 688; CHECK-NEXT: ror w0, w0, #3 689; CHECK-NEXT: ret 690entry: 691 %d = call i32 @llvm.fshr(i32 %a, i32 %a, i32 3) 692 ret i32 %d 693} 694 695define i64 @rotl_i64_c(i64 %a) { 696; CHECK-LABEL: rotl_i64_c: 697; CHECK: // %bb.0: // %entry 698; CHECK-NEXT: ror x0, x0, #61 699; CHECK-NEXT: ret 700entry: 701 %d = call i64 @llvm.fshl(i64 %a, i64 %a, i64 3) 702 ret i64 %d 703} 704 705define i64 @rotr_i64_c(i64 %a) { 706; CHECK-LABEL: rotr_i64_c: 707; CHECK: // %bb.0: // %entry 708; CHECK-NEXT: ror x0, x0, #3 709; CHECK-NEXT: ret 710entry: 711 %d = call i64 @llvm.fshr(i64 %a, i64 %a, i64 3) 712 ret i64 %d 713} 714 715define i128 @rotl_i128_c(i128 %a) { 716; CHECK-SD-LABEL: rotl_i128_c: 717; CHECK-SD: // %bb.0: // %entry 718; CHECK-SD-NEXT: extr x8, x0, x1, #61 719; CHECK-SD-NEXT: extr x1, x1, x0, #61 720; CHECK-SD-NEXT: mov x0, x8 721; CHECK-SD-NEXT: ret 722; 723; CHECK-GI-LABEL: rotl_i128_c: 724; CHECK-GI: // %bb.0: // %entry 725; CHECK-GI-NEXT: lsr x8, x0, #61 726; CHECK-GI-NEXT: lsr x9, x1, #61 727; CHECK-GI-NEXT: orr x1, x8, x1, lsl #3 728; CHECK-GI-NEXT: orr x0, x9, x0, lsl #3 729; CHECK-GI-NEXT: ret 730entry: 731 %d = call i128 @llvm.fshl(i128 %a, i128 %a, i128 3) 732 ret i128 %d 733} 734 735define i128 @rotr_i128_c(i128 %a) { 736; CHECK-SD-LABEL: rotr_i128_c: 737; CHECK-SD: // %bb.0: // %entry 738; CHECK-SD-NEXT: extr x8, x1, x0, #3 739; CHECK-SD-NEXT: extr x1, x0, x1, #3 740; CHECK-SD-NEXT: mov x0, x8 741; CHECK-SD-NEXT: ret 742; 743; CHECK-GI-LABEL: rotr_i128_c: 744; CHECK-GI: // %bb.0: // %entry 745; CHECK-GI-NEXT: lsl x8, x1, #61 746; CHECK-GI-NEXT: lsl x9, x0, #61 747; CHECK-GI-NEXT: orr x0, x8, x0, lsr #3 748; CHECK-GI-NEXT: orr x1, x9, x1, lsr #3 749; CHECK-GI-NEXT: ret 750entry: 751 %d = call i128 @llvm.fshr(i128 %a, i128 %a, i128 3) 752 ret i128 %d 753} 754 755define i8 @fshl_i8_c(i8 %a, i8 %b) { 756; CHECK-SD-LABEL: fshl_i8_c: 757; CHECK-SD: // %bb.0: // %entry 758; CHECK-SD-NEXT: lsl w8, w1, #24 759; CHECK-SD-NEXT: extr w0, w0, w8, #29 760; CHECK-SD-NEXT: ret 761; 762; CHECK-GI-LABEL: fshl_i8_c: 763; CHECK-GI: // %bb.0: // %entry 764; CHECK-GI-NEXT: ubfx w8, w1, #5, #3 765; CHECK-GI-NEXT: orr w0, w8, w0, lsl #3 766; CHECK-GI-NEXT: ret 767entry: 768 %d = call i8 @llvm.fshl(i8 %a, i8 %b, i8 3) 769 ret i8 %d 770} 771 772define i8 @fshr_i8_c(i8 %a, i8 %b) { 773; CHECK-SD-LABEL: fshr_i8_c: 774; CHECK-SD: // %bb.0: // %entry 775; CHECK-SD-NEXT: lsl w8, w1, #24 776; CHECK-SD-NEXT: extr w0, w0, w8, #27 777; CHECK-SD-NEXT: ret 778; 779; CHECK-GI-LABEL: fshr_i8_c: 780; CHECK-GI: // %bb.0: // %entry 781; CHECK-GI-NEXT: ubfx w8, w1, #3, #5 782; CHECK-GI-NEXT: orr w0, w8, w0, lsl #5 783; CHECK-GI-NEXT: ret 784entry: 785 %d = call i8 @llvm.fshr(i8 %a, i8 %b, i8 3) 786 ret i8 %d 787} 788 789define i16 @fshl_i16_c(i16 %a, i16 %b) { 790; CHECK-SD-LABEL: fshl_i16_c: 791; CHECK-SD: // %bb.0: // %entry 792; CHECK-SD-NEXT: lsl w8, w1, #16 793; CHECK-SD-NEXT: extr w0, w0, w8, #29 794; CHECK-SD-NEXT: ret 795; 796; CHECK-GI-LABEL: fshl_i16_c: 797; CHECK-GI: // %bb.0: // %entry 798; CHECK-GI-NEXT: ubfx w8, w1, #13, #3 799; CHECK-GI-NEXT: orr w0, w8, w0, lsl #3 800; CHECK-GI-NEXT: ret 801entry: 802 %d = call i16 @llvm.fshl(i16 %a, i16 %b, i16 3) 803 ret i16 %d 804} 805 806define i16 @fshr_i16_c(i16 %a, i16 %b) { 807; CHECK-SD-LABEL: fshr_i16_c: 808; CHECK-SD: // %bb.0: // %entry 809; CHECK-SD-NEXT: lsl w8, w1, #16 810; CHECK-SD-NEXT: extr w0, w0, w8, #19 811; CHECK-SD-NEXT: ret 812; 813; CHECK-GI-LABEL: fshr_i16_c: 814; CHECK-GI: // %bb.0: // %entry 815; CHECK-GI-NEXT: ubfx w8, w1, #3, #13 816; CHECK-GI-NEXT: orr w0, w8, w0, lsl #13 817; CHECK-GI-NEXT: ret 818entry: 819 %d = call i16 @llvm.fshr(i16 %a, i16 %b, i16 3) 820 ret i16 %d 821} 822 823define i32 @fshl_i32_c(i32 %a, i32 %b) { 824; CHECK-LABEL: fshl_i32_c: 825; CHECK: // %bb.0: // %entry 826; CHECK-NEXT: extr w0, w0, w1, #29 827; CHECK-NEXT: ret 828entry: 829 %d = call i32 @llvm.fshl(i32 %a, i32 %b, i32 3) 830 ret i32 %d 831} 832 833define i32 @fshr_i32_c(i32 %a, i32 %b) { 834; CHECK-LABEL: fshr_i32_c: 835; CHECK: // %bb.0: // %entry 836; CHECK-NEXT: extr w0, w0, w1, #3 837; CHECK-NEXT: ret 838entry: 839 %d = call i32 @llvm.fshr(i32 %a, i32 %b, i32 3) 840 ret i32 %d 841} 842 843define i64 @fshl_i64_c(i64 %a, i64 %b) { 844; CHECK-LABEL: fshl_i64_c: 845; CHECK: // %bb.0: // %entry 846; CHECK-NEXT: extr x0, x0, x1, #61 847; CHECK-NEXT: ret 848entry: 849 %d = call i64 @llvm.fshl(i64 %a, i64 %b, i64 3) 850 ret i64 %d 851} 852 853define i64 @fshr_i64_c(i64 %a, i64 %b) { 854; CHECK-LABEL: fshr_i64_c: 855; CHECK: // %bb.0: // %entry 856; CHECK-NEXT: extr x0, x0, x1, #3 857; CHECK-NEXT: ret 858entry: 859 %d = call i64 @llvm.fshr(i64 %a, i64 %b, i64 3) 860 ret i64 %d 861} 862 863define i128 @fshl_i128_c(i128 %a, i128 %b) { 864; CHECK-SD-LABEL: fshl_i128_c: 865; CHECK-SD: // %bb.0: // %entry 866; CHECK-SD-NEXT: extr x8, x0, x3, #61 867; CHECK-SD-NEXT: extr x1, x1, x0, #61 868; CHECK-SD-NEXT: mov x0, x8 869; CHECK-SD-NEXT: ret 870; 871; CHECK-GI-LABEL: fshl_i128_c: 872; CHECK-GI: // %bb.0: // %entry 873; CHECK-GI-NEXT: lsr x8, x0, #61 874; CHECK-GI-NEXT: lsr x9, x3, #61 875; CHECK-GI-NEXT: orr x1, x8, x1, lsl #3 876; CHECK-GI-NEXT: orr x0, x9, x0, lsl #3 877; CHECK-GI-NEXT: ret 878entry: 879 %d = call i128 @llvm.fshl(i128 %a, i128 %b, i128 3) 880 ret i128 %d 881} 882 883define i128 @fshr_i128_c(i128 %a, i128 %b) { 884; CHECK-SD-LABEL: fshr_i128_c: 885; CHECK-SD: // %bb.0: // %entry 886; CHECK-SD-NEXT: extr x8, x3, x2, #3 887; CHECK-SD-NEXT: extr x1, x0, x3, #3 888; CHECK-SD-NEXT: mov x0, x8 889; CHECK-SD-NEXT: ret 890; 891; CHECK-GI-LABEL: fshr_i128_c: 892; CHECK-GI: // %bb.0: // %entry 893; CHECK-GI-NEXT: lsl x8, x3, #61 894; CHECK-GI-NEXT: lsr x9, x3, #3 895; CHECK-GI-NEXT: orr x8, x8, x2, lsr #3 896; CHECK-GI-NEXT: orr x1, x9, x0, lsl #61 897; CHECK-GI-NEXT: mov x0, x8 898; CHECK-GI-NEXT: ret 899entry: 900 %d = call i128 @llvm.fshr(i128 %a, i128 %b, i128 3) 901 ret i128 %d 902} 903 904define <8 x i8> @rotl_v8i8(<8 x i8> %a, <8 x i8> %c) { 905; CHECK-LABEL: rotl_v8i8: 906; CHECK: // %bb.0: // %entry 907; CHECK-NEXT: movi v2.8b, #7 908; CHECK-NEXT: neg v3.8b, v1.8b 909; CHECK-NEXT: and v3.8b, v3.8b, v2.8b 910; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 911; CHECK-NEXT: neg v2.8b, v3.8b 912; CHECK-NEXT: ushl v1.8b, v0.8b, v1.8b 913; CHECK-NEXT: ushl v0.8b, v0.8b, v2.8b 914; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b 915; CHECK-NEXT: ret 916entry: 917 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %a, <8 x i8> %c) 918 ret <8 x i8> %d 919} 920 921define <8 x i8> @rotr_v8i8(<8 x i8> %a, <8 x i8> %c) { 922; CHECK-SD-LABEL: rotr_v8i8: 923; CHECK-SD: // %bb.0: // %entry 924; CHECK-SD-NEXT: movi v2.8b, #7 925; CHECK-SD-NEXT: neg v3.8b, v1.8b 926; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 927; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b 928; CHECK-SD-NEXT: neg v1.8b, v1.8b 929; CHECK-SD-NEXT: ushl v2.8b, v0.8b, v2.8b 930; CHECK-SD-NEXT: ushl v0.8b, v0.8b, v1.8b 931; CHECK-SD-NEXT: orr v0.8b, v0.8b, v2.8b 932; CHECK-SD-NEXT: ret 933; 934; CHECK-GI-LABEL: rotr_v8i8: 935; CHECK-GI: // %bb.0: // %entry 936; CHECK-GI-NEXT: movi v2.8b, #7 937; CHECK-GI-NEXT: neg v3.8b, v1.8b 938; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 939; CHECK-GI-NEXT: and v2.8b, v3.8b, v2.8b 940; CHECK-GI-NEXT: neg v1.8b, v1.8b 941; CHECK-GI-NEXT: ushl v1.8b, v0.8b, v1.8b 942; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v2.8b 943; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 944; CHECK-GI-NEXT: ret 945entry: 946 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %a, <8 x i8> %c) 947 ret <8 x i8> %d 948} 949 950define <16 x i8> @rotl_v16i8(<16 x i8> %a, <16 x i8> %c) { 951; CHECK-LABEL: rotl_v16i8: 952; CHECK: // %bb.0: // %entry 953; CHECK-NEXT: movi v2.16b, #7 954; CHECK-NEXT: neg v3.16b, v1.16b 955; CHECK-NEXT: and v3.16b, v3.16b, v2.16b 956; CHECK-NEXT: and v1.16b, v1.16b, v2.16b 957; CHECK-NEXT: neg v2.16b, v3.16b 958; CHECK-NEXT: ushl v1.16b, v0.16b, v1.16b 959; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b 960; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b 961; CHECK-NEXT: ret 962entry: 963 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %a, <16 x i8> %c) 964 ret <16 x i8> %d 965} 966 967define <16 x i8> @rotr_v16i8(<16 x i8> %a, <16 x i8> %c) { 968; CHECK-SD-LABEL: rotr_v16i8: 969; CHECK-SD: // %bb.0: // %entry 970; CHECK-SD-NEXT: movi v2.16b, #7 971; CHECK-SD-NEXT: neg v3.16b, v1.16b 972; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 973; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b 974; CHECK-SD-NEXT: neg v1.16b, v1.16b 975; CHECK-SD-NEXT: ushl v2.16b, v0.16b, v2.16b 976; CHECK-SD-NEXT: ushl v0.16b, v0.16b, v1.16b 977; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 978; CHECK-SD-NEXT: ret 979; 980; CHECK-GI-LABEL: rotr_v16i8: 981; CHECK-GI: // %bb.0: // %entry 982; CHECK-GI-NEXT: movi v2.16b, #7 983; CHECK-GI-NEXT: neg v3.16b, v1.16b 984; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b 985; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b 986; CHECK-GI-NEXT: neg v1.16b, v1.16b 987; CHECK-GI-NEXT: ushl v1.16b, v0.16b, v1.16b 988; CHECK-GI-NEXT: ushl v0.16b, v0.16b, v2.16b 989; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 990; CHECK-GI-NEXT: ret 991entry: 992 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %a, <16 x i8> %c) 993 ret <16 x i8> %d 994} 995 996define <4 x i16> @rotl_v4i16(<4 x i16> %a, <4 x i16> %c) { 997; CHECK-LABEL: rotl_v4i16: 998; CHECK: // %bb.0: // %entry 999; CHECK-NEXT: movi v2.4h, #15 1000; CHECK-NEXT: neg v3.4h, v1.4h 1001; CHECK-NEXT: and v3.8b, v3.8b, v2.8b 1002; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 1003; CHECK-NEXT: neg v2.4h, v3.4h 1004; CHECK-NEXT: ushl v1.4h, v0.4h, v1.4h 1005; CHECK-NEXT: ushl v0.4h, v0.4h, v2.4h 1006; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b 1007; CHECK-NEXT: ret 1008entry: 1009 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %a, <4 x i16> %c) 1010 ret <4 x i16> %d 1011} 1012 1013define <4 x i16> @rotr_v4i16(<4 x i16> %a, <4 x i16> %c) { 1014; CHECK-SD-LABEL: rotr_v4i16: 1015; CHECK-SD: // %bb.0: // %entry 1016; CHECK-SD-NEXT: movi v2.4h, #15 1017; CHECK-SD-NEXT: neg v3.4h, v1.4h 1018; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 1019; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b 1020; CHECK-SD-NEXT: neg v1.4h, v1.4h 1021; CHECK-SD-NEXT: ushl v2.4h, v0.4h, v2.4h 1022; CHECK-SD-NEXT: ushl v0.4h, v0.4h, v1.4h 1023; CHECK-SD-NEXT: orr v0.8b, v0.8b, v2.8b 1024; CHECK-SD-NEXT: ret 1025; 1026; CHECK-GI-LABEL: rotr_v4i16: 1027; CHECK-GI: // %bb.0: // %entry 1028; CHECK-GI-NEXT: movi v2.4h, #15 1029; CHECK-GI-NEXT: neg v3.4h, v1.4h 1030; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 1031; CHECK-GI-NEXT: and v2.8b, v3.8b, v2.8b 1032; CHECK-GI-NEXT: neg v1.4h, v1.4h 1033; CHECK-GI-NEXT: ushl v1.4h, v0.4h, v1.4h 1034; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v2.4h 1035; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 1036; CHECK-GI-NEXT: ret 1037entry: 1038 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %a, <4 x i16> %c) 1039 ret <4 x i16> %d 1040} 1041 1042define <7 x i16> @rotl_v7i16(<7 x i16> %a, <7 x i16> %c) { 1043; CHECK-SD-LABEL: rotl_v7i16: 1044; CHECK-SD: // %bb.0: // %entry 1045; CHECK-SD-NEXT: movi v2.8h, #15 1046; CHECK-SD-NEXT: neg v3.8h, v1.8h 1047; CHECK-SD-NEXT: and v3.16b, v3.16b, v2.16b 1048; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 1049; CHECK-SD-NEXT: neg v2.8h, v3.8h 1050; CHECK-SD-NEXT: ushl v1.8h, v0.8h, v1.8h 1051; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 1052; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b 1053; CHECK-SD-NEXT: ret 1054; 1055; CHECK-GI-LABEL: rotl_v7i16: 1056; CHECK-GI: // %bb.0: // %entry 1057; CHECK-GI-NEXT: mov w8, #0 // =0x0 1058; CHECK-GI-NEXT: mov w9, #15 // =0xf 1059; CHECK-GI-NEXT: fmov s2, w8 1060; CHECK-GI-NEXT: fmov s3, w9 1061; CHECK-GI-NEXT: mov v2.h[1], w8 1062; CHECK-GI-NEXT: mov v3.h[1], w9 1063; CHECK-GI-NEXT: mov v2.h[2], w8 1064; CHECK-GI-NEXT: mov v3.h[2], w9 1065; CHECK-GI-NEXT: mov v2.h[3], w8 1066; CHECK-GI-NEXT: mov v3.h[3], w9 1067; CHECK-GI-NEXT: mov v2.h[4], w8 1068; CHECK-GI-NEXT: mov v3.h[4], w9 1069; CHECK-GI-NEXT: mov v2.h[5], w8 1070; CHECK-GI-NEXT: mov v3.h[5], w9 1071; CHECK-GI-NEXT: mov v2.h[6], w8 1072; CHECK-GI-NEXT: mov v3.h[6], w9 1073; CHECK-GI-NEXT: sub v2.8h, v2.8h, v1.8h 1074; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 1075; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b 1076; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h 1077; CHECK-GI-NEXT: neg v2.8h, v2.8h 1078; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 1079; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 1080; CHECK-GI-NEXT: ret 1081entry: 1082 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %a, <7 x i16> %c) 1083 ret <7 x i16> %d 1084} 1085 1086define <7 x i16> @rotr_v7i16(<7 x i16> %a, <7 x i16> %c) { 1087; CHECK-SD-LABEL: rotr_v7i16: 1088; CHECK-SD: // %bb.0: // %entry 1089; CHECK-SD-NEXT: movi v2.8h, #15 1090; CHECK-SD-NEXT: neg v3.8h, v1.8h 1091; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 1092; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b 1093; CHECK-SD-NEXT: neg v1.8h, v1.8h 1094; CHECK-SD-NEXT: ushl v2.8h, v0.8h, v2.8h 1095; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v1.8h 1096; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1097; CHECK-SD-NEXT: ret 1098; 1099; CHECK-GI-LABEL: rotr_v7i16: 1100; CHECK-GI: // %bb.0: // %entry 1101; CHECK-GI-NEXT: mov w8, #0 // =0x0 1102; CHECK-GI-NEXT: mov w9, #15 // =0xf 1103; CHECK-GI-NEXT: fmov s2, w8 1104; CHECK-GI-NEXT: fmov s3, w9 1105; CHECK-GI-NEXT: mov v2.h[1], w8 1106; CHECK-GI-NEXT: mov v3.h[1], w9 1107; CHECK-GI-NEXT: mov v2.h[2], w8 1108; CHECK-GI-NEXT: mov v3.h[2], w9 1109; CHECK-GI-NEXT: mov v2.h[3], w8 1110; CHECK-GI-NEXT: mov v3.h[3], w9 1111; CHECK-GI-NEXT: mov v2.h[4], w8 1112; CHECK-GI-NEXT: mov v3.h[4], w9 1113; CHECK-GI-NEXT: mov v2.h[5], w8 1114; CHECK-GI-NEXT: mov v3.h[5], w9 1115; CHECK-GI-NEXT: mov v2.h[6], w8 1116; CHECK-GI-NEXT: mov v3.h[6], w9 1117; CHECK-GI-NEXT: sub v2.8h, v2.8h, v1.8h 1118; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 1119; CHECK-GI-NEXT: neg v1.8h, v1.8h 1120; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b 1121; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h 1122; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 1123; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 1124; CHECK-GI-NEXT: ret 1125entry: 1126 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %a, <7 x i16> %c) 1127 ret <7 x i16> %d 1128} 1129 1130define <8 x i16> @rotl_v8i16(<8 x i16> %a, <8 x i16> %c) { 1131; CHECK-LABEL: rotl_v8i16: 1132; CHECK: // %bb.0: // %entry 1133; CHECK-NEXT: movi v2.8h, #15 1134; CHECK-NEXT: neg v3.8h, v1.8h 1135; CHECK-NEXT: and v3.16b, v3.16b, v2.16b 1136; CHECK-NEXT: and v1.16b, v1.16b, v2.16b 1137; CHECK-NEXT: neg v2.8h, v3.8h 1138; CHECK-NEXT: ushl v1.8h, v0.8h, v1.8h 1139; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h 1140; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b 1141; CHECK-NEXT: ret 1142entry: 1143 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %a, <8 x i16> %c) 1144 ret <8 x i16> %d 1145} 1146 1147define <8 x i16> @rotr_v8i16(<8 x i16> %a, <8 x i16> %c) { 1148; CHECK-SD-LABEL: rotr_v8i16: 1149; CHECK-SD: // %bb.0: // %entry 1150; CHECK-SD-NEXT: movi v2.8h, #15 1151; CHECK-SD-NEXT: neg v3.8h, v1.8h 1152; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 1153; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b 1154; CHECK-SD-NEXT: neg v1.8h, v1.8h 1155; CHECK-SD-NEXT: ushl v2.8h, v0.8h, v2.8h 1156; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v1.8h 1157; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1158; CHECK-SD-NEXT: ret 1159; 1160; CHECK-GI-LABEL: rotr_v8i16: 1161; CHECK-GI: // %bb.0: // %entry 1162; CHECK-GI-NEXT: movi v2.8h, #15 1163; CHECK-GI-NEXT: neg v3.8h, v1.8h 1164; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b 1165; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b 1166; CHECK-GI-NEXT: neg v1.8h, v1.8h 1167; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h 1168; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 1169; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 1170; CHECK-GI-NEXT: ret 1171entry: 1172 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %a, <8 x i16> %c) 1173 ret <8 x i16> %d 1174} 1175 1176define <16 x i16> @rotl_v16i16(<16 x i16> %a, <16 x i16> %c) { 1177; CHECK-LABEL: rotl_v16i16: 1178; CHECK: // %bb.0: // %entry 1179; CHECK-NEXT: movi v4.8h, #15 1180; CHECK-NEXT: neg v5.8h, v2.8h 1181; CHECK-NEXT: neg v6.8h, v3.8h 1182; CHECK-NEXT: and v5.16b, v5.16b, v4.16b 1183; CHECK-NEXT: and v6.16b, v6.16b, v4.16b 1184; CHECK-NEXT: and v2.16b, v2.16b, v4.16b 1185; CHECK-NEXT: and v3.16b, v3.16b, v4.16b 1186; CHECK-NEXT: neg v4.8h, v5.8h 1187; CHECK-NEXT: neg v5.8h, v6.8h 1188; CHECK-NEXT: ushl v2.8h, v0.8h, v2.8h 1189; CHECK-NEXT: ushl v3.8h, v1.8h, v3.8h 1190; CHECK-NEXT: ushl v0.8h, v0.8h, v4.8h 1191; CHECK-NEXT: ushl v1.8h, v1.8h, v5.8h 1192; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b 1193; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b 1194; CHECK-NEXT: ret 1195entry: 1196 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %a, <16 x i16> %c) 1197 ret <16 x i16> %d 1198} 1199 1200define <16 x i16> @rotr_v16i16(<16 x i16> %a, <16 x i16> %c) { 1201; CHECK-SD-LABEL: rotr_v16i16: 1202; CHECK-SD: // %bb.0: // %entry 1203; CHECK-SD-NEXT: movi v4.8h, #15 1204; CHECK-SD-NEXT: neg v5.8h, v2.8h 1205; CHECK-SD-NEXT: neg v6.8h, v3.8h 1206; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b 1207; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b 1208; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b 1209; CHECK-SD-NEXT: and v4.16b, v6.16b, v4.16b 1210; CHECK-SD-NEXT: neg v2.8h, v2.8h 1211; CHECK-SD-NEXT: neg v3.8h, v3.8h 1212; CHECK-SD-NEXT: ushl v5.8h, v0.8h, v5.8h 1213; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 1214; CHECK-SD-NEXT: ushl v2.8h, v1.8h, v4.8h 1215; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h 1216; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b 1217; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b 1218; CHECK-SD-NEXT: ret 1219; 1220; CHECK-GI-LABEL: rotr_v16i16: 1221; CHECK-GI: // %bb.0: // %entry 1222; CHECK-GI-NEXT: movi v4.8h, #15 1223; CHECK-GI-NEXT: neg v6.8h, v3.8h 1224; CHECK-GI-NEXT: and v5.16b, v2.16b, v4.16b 1225; CHECK-GI-NEXT: neg v2.8h, v2.8h 1226; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b 1227; CHECK-GI-NEXT: neg v5.8h, v5.8h 1228; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b 1229; CHECK-GI-NEXT: and v4.16b, v6.16b, v4.16b 1230; CHECK-GI-NEXT: neg v3.8h, v3.8h 1231; CHECK-GI-NEXT: ushl v5.8h, v0.8h, v5.8h 1232; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 1233; CHECK-GI-NEXT: ushl v3.8h, v1.8h, v3.8h 1234; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v4.8h 1235; CHECK-GI-NEXT: orr v0.16b, v5.16b, v0.16b 1236; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 1237; CHECK-GI-NEXT: ret 1238entry: 1239 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %a, <16 x i16> %c) 1240 ret <16 x i16> %d 1241} 1242 1243define <2 x i32> @rotl_v2i32(<2 x i32> %a, <2 x i32> %c) { 1244; CHECK-LABEL: rotl_v2i32: 1245; CHECK: // %bb.0: // %entry 1246; CHECK-NEXT: movi v2.2s, #31 1247; CHECK-NEXT: neg v3.2s, v1.2s 1248; CHECK-NEXT: and v3.8b, v3.8b, v2.8b 1249; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 1250; CHECK-NEXT: neg v2.2s, v3.2s 1251; CHECK-NEXT: ushl v1.2s, v0.2s, v1.2s 1252; CHECK-NEXT: ushl v0.2s, v0.2s, v2.2s 1253; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b 1254; CHECK-NEXT: ret 1255entry: 1256 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %a, <2 x i32> %c) 1257 ret <2 x i32> %d 1258} 1259 1260define <2 x i32> @rotr_v2i32(<2 x i32> %a, <2 x i32> %c) { 1261; CHECK-SD-LABEL: rotr_v2i32: 1262; CHECK-SD: // %bb.0: // %entry 1263; CHECK-SD-NEXT: movi v2.2s, #31 1264; CHECK-SD-NEXT: neg v3.2s, v1.2s 1265; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b 1266; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b 1267; CHECK-SD-NEXT: neg v1.2s, v1.2s 1268; CHECK-SD-NEXT: ushl v2.2s, v0.2s, v2.2s 1269; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s 1270; CHECK-SD-NEXT: orr v0.8b, v0.8b, v2.8b 1271; CHECK-SD-NEXT: ret 1272; 1273; CHECK-GI-LABEL: rotr_v2i32: 1274; CHECK-GI: // %bb.0: // %entry 1275; CHECK-GI-NEXT: movi v2.2s, #31 1276; CHECK-GI-NEXT: neg v3.2s, v1.2s 1277; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b 1278; CHECK-GI-NEXT: and v2.8b, v3.8b, v2.8b 1279; CHECK-GI-NEXT: neg v1.2s, v1.2s 1280; CHECK-GI-NEXT: ushl v1.2s, v0.2s, v1.2s 1281; CHECK-GI-NEXT: ushl v0.2s, v0.2s, v2.2s 1282; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 1283; CHECK-GI-NEXT: ret 1284entry: 1285 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %a, <2 x i32> %c) 1286 ret <2 x i32> %d 1287} 1288 1289define <4 x i32> @rotl_v4i32(<4 x i32> %a, <4 x i32> %c) { 1290; CHECK-LABEL: rotl_v4i32: 1291; CHECK: // %bb.0: // %entry 1292; CHECK-NEXT: movi v2.4s, #31 1293; CHECK-NEXT: neg v3.4s, v1.4s 1294; CHECK-NEXT: and v3.16b, v3.16b, v2.16b 1295; CHECK-NEXT: and v1.16b, v1.16b, v2.16b 1296; CHECK-NEXT: neg v2.4s, v3.4s 1297; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s 1298; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s 1299; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b 1300; CHECK-NEXT: ret 1301entry: 1302 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %a, <4 x i32> %c) 1303 ret <4 x i32> %d 1304} 1305 1306define <4 x i32> @rotr_v4i32(<4 x i32> %a, <4 x i32> %c) { 1307; CHECK-SD-LABEL: rotr_v4i32: 1308; CHECK-SD: // %bb.0: // %entry 1309; CHECK-SD-NEXT: movi v2.4s, #31 1310; CHECK-SD-NEXT: neg v3.4s, v1.4s 1311; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 1312; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b 1313; CHECK-SD-NEXT: neg v1.4s, v1.4s 1314; CHECK-SD-NEXT: ushl v2.4s, v0.4s, v2.4s 1315; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s 1316; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1317; CHECK-SD-NEXT: ret 1318; 1319; CHECK-GI-LABEL: rotr_v4i32: 1320; CHECK-GI: // %bb.0: // %entry 1321; CHECK-GI-NEXT: movi v2.4s, #31 1322; CHECK-GI-NEXT: neg v3.4s, v1.4s 1323; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b 1324; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b 1325; CHECK-GI-NEXT: neg v1.4s, v1.4s 1326; CHECK-GI-NEXT: ushl v1.4s, v0.4s, v1.4s 1327; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s 1328; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 1329; CHECK-GI-NEXT: ret 1330entry: 1331 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %a, <4 x i32> %c) 1332 ret <4 x i32> %d 1333} 1334 1335define <7 x i32> @rotl_v7i32(<7 x i32> %a, <7 x i32> %c) { 1336; CHECK-SD-LABEL: rotl_v7i32: 1337; CHECK-SD: // %bb.0: // %entry 1338; CHECK-SD-NEXT: fmov s0, w7 1339; CHECK-SD-NEXT: mov x8, sp 1340; CHECK-SD-NEXT: ldr s1, [sp, #24] 1341; CHECK-SD-NEXT: fmov s2, w0 1342; CHECK-SD-NEXT: add x9, sp, #40 1343; CHECK-SD-NEXT: fmov s5, w4 1344; CHECK-SD-NEXT: movi v3.4s, #31 1345; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8] 1346; CHECK-SD-NEXT: add x8, sp, #8 1347; CHECK-SD-NEXT: mov v2.s[1], w1 1348; CHECK-SD-NEXT: mov v5.s[1], w5 1349; CHECK-SD-NEXT: ld1 { v0.s }[2], [x8] 1350; CHECK-SD-NEXT: add x8, sp, #32 1351; CHECK-SD-NEXT: ld1 { v1.s }[1], [x8] 1352; CHECK-SD-NEXT: add x8, sp, #16 1353; CHECK-SD-NEXT: mov v2.s[2], w2 1354; CHECK-SD-NEXT: mov v5.s[2], w6 1355; CHECK-SD-NEXT: ld1 { v0.s }[3], [x8] 1356; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9] 1357; CHECK-SD-NEXT: neg v4.4s, v0.4s 1358; CHECK-SD-NEXT: mov v2.s[3], w3 1359; CHECK-SD-NEXT: and v0.16b, v0.16b, v3.16b 1360; CHECK-SD-NEXT: neg v6.4s, v1.4s 1361; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b 1362; CHECK-SD-NEXT: and v4.16b, v4.16b, v3.16b 1363; CHECK-SD-NEXT: and v6.16b, v6.16b, v3.16b 1364; CHECK-SD-NEXT: ushl v0.4s, v2.4s, v0.4s 1365; CHECK-SD-NEXT: ushl v1.4s, v5.4s, v1.4s 1366; CHECK-SD-NEXT: neg v4.4s, v4.4s 1367; CHECK-SD-NEXT: neg v3.4s, v6.4s 1368; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v4.4s 1369; CHECK-SD-NEXT: ushl v3.4s, v5.4s, v3.4s 1370; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1371; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 1372; CHECK-SD-NEXT: mov w1, v0.s[1] 1373; CHECK-SD-NEXT: mov w2, v0.s[2] 1374; CHECK-SD-NEXT: mov w3, v0.s[3] 1375; CHECK-SD-NEXT: mov w5, v1.s[1] 1376; CHECK-SD-NEXT: mov w6, v1.s[2] 1377; CHECK-SD-NEXT: fmov w0, s0 1378; CHECK-SD-NEXT: fmov w4, s1 1379; CHECK-SD-NEXT: ret 1380; 1381; CHECK-GI-LABEL: rotl_v7i32: 1382; CHECK-GI: // %bb.0: // %entry 1383; CHECK-GI-NEXT: mov v1.s[0], w7 1384; CHECK-GI-NEXT: ldr s0, [sp, #24] 1385; CHECK-GI-NEXT: mov v2.s[0], wzr 1386; CHECK-GI-NEXT: mov v3.s[0], w7 1387; CHECK-GI-NEXT: mov x9, sp 1388; CHECK-GI-NEXT: ldr s5, [sp, #32] 1389; CHECK-GI-NEXT: mov v4.16b, v0.16b 1390; CHECK-GI-NEXT: mov w8, #31 // =0x1f 1391; CHECK-GI-NEXT: ldr s7, [sp] 1392; CHECK-GI-NEXT: mov v16.s[0], w8 1393; CHECK-GI-NEXT: mov v6.s[0], w0 1394; CHECK-GI-NEXT: ldr s18, [sp, #40] 1395; CHECK-GI-NEXT: ld1 { v1.s }[1], [x9] 1396; CHECK-GI-NEXT: mov v2.s[1], wzr 1397; CHECK-GI-NEXT: add x9, sp, #8 1398; CHECK-GI-NEXT: mov v4.s[1], v5.s[0] 1399; CHECK-GI-NEXT: mov v3.s[1], v7.s[0] 1400; CHECK-GI-NEXT: mov v7.s[0], w0 1401; CHECK-GI-NEXT: mov v19.s[0], w8 1402; CHECK-GI-NEXT: ldr s17, [sp, #8] 1403; CHECK-GI-NEXT: mov v20.s[0], w4 1404; CHECK-GI-NEXT: ld1 { v1.s }[2], [x9] 1405; CHECK-GI-NEXT: mov v16.s[1], w8 1406; CHECK-GI-NEXT: add x9, sp, #16 1407; CHECK-GI-NEXT: mov v2.s[2], wzr 1408; CHECK-GI-NEXT: mov v6.s[1], w1 1409; CHECK-GI-NEXT: mov v21.s[0], w4 1410; CHECK-GI-NEXT: mov v4.s[2], v18.s[0] 1411; CHECK-GI-NEXT: mov v7.s[1], w1 1412; CHECK-GI-NEXT: mov v3.s[2], v17.s[0] 1413; CHECK-GI-NEXT: ld1 { v1.s }[3], [x9] 1414; CHECK-GI-NEXT: mov v0.s[1], v5.s[0] 1415; CHECK-GI-NEXT: mov v19.s[1], w8 1416; CHECK-GI-NEXT: movi v5.4s, #31 1417; CHECK-GI-NEXT: mov v16.s[2], w8 1418; CHECK-GI-NEXT: ldr s17, [sp, #16] 1419; CHECK-GI-NEXT: mov v6.s[2], w2 1420; CHECK-GI-NEXT: mov v20.s[1], w5 1421; CHECK-GI-NEXT: mov v21.s[1], w5 1422; CHECK-GI-NEXT: sub v2.4s, v2.4s, v4.4s 1423; CHECK-GI-NEXT: neg v1.4s, v1.4s 1424; CHECK-GI-NEXT: mov v7.s[2], w2 1425; CHECK-GI-NEXT: mov v3.s[3], v17.s[0] 1426; CHECK-GI-NEXT: mov v0.s[2], v18.s[0] 1427; CHECK-GI-NEXT: mov v19.s[2], w8 1428; CHECK-GI-NEXT: and v1.16b, v1.16b, v5.16b 1429; CHECK-GI-NEXT: and v2.16b, v2.16b, v16.16b 1430; CHECK-GI-NEXT: mov v6.s[3], w3 1431; CHECK-GI-NEXT: mov v7.s[3], w3 1432; CHECK-GI-NEXT: mov v20.s[2], w6 1433; CHECK-GI-NEXT: mov v21.s[2], w6 1434; CHECK-GI-NEXT: and v3.16b, v3.16b, v5.16b 1435; CHECK-GI-NEXT: and v0.16b, v0.16b, v19.16b 1436; CHECK-GI-NEXT: neg v1.4s, v1.4s 1437; CHECK-GI-NEXT: neg v2.4s, v2.4s 1438; CHECK-GI-NEXT: ushl v3.4s, v6.4s, v3.4s 1439; CHECK-GI-NEXT: ushl v0.4s, v20.4s, v0.4s 1440; CHECK-GI-NEXT: ushl v1.4s, v7.4s, v1.4s 1441; CHECK-GI-NEXT: ushl v2.4s, v21.4s, v2.4s 1442; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 1443; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 1444; CHECK-GI-NEXT: mov s2, v1.s[1] 1445; CHECK-GI-NEXT: mov s3, v1.s[2] 1446; CHECK-GI-NEXT: mov s4, v1.s[3] 1447; CHECK-GI-NEXT: mov s5, v0.s[1] 1448; CHECK-GI-NEXT: mov s6, v0.s[2] 1449; CHECK-GI-NEXT: fmov w0, s1 1450; CHECK-GI-NEXT: fmov w4, s0 1451; CHECK-GI-NEXT: fmov w1, s2 1452; CHECK-GI-NEXT: fmov w2, s3 1453; CHECK-GI-NEXT: fmov w3, s4 1454; CHECK-GI-NEXT: fmov w5, s5 1455; CHECK-GI-NEXT: fmov w6, s6 1456; CHECK-GI-NEXT: ret 1457entry: 1458 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %a, <7 x i32> %c) 1459 ret <7 x i32> %d 1460} 1461 1462define <7 x i32> @rotr_v7i32(<7 x i32> %a, <7 x i32> %c) { 1463; CHECK-SD-LABEL: rotr_v7i32: 1464; CHECK-SD: // %bb.0: // %entry 1465; CHECK-SD-NEXT: fmov s0, w7 1466; CHECK-SD-NEXT: mov x8, sp 1467; CHECK-SD-NEXT: fmov s2, w0 1468; CHECK-SD-NEXT: ldr s1, [sp, #24] 1469; CHECK-SD-NEXT: add x9, sp, #32 1470; CHECK-SD-NEXT: fmov s4, w4 1471; CHECK-SD-NEXT: movi v3.4s, #31 1472; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8] 1473; CHECK-SD-NEXT: add x8, sp, #8 1474; CHECK-SD-NEXT: mov v2.s[1], w1 1475; CHECK-SD-NEXT: ld1 { v1.s }[1], [x9] 1476; CHECK-SD-NEXT: add x9, sp, #40 1477; CHECK-SD-NEXT: mov v4.s[1], w5 1478; CHECK-SD-NEXT: ld1 { v0.s }[2], [x8] 1479; CHECK-SD-NEXT: add x8, sp, #16 1480; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9] 1481; CHECK-SD-NEXT: mov v2.s[2], w2 1482; CHECK-SD-NEXT: mov v4.s[2], w6 1483; CHECK-SD-NEXT: ld1 { v0.s }[3], [x8] 1484; CHECK-SD-NEXT: neg v6.4s, v1.4s 1485; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b 1486; CHECK-SD-NEXT: mov v2.s[3], w3 1487; CHECK-SD-NEXT: neg v5.4s, v0.4s 1488; CHECK-SD-NEXT: and v0.16b, v0.16b, v3.16b 1489; CHECK-SD-NEXT: neg v1.4s, v1.4s 1490; CHECK-SD-NEXT: and v5.16b, v5.16b, v3.16b 1491; CHECK-SD-NEXT: neg v0.4s, v0.4s 1492; CHECK-SD-NEXT: and v3.16b, v6.16b, v3.16b 1493; CHECK-SD-NEXT: ushl v1.4s, v4.4s, v1.4s 1494; CHECK-SD-NEXT: ushl v5.4s, v2.4s, v5.4s 1495; CHECK-SD-NEXT: ushl v0.4s, v2.4s, v0.4s 1496; CHECK-SD-NEXT: ushl v2.4s, v4.4s, v3.4s 1497; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b 1498; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b 1499; CHECK-SD-NEXT: mov w1, v0.s[1] 1500; CHECK-SD-NEXT: mov w2, v0.s[2] 1501; CHECK-SD-NEXT: mov w3, v0.s[3] 1502; CHECK-SD-NEXT: mov w5, v1.s[1] 1503; CHECK-SD-NEXT: mov w6, v1.s[2] 1504; CHECK-SD-NEXT: fmov w0, s0 1505; CHECK-SD-NEXT: fmov w4, s1 1506; CHECK-SD-NEXT: ret 1507; 1508; CHECK-GI-LABEL: rotr_v7i32: 1509; CHECK-GI: // %bb.0: // %entry 1510; CHECK-GI-NEXT: mov v0.s[0], w7 1511; CHECK-GI-NEXT: ldr s2, [sp] 1512; CHECK-GI-NEXT: mov v1.s[0], w7 1513; CHECK-GI-NEXT: mov w8, #31 // =0x1f 1514; CHECK-GI-NEXT: ldr s7, [sp, #8] 1515; CHECK-GI-NEXT: mov v3.s[0], wzr 1516; CHECK-GI-NEXT: mov v5.s[0], w8 1517; CHECK-GI-NEXT: mov x11, sp 1518; CHECK-GI-NEXT: ldr s16, [sp, #32] 1519; CHECK-GI-NEXT: mov v4.s[0], w0 1520; CHECK-GI-NEXT: mov v17.s[0], w0 1521; CHECK-GI-NEXT: ldr s6, [sp, #16] 1522; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 1523; CHECK-GI-NEXT: ldr s2, [sp, #24] 1524; CHECK-GI-NEXT: ld1 { v1.s }[1], [x11] 1525; CHECK-GI-NEXT: mov v3.s[1], wzr 1526; CHECK-GI-NEXT: add x10, sp, #8 1527; CHECK-GI-NEXT: ldr s18, [sp, #40] 1528; CHECK-GI-NEXT: mov v19.16b, v2.16b 1529; CHECK-GI-NEXT: mov v2.s[1], v16.s[0] 1530; CHECK-GI-NEXT: mov v5.s[1], w8 1531; CHECK-GI-NEXT: ld1 { v1.s }[2], [x10] 1532; CHECK-GI-NEXT: mov v4.s[1], w1 1533; CHECK-GI-NEXT: mov v17.s[1], w1 1534; CHECK-GI-NEXT: mov v0.s[2], v7.s[0] 1535; CHECK-GI-NEXT: mov v7.s[0], w8 1536; CHECK-GI-NEXT: mov v20.s[0], w4 1537; CHECK-GI-NEXT: mov v19.s[1], v16.s[0] 1538; CHECK-GI-NEXT: add x9, sp, #16 1539; CHECK-GI-NEXT: movi v16.4s, #31 1540; CHECK-GI-NEXT: mov v2.s[2], v18.s[0] 1541; CHECK-GI-NEXT: mov v3.s[2], wzr 1542; CHECK-GI-NEXT: mov v5.s[2], w8 1543; CHECK-GI-NEXT: ld1 { v1.s }[3], [x9] 1544; CHECK-GI-NEXT: mov v4.s[2], w2 1545; CHECK-GI-NEXT: mov v17.s[2], w2 1546; CHECK-GI-NEXT: mov v0.s[3], v6.s[0] 1547; CHECK-GI-NEXT: mov v6.s[0], w4 1548; CHECK-GI-NEXT: mov v7.s[1], w8 1549; CHECK-GI-NEXT: mov v19.s[2], v18.s[0] 1550; CHECK-GI-NEXT: mov v20.s[1], w5 1551; CHECK-GI-NEXT: neg v1.4s, v1.4s 1552; CHECK-GI-NEXT: and v2.16b, v2.16b, v5.16b 1553; CHECK-GI-NEXT: mov v4.s[3], w3 1554; CHECK-GI-NEXT: mov v17.s[3], w3 1555; CHECK-GI-NEXT: mov v6.s[1], w5 1556; CHECK-GI-NEXT: mov v7.s[2], w8 1557; CHECK-GI-NEXT: and v0.16b, v0.16b, v16.16b 1558; CHECK-GI-NEXT: sub v3.4s, v3.4s, v19.4s 1559; CHECK-GI-NEXT: mov v20.s[2], w6 1560; CHECK-GI-NEXT: and v1.16b, v1.16b, v16.16b 1561; CHECK-GI-NEXT: neg v2.4s, v2.4s 1562; CHECK-GI-NEXT: neg v0.4s, v0.4s 1563; CHECK-GI-NEXT: mov v6.s[2], w6 1564; CHECK-GI-NEXT: and v3.16b, v3.16b, v7.16b 1565; CHECK-GI-NEXT: ushl v1.4s, v17.4s, v1.4s 1566; CHECK-GI-NEXT: ushl v2.4s, v20.4s, v2.4s 1567; CHECK-GI-NEXT: ushl v0.4s, v4.4s, v0.4s 1568; CHECK-GI-NEXT: ushl v3.4s, v6.4s, v3.4s 1569; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 1570; CHECK-GI-NEXT: orr v1.16b, v2.16b, v3.16b 1571; CHECK-GI-NEXT: mov s2, v0.s[1] 1572; CHECK-GI-NEXT: mov s3, v0.s[2] 1573; CHECK-GI-NEXT: mov s4, v0.s[3] 1574; CHECK-GI-NEXT: fmov w0, s0 1575; CHECK-GI-NEXT: mov s5, v1.s[1] 1576; CHECK-GI-NEXT: mov s6, v1.s[2] 1577; CHECK-GI-NEXT: fmov w4, s1 1578; CHECK-GI-NEXT: fmov w1, s2 1579; CHECK-GI-NEXT: fmov w2, s3 1580; CHECK-GI-NEXT: fmov w3, s4 1581; CHECK-GI-NEXT: fmov w5, s5 1582; CHECK-GI-NEXT: fmov w6, s6 1583; CHECK-GI-NEXT: ret 1584entry: 1585 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %a, <7 x i32> %c) 1586 ret <7 x i32> %d 1587} 1588 1589define <8 x i32> @rotl_v8i32(<8 x i32> %a, <8 x i32> %c) { 1590; CHECK-LABEL: rotl_v8i32: 1591; CHECK: // %bb.0: // %entry 1592; CHECK-NEXT: movi v4.4s, #31 1593; CHECK-NEXT: neg v5.4s, v2.4s 1594; CHECK-NEXT: neg v6.4s, v3.4s 1595; CHECK-NEXT: and v5.16b, v5.16b, v4.16b 1596; CHECK-NEXT: and v6.16b, v6.16b, v4.16b 1597; CHECK-NEXT: and v2.16b, v2.16b, v4.16b 1598; CHECK-NEXT: and v3.16b, v3.16b, v4.16b 1599; CHECK-NEXT: neg v4.4s, v5.4s 1600; CHECK-NEXT: neg v5.4s, v6.4s 1601; CHECK-NEXT: ushl v2.4s, v0.4s, v2.4s 1602; CHECK-NEXT: ushl v3.4s, v1.4s, v3.4s 1603; CHECK-NEXT: ushl v0.4s, v0.4s, v4.4s 1604; CHECK-NEXT: ushl v1.4s, v1.4s, v5.4s 1605; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b 1606; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b 1607; CHECK-NEXT: ret 1608entry: 1609 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %a, <8 x i32> %c) 1610 ret <8 x i32> %d 1611} 1612 1613define <8 x i32> @rotr_v8i32(<8 x i32> %a, <8 x i32> %c) { 1614; CHECK-SD-LABEL: rotr_v8i32: 1615; CHECK-SD: // %bb.0: // %entry 1616; CHECK-SD-NEXT: movi v4.4s, #31 1617; CHECK-SD-NEXT: neg v5.4s, v2.4s 1618; CHECK-SD-NEXT: neg v6.4s, v3.4s 1619; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b 1620; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b 1621; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b 1622; CHECK-SD-NEXT: and v4.16b, v6.16b, v4.16b 1623; CHECK-SD-NEXT: neg v2.4s, v2.4s 1624; CHECK-SD-NEXT: neg v3.4s, v3.4s 1625; CHECK-SD-NEXT: ushl v5.4s, v0.4s, v5.4s 1626; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v2.4s 1627; CHECK-SD-NEXT: ushl v2.4s, v1.4s, v4.4s 1628; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s 1629; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b 1630; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b 1631; CHECK-SD-NEXT: ret 1632; 1633; CHECK-GI-LABEL: rotr_v8i32: 1634; CHECK-GI: // %bb.0: // %entry 1635; CHECK-GI-NEXT: movi v4.4s, #31 1636; CHECK-GI-NEXT: neg v6.4s, v3.4s 1637; CHECK-GI-NEXT: and v5.16b, v2.16b, v4.16b 1638; CHECK-GI-NEXT: neg v2.4s, v2.4s 1639; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b 1640; CHECK-GI-NEXT: neg v5.4s, v5.4s 1641; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b 1642; CHECK-GI-NEXT: and v4.16b, v6.16b, v4.16b 1643; CHECK-GI-NEXT: neg v3.4s, v3.4s 1644; CHECK-GI-NEXT: ushl v5.4s, v0.4s, v5.4s 1645; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s 1646; CHECK-GI-NEXT: ushl v3.4s, v1.4s, v3.4s 1647; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v4.4s 1648; CHECK-GI-NEXT: orr v0.16b, v5.16b, v0.16b 1649; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 1650; CHECK-GI-NEXT: ret 1651entry: 1652 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %a, <8 x i32> %c) 1653 ret <8 x i32> %d 1654} 1655 1656define <2 x i64> @rotl_v2i64(<2 x i64> %a, <2 x i64> %c) { 1657; CHECK-SD-LABEL: rotl_v2i64: 1658; CHECK-SD: // %bb.0: // %entry 1659; CHECK-SD-NEXT: mov w8, #63 // =0x3f 1660; CHECK-SD-NEXT: neg v3.2d, v1.2d 1661; CHECK-SD-NEXT: dup v2.2d, x8 1662; CHECK-SD-NEXT: and v3.16b, v3.16b, v2.16b 1663; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 1664; CHECK-SD-NEXT: neg v2.2d, v3.2d 1665; CHECK-SD-NEXT: ushl v1.2d, v0.2d, v1.2d 1666; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d 1667; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b 1668; CHECK-SD-NEXT: ret 1669; 1670; CHECK-GI-LABEL: rotl_v2i64: 1671; CHECK-GI: // %bb.0: // %entry 1672; CHECK-GI-NEXT: adrp x8, .LCPI60_0 1673; CHECK-GI-NEXT: neg v2.2d, v1.2d 1674; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI60_0] 1675; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b 1676; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 1677; CHECK-GI-NEXT: neg v2.2d, v2.2d 1678; CHECK-GI-NEXT: ushl v1.2d, v0.2d, v1.2d 1679; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d 1680; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 1681; CHECK-GI-NEXT: ret 1682entry: 1683 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %a, <2 x i64> %c) 1684 ret <2 x i64> %d 1685} 1686 1687define <2 x i64> @rotr_v2i64(<2 x i64> %a, <2 x i64> %c) { 1688; CHECK-SD-LABEL: rotr_v2i64: 1689; CHECK-SD: // %bb.0: // %entry 1690; CHECK-SD-NEXT: mov w8, #63 // =0x3f 1691; CHECK-SD-NEXT: neg v3.2d, v1.2d 1692; CHECK-SD-NEXT: dup v2.2d, x8 1693; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b 1694; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b 1695; CHECK-SD-NEXT: neg v1.2d, v1.2d 1696; CHECK-SD-NEXT: ushl v2.2d, v0.2d, v2.2d 1697; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v1.2d 1698; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1699; CHECK-SD-NEXT: ret 1700; 1701; CHECK-GI-LABEL: rotr_v2i64: 1702; CHECK-GI: // %bb.0: // %entry 1703; CHECK-GI-NEXT: adrp x8, .LCPI61_0 1704; CHECK-GI-NEXT: neg v3.2d, v1.2d 1705; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI61_0] 1706; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b 1707; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b 1708; CHECK-GI-NEXT: neg v1.2d, v1.2d 1709; CHECK-GI-NEXT: ushl v1.2d, v0.2d, v1.2d 1710; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d 1711; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 1712; CHECK-GI-NEXT: ret 1713entry: 1714 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %a, <2 x i64> %c) 1715 ret <2 x i64> %d 1716} 1717 1718define <4 x i64> @rotl_v4i64(<4 x i64> %a, <4 x i64> %c) { 1719; CHECK-SD-LABEL: rotl_v4i64: 1720; CHECK-SD: // %bb.0: // %entry 1721; CHECK-SD-NEXT: mov w8, #63 // =0x3f 1722; CHECK-SD-NEXT: neg v5.2d, v2.2d 1723; CHECK-SD-NEXT: neg v6.2d, v3.2d 1724; CHECK-SD-NEXT: dup v4.2d, x8 1725; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b 1726; CHECK-SD-NEXT: and v6.16b, v6.16b, v4.16b 1727; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b 1728; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b 1729; CHECK-SD-NEXT: neg v4.2d, v5.2d 1730; CHECK-SD-NEXT: neg v5.2d, v6.2d 1731; CHECK-SD-NEXT: ushl v2.2d, v0.2d, v2.2d 1732; CHECK-SD-NEXT: ushl v3.2d, v1.2d, v3.2d 1733; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v4.2d 1734; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v5.2d 1735; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b 1736; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b 1737; CHECK-SD-NEXT: ret 1738; 1739; CHECK-GI-LABEL: rotl_v4i64: 1740; CHECK-GI: // %bb.0: // %entry 1741; CHECK-GI-NEXT: adrp x8, .LCPI62_0 1742; CHECK-GI-NEXT: neg v4.2d, v2.2d 1743; CHECK-GI-NEXT: neg v5.2d, v3.2d 1744; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI62_0] 1745; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b 1746; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b 1747; CHECK-GI-NEXT: and v2.16b, v2.16b, v6.16b 1748; CHECK-GI-NEXT: and v3.16b, v3.16b, v6.16b 1749; CHECK-GI-NEXT: neg v4.2d, v4.2d 1750; CHECK-GI-NEXT: neg v5.2d, v5.2d 1751; CHECK-GI-NEXT: ushl v2.2d, v0.2d, v2.2d 1752; CHECK-GI-NEXT: ushl v3.2d, v1.2d, v3.2d 1753; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v4.2d 1754; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v5.2d 1755; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 1756; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 1757; CHECK-GI-NEXT: ret 1758entry: 1759 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %a, <4 x i64> %c) 1760 ret <4 x i64> %d 1761} 1762 1763define <4 x i64> @rotr_v4i64(<4 x i64> %a, <4 x i64> %c) { 1764; CHECK-SD-LABEL: rotr_v4i64: 1765; CHECK-SD: // %bb.0: // %entry 1766; CHECK-SD-NEXT: mov w8, #63 // =0x3f 1767; CHECK-SD-NEXT: neg v5.2d, v2.2d 1768; CHECK-SD-NEXT: neg v6.2d, v3.2d 1769; CHECK-SD-NEXT: dup v4.2d, x8 1770; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b 1771; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b 1772; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b 1773; CHECK-SD-NEXT: and v4.16b, v6.16b, v4.16b 1774; CHECK-SD-NEXT: neg v2.2d, v2.2d 1775; CHECK-SD-NEXT: neg v3.2d, v3.2d 1776; CHECK-SD-NEXT: ushl v5.2d, v0.2d, v5.2d 1777; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d 1778; CHECK-SD-NEXT: ushl v2.2d, v1.2d, v4.2d 1779; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d 1780; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b 1781; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b 1782; CHECK-SD-NEXT: ret 1783; 1784; CHECK-GI-LABEL: rotr_v4i64: 1785; CHECK-GI: // %bb.0: // %entry 1786; CHECK-GI-NEXT: adrp x8, .LCPI63_0 1787; CHECK-GI-NEXT: neg v6.2d, v3.2d 1788; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI63_0] 1789; CHECK-GI-NEXT: and v5.16b, v2.16b, v4.16b 1790; CHECK-GI-NEXT: neg v2.2d, v2.2d 1791; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b 1792; CHECK-GI-NEXT: neg v5.2d, v5.2d 1793; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b 1794; CHECK-GI-NEXT: and v4.16b, v6.16b, v4.16b 1795; CHECK-GI-NEXT: neg v3.2d, v3.2d 1796; CHECK-GI-NEXT: ushl v5.2d, v0.2d, v5.2d 1797; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d 1798; CHECK-GI-NEXT: ushl v3.2d, v1.2d, v3.2d 1799; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v4.2d 1800; CHECK-GI-NEXT: orr v0.16b, v5.16b, v0.16b 1801; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 1802; CHECK-GI-NEXT: ret 1803entry: 1804 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %a, <4 x i64> %c) 1805 ret <4 x i64> %d 1806} 1807 1808define <2 x i128> @rotl_v2i128(<2 x i128> %a, <2 x i128> %c) { 1809; CHECK-SD-LABEL: rotl_v2i128: 1810; CHECK-SD: // %bb.0: // %entry 1811; CHECK-SD-NEXT: tst x4, #0x40 1812; CHECK-SD-NEXT: mvn w9, w4 1813; CHECK-SD-NEXT: csel x8, x1, x0, ne 1814; CHECK-SD-NEXT: csel x10, x0, x1, ne 1815; CHECK-SD-NEXT: tst x6, #0x40 1816; CHECK-SD-NEXT: lsl x11, x8, x4 1817; CHECK-SD-NEXT: lsr x12, x10, #1 1818; CHECK-SD-NEXT: lsr x8, x8, #1 1819; CHECK-SD-NEXT: csel x13, x3, x2, ne 1820; CHECK-SD-NEXT: csel x14, x2, x3, ne 1821; CHECK-SD-NEXT: lsl x10, x10, x4 1822; CHECK-SD-NEXT: lsr x15, x14, #1 1823; CHECK-SD-NEXT: lsr x16, x13, #1 1824; CHECK-SD-NEXT: lsr x12, x12, x9 1825; CHECK-SD-NEXT: lsr x8, x8, x9 1826; CHECK-SD-NEXT: lsl x9, x13, x6 1827; CHECK-SD-NEXT: mvn w13, w6 1828; CHECK-SD-NEXT: lsr x15, x15, x13 1829; CHECK-SD-NEXT: lsl x14, x14, x6 1830; CHECK-SD-NEXT: lsr x13, x16, x13 1831; CHECK-SD-NEXT: orr x0, x11, x12 1832; CHECK-SD-NEXT: orr x1, x10, x8 1833; CHECK-SD-NEXT: orr x2, x9, x15 1834; CHECK-SD-NEXT: orr x3, x14, x13 1835; CHECK-SD-NEXT: ret 1836; 1837; CHECK-GI-LABEL: rotl_v2i128: 1838; CHECK-GI: // %bb.0: // %entry 1839; CHECK-GI-NEXT: and x8, x4, #0x7f 1840; CHECK-GI-NEXT: mov w9, #64 // =0x40 1841; CHECK-GI-NEXT: neg x13, x4 1842; CHECK-GI-NEXT: sub x10, x9, x8 1843; CHECK-GI-NEXT: lsl x12, x1, x8 1844; CHECK-GI-NEXT: sub x11, x8, #64 1845; CHECK-GI-NEXT: lsr x10, x0, x10 1846; CHECK-GI-NEXT: lsl x14, x0, x8 1847; CHECK-GI-NEXT: lsl x11, x0, x11 1848; CHECK-GI-NEXT: cmp x8, #64 1849; CHECK-GI-NEXT: neg x15, x6 1850; CHECK-GI-NEXT: orr x8, x10, x12 1851; CHECK-GI-NEXT: and x10, x6, #0x7f 1852; CHECK-GI-NEXT: csel x12, x14, xzr, lo 1853; CHECK-GI-NEXT: sub x14, x9, x10 1854; CHECK-GI-NEXT: csel x8, x8, x11, lo 1855; CHECK-GI-NEXT: tst x4, #0x7f 1856; CHECK-GI-NEXT: sub x11, x10, #64 1857; CHECK-GI-NEXT: lsl x16, x2, x10 1858; CHECK-GI-NEXT: lsr x14, x2, x14 1859; CHECK-GI-NEXT: lsl x17, x3, x10 1860; CHECK-GI-NEXT: csel x8, x1, x8, eq 1861; CHECK-GI-NEXT: lsl x11, x2, x11 1862; CHECK-GI-NEXT: cmp x10, #64 1863; CHECK-GI-NEXT: and x4, x15, #0x7f 1864; CHECK-GI-NEXT: orr x10, x14, x17 1865; CHECK-GI-NEXT: csel x14, x16, xzr, lo 1866; CHECK-GI-NEXT: and x16, x13, #0x7f 1867; CHECK-GI-NEXT: csel x10, x10, x11, lo 1868; CHECK-GI-NEXT: sub x11, x9, x16 1869; CHECK-GI-NEXT: sub x17, x16, #64 1870; CHECK-GI-NEXT: lsr x18, x0, x16 1871; CHECK-GI-NEXT: lsl x11, x1, x11 1872; CHECK-GI-NEXT: tst x6, #0x7f 1873; CHECK-GI-NEXT: lsr x17, x1, x17 1874; CHECK-GI-NEXT: csel x10, x3, x10, eq 1875; CHECK-GI-NEXT: cmp x16, #64 1876; CHECK-GI-NEXT: orr x11, x18, x11 1877; CHECK-GI-NEXT: sub x9, x9, x4 1878; CHECK-GI-NEXT: lsr x1, x1, x16 1879; CHECK-GI-NEXT: csel x11, x11, x17, lo 1880; CHECK-GI-NEXT: tst x13, #0x7f 1881; CHECK-GI-NEXT: sub x13, x4, #64 1882; CHECK-GI-NEXT: lsr x17, x2, x4 1883; CHECK-GI-NEXT: lsl x9, x3, x9 1884; CHECK-GI-NEXT: csel x11, x0, x11, eq 1885; CHECK-GI-NEXT: cmp x16, #64 1886; CHECK-GI-NEXT: lsr x13, x3, x13 1887; CHECK-GI-NEXT: orr x0, x12, x11 1888; CHECK-GI-NEXT: csel x16, x1, xzr, lo 1889; CHECK-GI-NEXT: orr x9, x17, x9 1890; CHECK-GI-NEXT: cmp x4, #64 1891; CHECK-GI-NEXT: lsr x17, x3, x4 1892; CHECK-GI-NEXT: csel x9, x9, x13, lo 1893; CHECK-GI-NEXT: tst x15, #0x7f 1894; CHECK-GI-NEXT: csel x9, x2, x9, eq 1895; CHECK-GI-NEXT: cmp x4, #64 1896; CHECK-GI-NEXT: orr x1, x8, x16 1897; CHECK-GI-NEXT: csel x13, x17, xzr, lo 1898; CHECK-GI-NEXT: orr x2, x14, x9 1899; CHECK-GI-NEXT: orr x3, x10, x13 1900; CHECK-GI-NEXT: ret 1901entry: 1902 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c) 1903 ret <2 x i128> %d 1904} 1905 1906define <2 x i128> @rotr_v2i128(<2 x i128> %a, <2 x i128> %c) { 1907; CHECK-SD-LABEL: rotr_v2i128: 1908; CHECK-SD: // %bb.0: // %entry 1909; CHECK-SD-NEXT: tst x4, #0x40 1910; CHECK-SD-NEXT: mvn w9, w4 1911; CHECK-SD-NEXT: csel x8, x0, x1, eq 1912; CHECK-SD-NEXT: csel x10, x1, x0, eq 1913; CHECK-SD-NEXT: tst x6, #0x40 1914; CHECK-SD-NEXT: lsr x11, x8, x4 1915; CHECK-SD-NEXT: lsl x12, x10, #1 1916; CHECK-SD-NEXT: lsl x8, x8, #1 1917; CHECK-SD-NEXT: csel x13, x2, x3, eq 1918; CHECK-SD-NEXT: csel x14, x3, x2, eq 1919; CHECK-SD-NEXT: lsr x10, x10, x4 1920; CHECK-SD-NEXT: lsl x15, x14, #1 1921; CHECK-SD-NEXT: lsl x16, x13, #1 1922; CHECK-SD-NEXT: lsl x12, x12, x9 1923; CHECK-SD-NEXT: lsl x8, x8, x9 1924; CHECK-SD-NEXT: lsr x9, x13, x6 1925; CHECK-SD-NEXT: mvn w13, w6 1926; CHECK-SD-NEXT: lsl x15, x15, x13 1927; CHECK-SD-NEXT: lsr x14, x14, x6 1928; CHECK-SD-NEXT: lsl x13, x16, x13 1929; CHECK-SD-NEXT: orr x0, x12, x11 1930; CHECK-SD-NEXT: orr x1, x8, x10 1931; CHECK-SD-NEXT: orr x2, x15, x9 1932; CHECK-SD-NEXT: orr x3, x13, x14 1933; CHECK-SD-NEXT: ret 1934; 1935; CHECK-GI-LABEL: rotr_v2i128: 1936; CHECK-GI: // %bb.0: // %entry 1937; CHECK-GI-NEXT: and x8, x4, #0x7f 1938; CHECK-GI-NEXT: mov w9, #64 // =0x40 1939; CHECK-GI-NEXT: and x14, x6, #0x7f 1940; CHECK-GI-NEXT: sub x10, x9, x8 1941; CHECK-GI-NEXT: sub x11, x8, #64 1942; CHECK-GI-NEXT: lsr x12, x0, x8 1943; CHECK-GI-NEXT: lsl x10, x1, x10 1944; CHECK-GI-NEXT: lsr x11, x1, x11 1945; CHECK-GI-NEXT: cmp x8, #64 1946; CHECK-GI-NEXT: sub x15, x9, x14 1947; CHECK-GI-NEXT: neg x13, x4 1948; CHECK-GI-NEXT: lsr x17, x3, x14 1949; CHECK-GI-NEXT: orr x10, x12, x10 1950; CHECK-GI-NEXT: lsr x12, x1, x8 1951; CHECK-GI-NEXT: lsl x15, x3, x15 1952; CHECK-GI-NEXT: csel x10, x10, x11, lo 1953; CHECK-GI-NEXT: tst x4, #0x7f 1954; CHECK-GI-NEXT: sub x11, x14, #64 1955; CHECK-GI-NEXT: csel x10, x0, x10, eq 1956; CHECK-GI-NEXT: cmp x8, #64 1957; CHECK-GI-NEXT: lsr x8, x2, x14 1958; CHECK-GI-NEXT: lsr x11, x3, x11 1959; CHECK-GI-NEXT: csel x12, x12, xzr, lo 1960; CHECK-GI-NEXT: cmp x14, #64 1961; CHECK-GI-NEXT: orr x8, x8, x15 1962; CHECK-GI-NEXT: neg x16, x6 1963; CHECK-GI-NEXT: csel x8, x8, x11, lo 1964; CHECK-GI-NEXT: tst x6, #0x7f 1965; CHECK-GI-NEXT: and x11, x13, #0x7f 1966; CHECK-GI-NEXT: csel x8, x2, x8, eq 1967; CHECK-GI-NEXT: cmp x14, #64 1968; CHECK-GI-NEXT: sub x14, x9, x11 1969; CHECK-GI-NEXT: sub x15, x11, #64 1970; CHECK-GI-NEXT: lsr x14, x0, x14 1971; CHECK-GI-NEXT: lsl x18, x1, x11 1972; CHECK-GI-NEXT: lsl x4, x0, x11 1973; CHECK-GI-NEXT: lsl x15, x0, x15 1974; CHECK-GI-NEXT: and x0, x16, #0x7f 1975; CHECK-GI-NEXT: csel x17, x17, xzr, lo 1976; CHECK-GI-NEXT: orr x14, x14, x18 1977; CHECK-GI-NEXT: cmp x11, #64 1978; CHECK-GI-NEXT: sub x9, x9, x0 1979; CHECK-GI-NEXT: csel x14, x14, x15, lo 1980; CHECK-GI-NEXT: sub x15, x0, #64 1981; CHECK-GI-NEXT: lsr x9, x2, x9 1982; CHECK-GI-NEXT: lsl x18, x3, x0 1983; CHECK-GI-NEXT: csel x11, x4, xzr, lo 1984; CHECK-GI-NEXT: tst x13, #0x7f 1985; CHECK-GI-NEXT: lsl x13, x2, x0 1986; CHECK-GI-NEXT: lsl x15, x2, x15 1987; CHECK-GI-NEXT: csel x14, x1, x14, eq 1988; CHECK-GI-NEXT: orr x9, x9, x18 1989; CHECK-GI-NEXT: cmp x0, #64 1990; CHECK-GI-NEXT: csel x13, x13, xzr, lo 1991; CHECK-GI-NEXT: csel x9, x9, x15, lo 1992; CHECK-GI-NEXT: tst x16, #0x7f 1993; CHECK-GI-NEXT: csel x9, x3, x9, eq 1994; CHECK-GI-NEXT: orr x0, x10, x11 1995; CHECK-GI-NEXT: orr x1, x12, x14 1996; CHECK-GI-NEXT: orr x2, x8, x13 1997; CHECK-GI-NEXT: orr x3, x17, x9 1998; CHECK-GI-NEXT: ret 1999entry: 2000 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c) 2001 ret <2 x i128> %d 2002} 2003 2004define <8 x i8> @fshl_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 2005; CHECK-LABEL: fshl_v8i8: 2006; CHECK: // %bb.0: // %entry 2007; CHECK-NEXT: movi v3.8b, #7 2008; CHECK-NEXT: ushr v1.8b, v1.8b, #1 2009; CHECK-NEXT: bic v4.8b, v3.8b, v2.8b 2010; CHECK-NEXT: and v2.8b, v2.8b, v3.8b 2011; CHECK-NEXT: neg v3.8b, v4.8b 2012; CHECK-NEXT: ushl v0.8b, v0.8b, v2.8b 2013; CHECK-NEXT: ushl v1.8b, v1.8b, v3.8b 2014; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 2015; CHECK-NEXT: ret 2016entry: 2017 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) 2018 ret <8 x i8> %d 2019} 2020 2021define <8 x i8> @fshr_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 2022; CHECK-SD-LABEL: fshr_v8i8: 2023; CHECK-SD: // %bb.0: // %entry 2024; CHECK-SD-NEXT: movi v3.8b, #7 2025; CHECK-SD-NEXT: add v0.8b, v0.8b, v0.8b 2026; CHECK-SD-NEXT: and v4.8b, v2.8b, v3.8b 2027; CHECK-SD-NEXT: bic v2.8b, v3.8b, v2.8b 2028; CHECK-SD-NEXT: neg v3.8b, v4.8b 2029; CHECK-SD-NEXT: ushl v0.8b, v0.8b, v2.8b 2030; CHECK-SD-NEXT: ushl v1.8b, v1.8b, v3.8b 2031; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 2032; CHECK-SD-NEXT: ret 2033; 2034; CHECK-GI-LABEL: fshr_v8i8: 2035; CHECK-GI: // %bb.0: // %entry 2036; CHECK-GI-NEXT: movi v3.8b, #7 2037; CHECK-GI-NEXT: shl v0.8b, v0.8b, #1 2038; CHECK-GI-NEXT: and v4.8b, v2.8b, v3.8b 2039; CHECK-GI-NEXT: bic v2.8b, v3.8b, v2.8b 2040; CHECK-GI-NEXT: neg v3.8b, v4.8b 2041; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v2.8b 2042; CHECK-GI-NEXT: ushl v1.8b, v1.8b, v3.8b 2043; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 2044; CHECK-GI-NEXT: ret 2045entry: 2046 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) 2047 ret <8 x i8> %d 2048} 2049 2050define <16 x i8> @fshl_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2051; CHECK-LABEL: fshl_v16i8: 2052; CHECK: // %bb.0: // %entry 2053; CHECK-NEXT: movi v3.16b, #7 2054; CHECK-NEXT: ushr v1.16b, v1.16b, #1 2055; CHECK-NEXT: bic v4.16b, v3.16b, v2.16b 2056; CHECK-NEXT: and v2.16b, v2.16b, v3.16b 2057; CHECK-NEXT: neg v3.16b, v4.16b 2058; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b 2059; CHECK-NEXT: ushl v1.16b, v1.16b, v3.16b 2060; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2061; CHECK-NEXT: ret 2062entry: 2063 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) 2064 ret <16 x i8> %d 2065} 2066 2067define <16 x i8> @fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2068; CHECK-SD-LABEL: fshr_v16i8: 2069; CHECK-SD: // %bb.0: // %entry 2070; CHECK-SD-NEXT: movi v3.16b, #7 2071; CHECK-SD-NEXT: add v0.16b, v0.16b, v0.16b 2072; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b 2073; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b 2074; CHECK-SD-NEXT: neg v3.16b, v4.16b 2075; CHECK-SD-NEXT: ushl v0.16b, v0.16b, v2.16b 2076; CHECK-SD-NEXT: ushl v1.16b, v1.16b, v3.16b 2077; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2078; CHECK-SD-NEXT: ret 2079; 2080; CHECK-GI-LABEL: fshr_v16i8: 2081; CHECK-GI: // %bb.0: // %entry 2082; CHECK-GI-NEXT: movi v3.16b, #7 2083; CHECK-GI-NEXT: shl v0.16b, v0.16b, #1 2084; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b 2085; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b 2086; CHECK-GI-NEXT: neg v3.16b, v4.16b 2087; CHECK-GI-NEXT: ushl v0.16b, v0.16b, v2.16b 2088; CHECK-GI-NEXT: ushl v1.16b, v1.16b, v3.16b 2089; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2090; CHECK-GI-NEXT: ret 2091entry: 2092 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) 2093 ret <16 x i8> %d 2094} 2095 2096define <4 x i16> @fshl_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) { 2097; CHECK-LABEL: fshl_v4i16: 2098; CHECK: // %bb.0: // %entry 2099; CHECK-NEXT: movi v3.4h, #15 2100; CHECK-NEXT: ushr v1.4h, v1.4h, #1 2101; CHECK-NEXT: bic v4.8b, v3.8b, v2.8b 2102; CHECK-NEXT: and v2.8b, v2.8b, v3.8b 2103; CHECK-NEXT: neg v3.4h, v4.4h 2104; CHECK-NEXT: ushl v0.4h, v0.4h, v2.4h 2105; CHECK-NEXT: ushl v1.4h, v1.4h, v3.4h 2106; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 2107; CHECK-NEXT: ret 2108entry: 2109 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) 2110 ret <4 x i16> %d 2111} 2112 2113define <4 x i16> @fshr_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) { 2114; CHECK-SD-LABEL: fshr_v4i16: 2115; CHECK-SD: // %bb.0: // %entry 2116; CHECK-SD-NEXT: movi v3.4h, #15 2117; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h 2118; CHECK-SD-NEXT: and v4.8b, v2.8b, v3.8b 2119; CHECK-SD-NEXT: bic v2.8b, v3.8b, v2.8b 2120; CHECK-SD-NEXT: neg v3.4h, v4.4h 2121; CHECK-SD-NEXT: ushl v0.4h, v0.4h, v2.4h 2122; CHECK-SD-NEXT: ushl v1.4h, v1.4h, v3.4h 2123; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 2124; CHECK-SD-NEXT: ret 2125; 2126; CHECK-GI-LABEL: fshr_v4i16: 2127; CHECK-GI: // %bb.0: // %entry 2128; CHECK-GI-NEXT: movi v3.4h, #15 2129; CHECK-GI-NEXT: shl v0.4h, v0.4h, #1 2130; CHECK-GI-NEXT: and v4.8b, v2.8b, v3.8b 2131; CHECK-GI-NEXT: bic v2.8b, v3.8b, v2.8b 2132; CHECK-GI-NEXT: neg v3.4h, v4.4h 2133; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v2.4h 2134; CHECK-GI-NEXT: ushl v1.4h, v1.4h, v3.4h 2135; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 2136; CHECK-GI-NEXT: ret 2137entry: 2138 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) 2139 ret <4 x i16> %d 2140} 2141 2142define <7 x i16> @fshl_v7i16(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c) { 2143; CHECK-SD-LABEL: fshl_v7i16: 2144; CHECK-SD: // %bb.0: // %entry 2145; CHECK-SD-NEXT: movi v3.8h, #15 2146; CHECK-SD-NEXT: ushr v1.8h, v1.8h, #1 2147; CHECK-SD-NEXT: bic v4.16b, v3.16b, v2.16b 2148; CHECK-SD-NEXT: and v2.16b, v2.16b, v3.16b 2149; CHECK-SD-NEXT: neg v3.8h, v4.8h 2150; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 2151; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h 2152; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2153; CHECK-SD-NEXT: ret 2154; 2155; CHECK-GI-LABEL: fshl_v7i16: 2156; CHECK-GI: // %bb.0: // %entry 2157; CHECK-GI-NEXT: mov w8, #65535 // =0xffff 2158; CHECK-GI-NEXT: mov w9, #15 // =0xf 2159; CHECK-GI-NEXT: mov w10, #1 // =0x1 2160; CHECK-GI-NEXT: fmov s3, w8 2161; CHECK-GI-NEXT: fmov s4, w9 2162; CHECK-GI-NEXT: fmov s5, w10 2163; CHECK-GI-NEXT: mov v3.h[1], w8 2164; CHECK-GI-NEXT: mov v4.h[1], w9 2165; CHECK-GI-NEXT: mov v5.h[1], w10 2166; CHECK-GI-NEXT: mov v3.h[2], w8 2167; CHECK-GI-NEXT: mov v4.h[2], w9 2168; CHECK-GI-NEXT: mov v5.h[2], w10 2169; CHECK-GI-NEXT: mov v3.h[3], w8 2170; CHECK-GI-NEXT: mov v4.h[3], w9 2171; CHECK-GI-NEXT: mov v5.h[3], w10 2172; CHECK-GI-NEXT: mov v3.h[4], w8 2173; CHECK-GI-NEXT: mov v4.h[4], w9 2174; CHECK-GI-NEXT: mov v5.h[4], w10 2175; CHECK-GI-NEXT: mov v3.h[5], w8 2176; CHECK-GI-NEXT: mov v4.h[5], w9 2177; CHECK-GI-NEXT: mov v5.h[5], w10 2178; CHECK-GI-NEXT: mov v3.h[6], w8 2179; CHECK-GI-NEXT: mov v4.h[6], w9 2180; CHECK-GI-NEXT: mov v5.h[6], w10 2181; CHECK-GI-NEXT: eor v3.16b, v2.16b, v3.16b 2182; CHECK-GI-NEXT: neg v5.8h, v5.8h 2183; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b 2184; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b 2185; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v5.8h 2186; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 2187; CHECK-GI-NEXT: neg v3.8h, v3.8h 2188; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v3.8h 2189; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2190; CHECK-GI-NEXT: ret 2191entry: 2192 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c) 2193 ret <7 x i16> %d 2194} 2195 2196define <7 x i16> @fshr_v7i16(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c) { 2197; CHECK-SD-LABEL: fshr_v7i16: 2198; CHECK-SD: // %bb.0: // %entry 2199; CHECK-SD-NEXT: movi v3.8h, #15 2200; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h 2201; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b 2202; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b 2203; CHECK-SD-NEXT: neg v3.8h, v4.8h 2204; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 2205; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h 2206; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2207; CHECK-SD-NEXT: ret 2208; 2209; CHECK-GI-LABEL: fshr_v7i16: 2210; CHECK-GI: // %bb.0: // %entry 2211; CHECK-GI-NEXT: mov w8, #15 // =0xf 2212; CHECK-GI-NEXT: mov w9, #65535 // =0xffff 2213; CHECK-GI-NEXT: mov w10, #1 // =0x1 2214; CHECK-GI-NEXT: fmov s3, w8 2215; CHECK-GI-NEXT: fmov s4, w9 2216; CHECK-GI-NEXT: fmov s5, w10 2217; CHECK-GI-NEXT: mov v3.h[1], w8 2218; CHECK-GI-NEXT: mov v4.h[1], w9 2219; CHECK-GI-NEXT: mov v5.h[1], w10 2220; CHECK-GI-NEXT: mov v3.h[2], w8 2221; CHECK-GI-NEXT: mov v4.h[2], w9 2222; CHECK-GI-NEXT: mov v5.h[2], w10 2223; CHECK-GI-NEXT: mov v3.h[3], w8 2224; CHECK-GI-NEXT: mov v4.h[3], w9 2225; CHECK-GI-NEXT: mov v5.h[3], w10 2226; CHECK-GI-NEXT: mov v3.h[4], w8 2227; CHECK-GI-NEXT: mov v4.h[4], w9 2228; CHECK-GI-NEXT: mov v5.h[4], w10 2229; CHECK-GI-NEXT: mov v3.h[5], w8 2230; CHECK-GI-NEXT: mov v4.h[5], w9 2231; CHECK-GI-NEXT: mov v5.h[5], w10 2232; CHECK-GI-NEXT: mov v3.h[6], w8 2233; CHECK-GI-NEXT: mov v4.h[6], w9 2234; CHECK-GI-NEXT: mov v5.h[6], w10 2235; CHECK-GI-NEXT: eor v4.16b, v2.16b, v4.16b 2236; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b 2237; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v5.8h 2238; CHECK-GI-NEXT: and v3.16b, v4.16b, v3.16b 2239; CHECK-GI-NEXT: neg v2.8h, v2.8h 2240; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v3.8h 2241; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v2.8h 2242; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2243; CHECK-GI-NEXT: ret 2244entry: 2245 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c) 2246 ret <7 x i16> %d 2247} 2248 2249define <8 x i16> @fshl_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 2250; CHECK-LABEL: fshl_v8i16: 2251; CHECK: // %bb.0: // %entry 2252; CHECK-NEXT: movi v3.8h, #15 2253; CHECK-NEXT: ushr v1.8h, v1.8h, #1 2254; CHECK-NEXT: bic v4.16b, v3.16b, v2.16b 2255; CHECK-NEXT: and v2.16b, v2.16b, v3.16b 2256; CHECK-NEXT: neg v3.8h, v4.8h 2257; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h 2258; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h 2259; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2260; CHECK-NEXT: ret 2261entry: 2262 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) 2263 ret <8 x i16> %d 2264} 2265 2266define <8 x i16> @fshr_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 2267; CHECK-SD-LABEL: fshr_v8i16: 2268; CHECK-SD: // %bb.0: // %entry 2269; CHECK-SD-NEXT: movi v3.8h, #15 2270; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h 2271; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b 2272; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b 2273; CHECK-SD-NEXT: neg v3.8h, v4.8h 2274; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 2275; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h 2276; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2277; CHECK-SD-NEXT: ret 2278; 2279; CHECK-GI-LABEL: fshr_v8i16: 2280; CHECK-GI: // %bb.0: // %entry 2281; CHECK-GI-NEXT: movi v3.8h, #15 2282; CHECK-GI-NEXT: shl v0.8h, v0.8h, #1 2283; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b 2284; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b 2285; CHECK-GI-NEXT: neg v3.8h, v4.8h 2286; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 2287; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v3.8h 2288; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2289; CHECK-GI-NEXT: ret 2290entry: 2291 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) 2292 ret <8 x i16> %d 2293} 2294 2295define <16 x i16> @fshl_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c) { 2296; CHECK-LABEL: fshl_v16i16: 2297; CHECK: // %bb.0: // %entry 2298; CHECK-NEXT: movi v6.8h, #15 2299; CHECK-NEXT: ushr v2.8h, v2.8h, #1 2300; CHECK-NEXT: ushr v3.8h, v3.8h, #1 2301; CHECK-NEXT: bic v7.16b, v6.16b, v4.16b 2302; CHECK-NEXT: bic v16.16b, v6.16b, v5.16b 2303; CHECK-NEXT: and v4.16b, v4.16b, v6.16b 2304; CHECK-NEXT: and v5.16b, v5.16b, v6.16b 2305; CHECK-NEXT: neg v6.8h, v7.8h 2306; CHECK-NEXT: neg v7.8h, v16.8h 2307; CHECK-NEXT: ushl v0.8h, v0.8h, v4.8h 2308; CHECK-NEXT: ushl v1.8h, v1.8h, v5.8h 2309; CHECK-NEXT: ushl v2.8h, v2.8h, v6.8h 2310; CHECK-NEXT: ushl v3.8h, v3.8h, v7.8h 2311; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2312; CHECK-NEXT: orr v1.16b, v1.16b, v3.16b 2313; CHECK-NEXT: ret 2314entry: 2315 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c) 2316 ret <16 x i16> %d 2317} 2318 2319define <16 x i16> @fshr_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c) { 2320; CHECK-SD-LABEL: fshr_v16i16: 2321; CHECK-SD: // %bb.0: // %entry 2322; CHECK-SD-NEXT: movi v6.8h, #15 2323; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h 2324; CHECK-SD-NEXT: add v1.8h, v1.8h, v1.8h 2325; CHECK-SD-NEXT: and v7.16b, v4.16b, v6.16b 2326; CHECK-SD-NEXT: and v16.16b, v5.16b, v6.16b 2327; CHECK-SD-NEXT: bic v4.16b, v6.16b, v4.16b 2328; CHECK-SD-NEXT: bic v5.16b, v6.16b, v5.16b 2329; CHECK-SD-NEXT: neg v6.8h, v7.8h 2330; CHECK-SD-NEXT: neg v7.8h, v16.8h 2331; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v4.8h 2332; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v5.8h 2333; CHECK-SD-NEXT: ushl v2.8h, v2.8h, v6.8h 2334; CHECK-SD-NEXT: ushl v3.8h, v3.8h, v7.8h 2335; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 2336; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 2337; CHECK-SD-NEXT: ret 2338; 2339; CHECK-GI-LABEL: fshr_v16i16: 2340; CHECK-GI: // %bb.0: // %entry 2341; CHECK-GI-NEXT: movi v6.8h, #15 2342; CHECK-GI-NEXT: shl v0.8h, v0.8h, #1 2343; CHECK-GI-NEXT: shl v1.8h, v1.8h, #1 2344; CHECK-GI-NEXT: and v7.16b, v4.16b, v6.16b 2345; CHECK-GI-NEXT: and v16.16b, v5.16b, v6.16b 2346; CHECK-GI-NEXT: bic v4.16b, v6.16b, v4.16b 2347; CHECK-GI-NEXT: bic v5.16b, v6.16b, v5.16b 2348; CHECK-GI-NEXT: neg v6.8h, v7.8h 2349; CHECK-GI-NEXT: neg v7.8h, v16.8h 2350; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v4.8h 2351; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v5.8h 2352; CHECK-GI-NEXT: ushl v2.8h, v2.8h, v6.8h 2353; CHECK-GI-NEXT: ushl v3.8h, v3.8h, v7.8h 2354; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 2355; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 2356; CHECK-GI-NEXT: ret 2357entry: 2358 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c) 2359 ret <16 x i16> %d 2360} 2361 2362define <2 x i32> @fshl_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) { 2363; CHECK-LABEL: fshl_v2i32: 2364; CHECK: // %bb.0: // %entry 2365; CHECK-NEXT: movi v3.2s, #31 2366; CHECK-NEXT: ushr v1.2s, v1.2s, #1 2367; CHECK-NEXT: bic v4.8b, v3.8b, v2.8b 2368; CHECK-NEXT: and v2.8b, v2.8b, v3.8b 2369; CHECK-NEXT: neg v3.2s, v4.2s 2370; CHECK-NEXT: ushl v0.2s, v0.2s, v2.2s 2371; CHECK-NEXT: ushl v1.2s, v1.2s, v3.2s 2372; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 2373; CHECK-NEXT: ret 2374entry: 2375 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) 2376 ret <2 x i32> %d 2377} 2378 2379define <2 x i32> @fshr_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) { 2380; CHECK-SD-LABEL: fshr_v2i32: 2381; CHECK-SD: // %bb.0: // %entry 2382; CHECK-SD-NEXT: movi v3.2s, #31 2383; CHECK-SD-NEXT: add v0.2s, v0.2s, v0.2s 2384; CHECK-SD-NEXT: and v4.8b, v2.8b, v3.8b 2385; CHECK-SD-NEXT: bic v2.8b, v3.8b, v2.8b 2386; CHECK-SD-NEXT: neg v3.2s, v4.2s 2387; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v2.2s 2388; CHECK-SD-NEXT: ushl v1.2s, v1.2s, v3.2s 2389; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 2390; CHECK-SD-NEXT: ret 2391; 2392; CHECK-GI-LABEL: fshr_v2i32: 2393; CHECK-GI: // %bb.0: // %entry 2394; CHECK-GI-NEXT: movi v3.2s, #31 2395; CHECK-GI-NEXT: shl v0.2s, v0.2s, #1 2396; CHECK-GI-NEXT: and v4.8b, v2.8b, v3.8b 2397; CHECK-GI-NEXT: bic v2.8b, v3.8b, v2.8b 2398; CHECK-GI-NEXT: neg v3.2s, v4.2s 2399; CHECK-GI-NEXT: ushl v0.2s, v0.2s, v2.2s 2400; CHECK-GI-NEXT: ushl v1.2s, v1.2s, v3.2s 2401; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 2402; CHECK-GI-NEXT: ret 2403entry: 2404 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) 2405 ret <2 x i32> %d 2406} 2407 2408define <4 x i32> @fshl_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 2409; CHECK-LABEL: fshl_v4i32: 2410; CHECK: // %bb.0: // %entry 2411; CHECK-NEXT: movi v3.4s, #31 2412; CHECK-NEXT: ushr v1.4s, v1.4s, #1 2413; CHECK-NEXT: bic v4.16b, v3.16b, v2.16b 2414; CHECK-NEXT: and v2.16b, v2.16b, v3.16b 2415; CHECK-NEXT: neg v3.4s, v4.4s 2416; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s 2417; CHECK-NEXT: ushl v1.4s, v1.4s, v3.4s 2418; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2419; CHECK-NEXT: ret 2420entry: 2421 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) 2422 ret <4 x i32> %d 2423} 2424 2425define <4 x i32> @fshr_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 2426; CHECK-SD-LABEL: fshr_v4i32: 2427; CHECK-SD: // %bb.0: // %entry 2428; CHECK-SD-NEXT: movi v3.4s, #31 2429; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s 2430; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b 2431; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b 2432; CHECK-SD-NEXT: neg v3.4s, v4.4s 2433; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v2.4s 2434; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s 2435; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2436; CHECK-SD-NEXT: ret 2437; 2438; CHECK-GI-LABEL: fshr_v4i32: 2439; CHECK-GI: // %bb.0: // %entry 2440; CHECK-GI-NEXT: movi v3.4s, #31 2441; CHECK-GI-NEXT: shl v0.4s, v0.4s, #1 2442; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b 2443; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b 2444; CHECK-GI-NEXT: neg v3.4s, v4.4s 2445; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s 2446; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v3.4s 2447; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2448; CHECK-GI-NEXT: ret 2449entry: 2450 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) 2451 ret <4 x i32> %d 2452} 2453 2454define <7 x i32> @fshl_v7i32(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c) { 2455; CHECK-SD-LABEL: fshl_v7i32: 2456; CHECK-SD: // %bb.0: // %entry 2457; CHECK-SD-NEXT: ldr s0, [sp, #48] 2458; CHECK-SD-NEXT: add x8, sp, #56 2459; CHECK-SD-NEXT: fmov s3, w7 2460; CHECK-SD-NEXT: fmov s4, w0 2461; CHECK-SD-NEXT: ldr s2, [sp, #80] 2462; CHECK-SD-NEXT: mov x9, sp 2463; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8] 2464; CHECK-SD-NEXT: add x10, sp, #88 2465; CHECK-SD-NEXT: ldr s1, [sp, #24] 2466; CHECK-SD-NEXT: ld1 { v3.s }[1], [x9] 2467; CHECK-SD-NEXT: add x9, sp, #64 2468; CHECK-SD-NEXT: ld1 { v2.s }[1], [x10] 2469; CHECK-SD-NEXT: mov v4.s[1], w1 2470; CHECK-SD-NEXT: add x8, sp, #32 2471; CHECK-SD-NEXT: fmov s5, w4 2472; CHECK-SD-NEXT: ld1 { v0.s }[2], [x9] 2473; CHECK-SD-NEXT: ld1 { v1.s }[1], [x8] 2474; CHECK-SD-NEXT: add x8, sp, #8 2475; CHECK-SD-NEXT: add x9, sp, #72 2476; CHECK-SD-NEXT: movi v6.4s, #31 2477; CHECK-SD-NEXT: add x10, sp, #96 2478; CHECK-SD-NEXT: ld1 { v3.s }[2], [x8] 2479; CHECK-SD-NEXT: ld1 { v2.s }[2], [x10] 2480; CHECK-SD-NEXT: mov v5.s[1], w5 2481; CHECK-SD-NEXT: ld1 { v0.s }[3], [x9] 2482; CHECK-SD-NEXT: mov v4.s[2], w2 2483; CHECK-SD-NEXT: add x8, sp, #16 2484; CHECK-SD-NEXT: add x9, sp, #40 2485; CHECK-SD-NEXT: ld1 { v3.s }[3], [x8] 2486; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9] 2487; CHECK-SD-NEXT: bic v16.16b, v6.16b, v2.16b 2488; CHECK-SD-NEXT: bic v7.16b, v6.16b, v0.16b 2489; CHECK-SD-NEXT: mov v5.s[2], w6 2490; CHECK-SD-NEXT: and v0.16b, v0.16b, v6.16b 2491; CHECK-SD-NEXT: mov v4.s[3], w3 2492; CHECK-SD-NEXT: and v2.16b, v2.16b, v6.16b 2493; CHECK-SD-NEXT: ushr v3.4s, v3.4s, #1 2494; CHECK-SD-NEXT: ushr v1.4s, v1.4s, #1 2495; CHECK-SD-NEXT: neg v6.4s, v16.4s 2496; CHECK-SD-NEXT: neg v7.4s, v7.4s 2497; CHECK-SD-NEXT: ushl v2.4s, v5.4s, v2.4s 2498; CHECK-SD-NEXT: ushl v0.4s, v4.4s, v0.4s 2499; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v6.4s 2500; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v7.4s 2501; CHECK-SD-NEXT: orr v1.16b, v2.16b, v1.16b 2502; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b 2503; CHECK-SD-NEXT: mov w5, v1.s[1] 2504; CHECK-SD-NEXT: mov w6, v1.s[2] 2505; CHECK-SD-NEXT: fmov w4, s1 2506; CHECK-SD-NEXT: mov w1, v0.s[1] 2507; CHECK-SD-NEXT: mov w2, v0.s[2] 2508; CHECK-SD-NEXT: mov w3, v0.s[3] 2509; CHECK-SD-NEXT: fmov w0, s0 2510; CHECK-SD-NEXT: ret 2511; 2512; CHECK-GI-LABEL: fshl_v7i32: 2513; CHECK-GI: // %bb.0: // %entry 2514; CHECK-GI-NEXT: mov w11, #-1 // =0xffffffff 2515; CHECK-GI-NEXT: ldr s3, [sp, #48] 2516; CHECK-GI-NEXT: ldr s19, [sp, #56] 2517; CHECK-GI-NEXT: mov v20.s[0], w11 2518; CHECK-GI-NEXT: mov v21.s[0], w7 2519; CHECK-GI-NEXT: ldr s16, [sp, #80] 2520; CHECK-GI-NEXT: ldr s22, [sp, #88] 2521; CHECK-GI-NEXT: mov w12, #31 // =0x1f 2522; CHECK-GI-NEXT: mov w13, #1 // =0x1 2523; CHECK-GI-NEXT: ldr s6, [sp] 2524; CHECK-GI-NEXT: mov v3.s[1], v19.s[0] 2525; CHECK-GI-NEXT: mov v19.s[0], w12 2526; CHECK-GI-NEXT: mov v23.s[0], w13 2527; CHECK-GI-NEXT: mov v16.s[1], v22.s[0] 2528; CHECK-GI-NEXT: ldr s7, [sp, #64] 2529; CHECK-GI-NEXT: mov v20.s[1], w11 2530; CHECK-GI-NEXT: mov v22.s[0], w0 2531; CHECK-GI-NEXT: mov v21.s[1], v6.s[0] 2532; CHECK-GI-NEXT: ldr s24, [sp, #96] 2533; CHECK-GI-NEXT: mov v6.s[0], w12 2534; CHECK-GI-NEXT: ldr s5, [sp, #8] 2535; CHECK-GI-NEXT: ldr s18, [sp, #48] 2536; CHECK-GI-NEXT: mov v3.s[2], v7.s[0] 2537; CHECK-GI-NEXT: mov v19.s[1], w12 2538; CHECK-GI-NEXT: mov v23.s[1], w13 2539; CHECK-GI-NEXT: ldr s0, [sp, #24] 2540; CHECK-GI-NEXT: ldr s4, [sp, #32] 2541; CHECK-GI-NEXT: add x10, sp, #56 2542; CHECK-GI-NEXT: mov v16.s[2], v24.s[0] 2543; CHECK-GI-NEXT: mov v20.s[2], w11 2544; CHECK-GI-NEXT: ldr s17, [sp, #72] 2545; CHECK-GI-NEXT: ld1 { v18.s }[1], [x10] 2546; CHECK-GI-NEXT: mov v22.s[1], w1 2547; CHECK-GI-NEXT: mov v21.s[2], v5.s[0] 2548; CHECK-GI-NEXT: mov v5.s[0], w4 2549; CHECK-GI-NEXT: ldr s24, [sp, #80] 2550; CHECK-GI-NEXT: mov v6.s[1], w12 2551; CHECK-GI-NEXT: mov v0.s[1], v4.s[0] 2552; CHECK-GI-NEXT: add x9, sp, #64 2553; CHECK-GI-NEXT: add x10, sp, #88 2554; CHECK-GI-NEXT: movi v7.4s, #31 2555; CHECK-GI-NEXT: mov v3.s[3], v17.s[0] 2556; CHECK-GI-NEXT: mov v19.s[2], w12 2557; CHECK-GI-NEXT: mov v23.s[2], w13 2558; CHECK-GI-NEXT: ldr s2, [sp, #16] 2559; CHECK-GI-NEXT: ldr s1, [sp, #40] 2560; CHECK-GI-NEXT: ld1 { v18.s }[2], [x9] 2561; CHECK-GI-NEXT: ld1 { v24.s }[1], [x10] 2562; CHECK-GI-NEXT: eor v4.16b, v16.16b, v20.16b 2563; CHECK-GI-NEXT: mov v22.s[2], w2 2564; CHECK-GI-NEXT: mov v5.s[1], w5 2565; CHECK-GI-NEXT: add x8, sp, #72 2566; CHECK-GI-NEXT: add x9, sp, #96 2567; CHECK-GI-NEXT: mov v21.s[3], v2.s[0] 2568; CHECK-GI-NEXT: mov v6.s[2], w12 2569; CHECK-GI-NEXT: mov v0.s[2], v1.s[0] 2570; CHECK-GI-NEXT: ld1 { v18.s }[3], [x8] 2571; CHECK-GI-NEXT: bic v2.16b, v7.16b, v3.16b 2572; CHECK-GI-NEXT: ld1 { v24.s }[2], [x9] 2573; CHECK-GI-NEXT: and v1.16b, v4.16b, v19.16b 2574; CHECK-GI-NEXT: neg v3.4s, v23.4s 2575; CHECK-GI-NEXT: mov v22.s[3], w3 2576; CHECK-GI-NEXT: mov v5.s[2], w6 2577; CHECK-GI-NEXT: and v4.16b, v18.16b, v7.16b 2578; CHECK-GI-NEXT: ushr v7.4s, v21.4s, #1 2579; CHECK-GI-NEXT: neg v2.4s, v2.4s 2580; CHECK-GI-NEXT: and v6.16b, v24.16b, v6.16b 2581; CHECK-GI-NEXT: neg v1.4s, v1.4s 2582; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v3.4s 2583; CHECK-GI-NEXT: ushl v3.4s, v22.4s, v4.4s 2584; CHECK-GI-NEXT: ushl v2.4s, v7.4s, v2.4s 2585; CHECK-GI-NEXT: ushl v4.4s, v5.4s, v6.4s 2586; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v1.4s 2587; CHECK-GI-NEXT: orr v1.16b, v3.16b, v2.16b 2588; CHECK-GI-NEXT: orr v0.16b, v4.16b, v0.16b 2589; CHECK-GI-NEXT: mov s2, v1.s[1] 2590; CHECK-GI-NEXT: mov s3, v1.s[2] 2591; CHECK-GI-NEXT: mov s4, v1.s[3] 2592; CHECK-GI-NEXT: mov s5, v0.s[1] 2593; CHECK-GI-NEXT: mov s6, v0.s[2] 2594; CHECK-GI-NEXT: fmov w0, s1 2595; CHECK-GI-NEXT: fmov w4, s0 2596; CHECK-GI-NEXT: fmov w1, s2 2597; CHECK-GI-NEXT: fmov w2, s3 2598; CHECK-GI-NEXT: fmov w3, s4 2599; CHECK-GI-NEXT: fmov w5, s5 2600; CHECK-GI-NEXT: fmov w6, s6 2601; CHECK-GI-NEXT: ret 2602entry: 2603 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c) 2604 ret <7 x i32> %d 2605} 2606 2607define <7 x i32> @fshr_v7i32(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c) { 2608; CHECK-SD-LABEL: fshr_v7i32: 2609; CHECK-SD: // %bb.0: // %entry 2610; CHECK-SD-NEXT: fmov s1, w0 2611; CHECK-SD-NEXT: ldr s0, [sp, #48] 2612; CHECK-SD-NEXT: add x8, sp, #56 2613; CHECK-SD-NEXT: ldr s2, [sp, #80] 2614; CHECK-SD-NEXT: fmov s3, w4 2615; CHECK-SD-NEXT: add x9, sp, #64 2616; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8] 2617; CHECK-SD-NEXT: add x8, sp, #88 2618; CHECK-SD-NEXT: fmov s4, w7 2619; CHECK-SD-NEXT: mov v1.s[1], w1 2620; CHECK-SD-NEXT: ld1 { v2.s }[1], [x8] 2621; CHECK-SD-NEXT: mov x10, sp 2622; CHECK-SD-NEXT: mov v3.s[1], w5 2623; CHECK-SD-NEXT: add x8, sp, #72 2624; CHECK-SD-NEXT: movi v5.4s, #31 2625; CHECK-SD-NEXT: ld1 { v0.s }[2], [x9] 2626; CHECK-SD-NEXT: add x9, sp, #96 2627; CHECK-SD-NEXT: ld1 { v4.s }[1], [x10] 2628; CHECK-SD-NEXT: ld1 { v2.s }[2], [x9] 2629; CHECK-SD-NEXT: ldr s6, [sp, #24] 2630; CHECK-SD-NEXT: add x9, sp, #8 2631; CHECK-SD-NEXT: mov v1.s[2], w2 2632; CHECK-SD-NEXT: ld1 { v0.s }[3], [x8] 2633; CHECK-SD-NEXT: add x8, sp, #32 2634; CHECK-SD-NEXT: mov v3.s[2], w6 2635; CHECK-SD-NEXT: ld1 { v4.s }[2], [x9] 2636; CHECK-SD-NEXT: ld1 { v6.s }[1], [x8] 2637; CHECK-SD-NEXT: bic v16.16b, v5.16b, v2.16b 2638; CHECK-SD-NEXT: and v2.16b, v2.16b, v5.16b 2639; CHECK-SD-NEXT: add x8, sp, #40 2640; CHECK-SD-NEXT: add x9, sp, #16 2641; CHECK-SD-NEXT: mov v1.s[3], w3 2642; CHECK-SD-NEXT: and v7.16b, v0.16b, v5.16b 2643; CHECK-SD-NEXT: bic v0.16b, v5.16b, v0.16b 2644; CHECK-SD-NEXT: ld1 { v4.s }[3], [x9] 2645; CHECK-SD-NEXT: ld1 { v6.s }[2], [x8] 2646; CHECK-SD-NEXT: add v3.4s, v3.4s, v3.4s 2647; CHECK-SD-NEXT: neg v2.4s, v2.4s 2648; CHECK-SD-NEXT: neg v5.4s, v7.4s 2649; CHECK-SD-NEXT: add v1.4s, v1.4s, v1.4s 2650; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v16.4s 2651; CHECK-SD-NEXT: ushl v2.4s, v6.4s, v2.4s 2652; CHECK-SD-NEXT: ushl v0.4s, v1.4s, v0.4s 2653; CHECK-SD-NEXT: ushl v1.4s, v4.4s, v5.4s 2654; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2655; CHECK-SD-NEXT: orr v1.16b, v3.16b, v2.16b 2656; CHECK-SD-NEXT: mov w1, v0.s[1] 2657; CHECK-SD-NEXT: mov w2, v0.s[2] 2658; CHECK-SD-NEXT: mov w3, v0.s[3] 2659; CHECK-SD-NEXT: mov w5, v1.s[1] 2660; CHECK-SD-NEXT: mov w6, v1.s[2] 2661; CHECK-SD-NEXT: fmov w0, s0 2662; CHECK-SD-NEXT: fmov w4, s1 2663; CHECK-SD-NEXT: ret 2664; 2665; CHECK-GI-LABEL: fshr_v7i32: 2666; CHECK-GI: // %bb.0: // %entry 2667; CHECK-GI-NEXT: ldr s2, [sp, #48] 2668; CHECK-GI-NEXT: ldr s16, [sp, #56] 2669; CHECK-GI-NEXT: add x10, sp, #56 2670; CHECK-GI-NEXT: ldr s4, [sp, #80] 2671; CHECK-GI-NEXT: ldr s17, [sp, #88] 2672; CHECK-GI-NEXT: mov w11, #-1 // =0xffffffff 2673; CHECK-GI-NEXT: ldr s7, [sp, #48] 2674; CHECK-GI-NEXT: mov v2.s[1], v16.s[0] 2675; CHECK-GI-NEXT: mov v16.s[0], w0 2676; CHECK-GI-NEXT: mov v4.s[1], v17.s[0] 2677; CHECK-GI-NEXT: ldr s19, [sp, #64] 2678; CHECK-GI-NEXT: mov v18.s[0], w11 2679; CHECK-GI-NEXT: ld1 { v7.s }[1], [x10] 2680; CHECK-GI-NEXT: mov w10, #31 // =0x1f 2681; CHECK-GI-NEXT: add x9, sp, #64 2682; CHECK-GI-NEXT: mov v17.s[0], w10 2683; CHECK-GI-NEXT: ldr s21, [sp, #96] 2684; CHECK-GI-NEXT: mov v22.s[0], w4 2685; CHECK-GI-NEXT: mov v2.s[2], v19.s[0] 2686; CHECK-GI-NEXT: mov v19.s[0], w7 2687; CHECK-GI-NEXT: mov v16.s[1], w1 2688; CHECK-GI-NEXT: ld1 { v7.s }[2], [x9] 2689; CHECK-GI-NEXT: mov w9, #1 // =0x1 2690; CHECK-GI-NEXT: mov v4.s[2], v21.s[0] 2691; CHECK-GI-NEXT: mov v21.s[0], w10 2692; CHECK-GI-NEXT: mov v23.s[0], w9 2693; CHECK-GI-NEXT: ldr s6, [sp] 2694; CHECK-GI-NEXT: ldr s24, [sp, #80] 2695; CHECK-GI-NEXT: mov v17.s[1], w10 2696; CHECK-GI-NEXT: mov v18.s[1], w11 2697; CHECK-GI-NEXT: add x12, sp, #88 2698; CHECK-GI-NEXT: mov v19.s[1], v6.s[0] 2699; CHECK-GI-NEXT: add x8, sp, #72 2700; CHECK-GI-NEXT: ld1 { v24.s }[1], [x12] 2701; CHECK-GI-NEXT: mov v16.s[2], w2 2702; CHECK-GI-NEXT: mov v22.s[1], w5 2703; CHECK-GI-NEXT: mov v21.s[1], w10 2704; CHECK-GI-NEXT: mov v23.s[1], w9 2705; CHECK-GI-NEXT: ldr s5, [sp, #8] 2706; CHECK-GI-NEXT: ldr s0, [sp, #24] 2707; CHECK-GI-NEXT: ldr s3, [sp, #32] 2708; CHECK-GI-NEXT: ld1 { v7.s }[3], [x8] 2709; CHECK-GI-NEXT: movi v6.4s, #31 2710; CHECK-GI-NEXT: add x8, sp, #96 2711; CHECK-GI-NEXT: mov v17.s[2], w10 2712; CHECK-GI-NEXT: mov v18.s[2], w11 2713; CHECK-GI-NEXT: ldr s20, [sp, #72] 2714; CHECK-GI-NEXT: ld1 { v24.s }[2], [x8] 2715; CHECK-GI-NEXT: mov v19.s[2], v5.s[0] 2716; CHECK-GI-NEXT: mov v0.s[1], v3.s[0] 2717; CHECK-GI-NEXT: mov v16.s[3], w3 2718; CHECK-GI-NEXT: mov v2.s[3], v20.s[0] 2719; CHECK-GI-NEXT: mov v21.s[2], w10 2720; CHECK-GI-NEXT: mov v22.s[2], w6 2721; CHECK-GI-NEXT: mov v23.s[2], w9 2722; CHECK-GI-NEXT: ldr s1, [sp, #16] 2723; CHECK-GI-NEXT: and v5.16b, v7.16b, v6.16b 2724; CHECK-GI-NEXT: ldr s3, [sp, #40] 2725; CHECK-GI-NEXT: and v7.16b, v24.16b, v17.16b 2726; CHECK-GI-NEXT: eor v4.16b, v4.16b, v18.16b 2727; CHECK-GI-NEXT: mov v19.s[3], v1.s[0] 2728; CHECK-GI-NEXT: shl v1.4s, v16.4s, #1 2729; CHECK-GI-NEXT: mov v0.s[2], v3.s[0] 2730; CHECK-GI-NEXT: bic v2.16b, v6.16b, v2.16b 2731; CHECK-GI-NEXT: neg v5.4s, v5.4s 2732; CHECK-GI-NEXT: and v3.16b, v4.16b, v21.16b 2733; CHECK-GI-NEXT: ushl v4.4s, v22.4s, v23.4s 2734; CHECK-GI-NEXT: neg v6.4s, v7.4s 2735; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v2.4s 2736; CHECK-GI-NEXT: ushl v2.4s, v19.4s, v5.4s 2737; CHECK-GI-NEXT: ushl v3.4s, v4.4s, v3.4s 2738; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v6.4s 2739; CHECK-GI-NEXT: orr v1.16b, v1.16b, v2.16b 2740; CHECK-GI-NEXT: orr v0.16b, v3.16b, v0.16b 2741; CHECK-GI-NEXT: mov s2, v1.s[1] 2742; CHECK-GI-NEXT: mov s3, v1.s[2] 2743; CHECK-GI-NEXT: mov s4, v1.s[3] 2744; CHECK-GI-NEXT: mov s5, v0.s[1] 2745; CHECK-GI-NEXT: mov s6, v0.s[2] 2746; CHECK-GI-NEXT: fmov w0, s1 2747; CHECK-GI-NEXT: fmov w4, s0 2748; CHECK-GI-NEXT: fmov w1, s2 2749; CHECK-GI-NEXT: fmov w2, s3 2750; CHECK-GI-NEXT: fmov w3, s4 2751; CHECK-GI-NEXT: fmov w5, s5 2752; CHECK-GI-NEXT: fmov w6, s6 2753; CHECK-GI-NEXT: ret 2754entry: 2755 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c) 2756 ret <7 x i32> %d 2757} 2758 2759define <8 x i32> @fshl_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c) { 2760; CHECK-LABEL: fshl_v8i32: 2761; CHECK: // %bb.0: // %entry 2762; CHECK-NEXT: movi v6.4s, #31 2763; CHECK-NEXT: ushr v2.4s, v2.4s, #1 2764; CHECK-NEXT: ushr v3.4s, v3.4s, #1 2765; CHECK-NEXT: bic v7.16b, v6.16b, v4.16b 2766; CHECK-NEXT: bic v16.16b, v6.16b, v5.16b 2767; CHECK-NEXT: and v4.16b, v4.16b, v6.16b 2768; CHECK-NEXT: and v5.16b, v5.16b, v6.16b 2769; CHECK-NEXT: neg v6.4s, v7.4s 2770; CHECK-NEXT: neg v7.4s, v16.4s 2771; CHECK-NEXT: ushl v0.4s, v0.4s, v4.4s 2772; CHECK-NEXT: ushl v1.4s, v1.4s, v5.4s 2773; CHECK-NEXT: ushl v2.4s, v2.4s, v6.4s 2774; CHECK-NEXT: ushl v3.4s, v3.4s, v7.4s 2775; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2776; CHECK-NEXT: orr v1.16b, v1.16b, v3.16b 2777; CHECK-NEXT: ret 2778entry: 2779 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c) 2780 ret <8 x i32> %d 2781} 2782 2783define <8 x i32> @fshr_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c) { 2784; CHECK-SD-LABEL: fshr_v8i32: 2785; CHECK-SD: // %bb.0: // %entry 2786; CHECK-SD-NEXT: movi v6.4s, #31 2787; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s 2788; CHECK-SD-NEXT: add v1.4s, v1.4s, v1.4s 2789; CHECK-SD-NEXT: and v7.16b, v4.16b, v6.16b 2790; CHECK-SD-NEXT: and v16.16b, v5.16b, v6.16b 2791; CHECK-SD-NEXT: bic v4.16b, v6.16b, v4.16b 2792; CHECK-SD-NEXT: bic v5.16b, v6.16b, v5.16b 2793; CHECK-SD-NEXT: neg v6.4s, v7.4s 2794; CHECK-SD-NEXT: neg v7.4s, v16.4s 2795; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v4.4s 2796; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v5.4s 2797; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v6.4s 2798; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v7.4s 2799; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 2800; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 2801; CHECK-SD-NEXT: ret 2802; 2803; CHECK-GI-LABEL: fshr_v8i32: 2804; CHECK-GI: // %bb.0: // %entry 2805; CHECK-GI-NEXT: movi v6.4s, #31 2806; CHECK-GI-NEXT: shl v0.4s, v0.4s, #1 2807; CHECK-GI-NEXT: shl v1.4s, v1.4s, #1 2808; CHECK-GI-NEXT: and v7.16b, v4.16b, v6.16b 2809; CHECK-GI-NEXT: and v16.16b, v5.16b, v6.16b 2810; CHECK-GI-NEXT: bic v4.16b, v6.16b, v4.16b 2811; CHECK-GI-NEXT: bic v5.16b, v6.16b, v5.16b 2812; CHECK-GI-NEXT: neg v6.4s, v7.4s 2813; CHECK-GI-NEXT: neg v7.4s, v16.4s 2814; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s 2815; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v5.4s 2816; CHECK-GI-NEXT: ushl v2.4s, v2.4s, v6.4s 2817; CHECK-GI-NEXT: ushl v3.4s, v3.4s, v7.4s 2818; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 2819; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 2820; CHECK-GI-NEXT: ret 2821entry: 2822 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c) 2823 ret <8 x i32> %d 2824} 2825 2826define <2 x i64> @fshl_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 2827; CHECK-SD-LABEL: fshl_v2i64: 2828; CHECK-SD: // %bb.0: // %entry 2829; CHECK-SD-NEXT: mov w8, #63 // =0x3f 2830; CHECK-SD-NEXT: ushr v1.2d, v1.2d, #1 2831; CHECK-SD-NEXT: dup v3.2d, x8 2832; CHECK-SD-NEXT: bic v4.16b, v3.16b, v2.16b 2833; CHECK-SD-NEXT: and v2.16b, v2.16b, v3.16b 2834; CHECK-SD-NEXT: neg v3.2d, v4.2d 2835; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d 2836; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d 2837; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2838; CHECK-SD-NEXT: ret 2839; 2840; CHECK-GI-LABEL: fshl_v2i64: 2841; CHECK-GI: // %bb.0: // %entry 2842; CHECK-GI-NEXT: adrp x8, .LCPI86_0 2843; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #1 2844; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI86_0] 2845; CHECK-GI-NEXT: bic v4.16b, v3.16b, v2.16b 2846; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b 2847; CHECK-GI-NEXT: neg v3.2d, v4.2d 2848; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d 2849; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v3.2d 2850; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2851; CHECK-GI-NEXT: ret 2852entry: 2853 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) 2854 ret <2 x i64> %d 2855} 2856 2857define <2 x i64> @fshr_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 2858; CHECK-SD-LABEL: fshr_v2i64: 2859; CHECK-SD: // %bb.0: // %entry 2860; CHECK-SD-NEXT: mov w8, #63 // =0x3f 2861; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d 2862; CHECK-SD-NEXT: dup v3.2d, x8 2863; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b 2864; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b 2865; CHECK-SD-NEXT: neg v3.2d, v4.2d 2866; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d 2867; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d 2868; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 2869; CHECK-SD-NEXT: ret 2870; 2871; CHECK-GI-LABEL: fshr_v2i64: 2872; CHECK-GI: // %bb.0: // %entry 2873; CHECK-GI-NEXT: adrp x8, .LCPI87_0 2874; CHECK-GI-NEXT: shl v0.2d, v0.2d, #1 2875; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI87_0] 2876; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b 2877; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b 2878; CHECK-GI-NEXT: neg v3.2d, v4.2d 2879; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d 2880; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v3.2d 2881; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 2882; CHECK-GI-NEXT: ret 2883entry: 2884 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) 2885 ret <2 x i64> %d 2886} 2887 2888define <4 x i64> @fshl_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) { 2889; CHECK-SD-LABEL: fshl_v4i64: 2890; CHECK-SD: // %bb.0: // %entry 2891; CHECK-SD-NEXT: mov w8, #63 // =0x3f 2892; CHECK-SD-NEXT: ushr v2.2d, v2.2d, #1 2893; CHECK-SD-NEXT: ushr v3.2d, v3.2d, #1 2894; CHECK-SD-NEXT: dup v6.2d, x8 2895; CHECK-SD-NEXT: bic v7.16b, v6.16b, v4.16b 2896; CHECK-SD-NEXT: bic v16.16b, v6.16b, v5.16b 2897; CHECK-SD-NEXT: and v4.16b, v4.16b, v6.16b 2898; CHECK-SD-NEXT: and v5.16b, v5.16b, v6.16b 2899; CHECK-SD-NEXT: neg v6.2d, v7.2d 2900; CHECK-SD-NEXT: neg v7.2d, v16.2d 2901; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v4.2d 2902; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v5.2d 2903; CHECK-SD-NEXT: ushl v2.2d, v2.2d, v6.2d 2904; CHECK-SD-NEXT: ushl v3.2d, v3.2d, v7.2d 2905; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 2906; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 2907; CHECK-SD-NEXT: ret 2908; 2909; CHECK-GI-LABEL: fshl_v4i64: 2910; CHECK-GI: // %bb.0: // %entry 2911; CHECK-GI-NEXT: adrp x8, .LCPI88_0 2912; CHECK-GI-NEXT: ushr v2.2d, v2.2d, #1 2913; CHECK-GI-NEXT: ushr v3.2d, v3.2d, #1 2914; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI88_0] 2915; CHECK-GI-NEXT: bic v7.16b, v6.16b, v4.16b 2916; CHECK-GI-NEXT: bic v16.16b, v6.16b, v5.16b 2917; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b 2918; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b 2919; CHECK-GI-NEXT: neg v6.2d, v7.2d 2920; CHECK-GI-NEXT: neg v7.2d, v16.2d 2921; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v4.2d 2922; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v5.2d 2923; CHECK-GI-NEXT: ushl v2.2d, v2.2d, v6.2d 2924; CHECK-GI-NEXT: ushl v3.2d, v3.2d, v7.2d 2925; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 2926; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 2927; CHECK-GI-NEXT: ret 2928entry: 2929 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) 2930 ret <4 x i64> %d 2931} 2932 2933define <4 x i64> @fshr_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) { 2934; CHECK-SD-LABEL: fshr_v4i64: 2935; CHECK-SD: // %bb.0: // %entry 2936; CHECK-SD-NEXT: mov w8, #63 // =0x3f 2937; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d 2938; CHECK-SD-NEXT: add v1.2d, v1.2d, v1.2d 2939; CHECK-SD-NEXT: dup v6.2d, x8 2940; CHECK-SD-NEXT: and v7.16b, v4.16b, v6.16b 2941; CHECK-SD-NEXT: and v16.16b, v5.16b, v6.16b 2942; CHECK-SD-NEXT: bic v4.16b, v6.16b, v4.16b 2943; CHECK-SD-NEXT: bic v5.16b, v6.16b, v5.16b 2944; CHECK-SD-NEXT: neg v6.2d, v7.2d 2945; CHECK-SD-NEXT: neg v7.2d, v16.2d 2946; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v4.2d 2947; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v5.2d 2948; CHECK-SD-NEXT: ushl v2.2d, v2.2d, v6.2d 2949; CHECK-SD-NEXT: ushl v3.2d, v3.2d, v7.2d 2950; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 2951; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 2952; CHECK-SD-NEXT: ret 2953; 2954; CHECK-GI-LABEL: fshr_v4i64: 2955; CHECK-GI: // %bb.0: // %entry 2956; CHECK-GI-NEXT: adrp x8, .LCPI89_0 2957; CHECK-GI-NEXT: shl v0.2d, v0.2d, #1 2958; CHECK-GI-NEXT: shl v1.2d, v1.2d, #1 2959; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI89_0] 2960; CHECK-GI-NEXT: and v7.16b, v4.16b, v6.16b 2961; CHECK-GI-NEXT: and v16.16b, v5.16b, v6.16b 2962; CHECK-GI-NEXT: bic v4.16b, v6.16b, v4.16b 2963; CHECK-GI-NEXT: bic v5.16b, v6.16b, v5.16b 2964; CHECK-GI-NEXT: neg v6.2d, v7.2d 2965; CHECK-GI-NEXT: neg v7.2d, v16.2d 2966; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v4.2d 2967; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v5.2d 2968; CHECK-GI-NEXT: ushl v2.2d, v2.2d, v6.2d 2969; CHECK-GI-NEXT: ushl v3.2d, v3.2d, v7.2d 2970; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 2971; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 2972; CHECK-GI-NEXT: ret 2973entry: 2974 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) 2975 ret <4 x i64> %d 2976} 2977 2978define <2 x i128> @fshl_v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) { 2979; CHECK-SD-LABEL: fshl_v2i128: 2980; CHECK-SD: // %bb.0: // %entry 2981; CHECK-SD-NEXT: ldr x8, [sp] 2982; CHECK-SD-NEXT: ldr x10, [sp, #16] 2983; CHECK-SD-NEXT: tst x8, #0x40 2984; CHECK-SD-NEXT: mvn w13, w8 2985; CHECK-SD-NEXT: mvn w16, w10 2986; CHECK-SD-NEXT: csel x9, x5, x0, ne 2987; CHECK-SD-NEXT: csel x11, x4, x5, ne 2988; CHECK-SD-NEXT: csel x14, x0, x1, ne 2989; CHECK-SD-NEXT: lsl x12, x9, x8 2990; CHECK-SD-NEXT: lsr x11, x11, #1 2991; CHECK-SD-NEXT: lsr x9, x9, #1 2992; CHECK-SD-NEXT: tst x10, #0x40 2993; CHECK-SD-NEXT: lsl x8, x14, x8 2994; CHECK-SD-NEXT: csel x14, x7, x2, ne 2995; CHECK-SD-NEXT: csel x15, x6, x7, ne 2996; CHECK-SD-NEXT: lsr x11, x11, x13 2997; CHECK-SD-NEXT: lsr x9, x9, x13 2998; CHECK-SD-NEXT: lsr x13, x15, #1 2999; CHECK-SD-NEXT: lsr x15, x14, #1 3000; CHECK-SD-NEXT: csel x17, x2, x3, ne 3001; CHECK-SD-NEXT: lsl x14, x14, x10 3002; CHECK-SD-NEXT: orr x0, x12, x11 3003; CHECK-SD-NEXT: lsr x13, x13, x16 3004; CHECK-SD-NEXT: lsl x10, x17, x10 3005; CHECK-SD-NEXT: lsr x15, x15, x16 3006; CHECK-SD-NEXT: orr x1, x8, x9 3007; CHECK-SD-NEXT: orr x2, x14, x13 3008; CHECK-SD-NEXT: orr x3, x10, x15 3009; CHECK-SD-NEXT: ret 3010; 3011; CHECK-GI-LABEL: fshl_v2i128: 3012; CHECK-GI: // %bb.0: // %entry 3013; CHECK-GI-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill 3014; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 3015; CHECK-GI-NEXT: .cfi_offset w19, -16 3016; CHECK-GI-NEXT: ldr x11, [sp, #16] 3017; CHECK-GI-NEXT: mov w10, #64 // =0x40 3018; CHECK-GI-NEXT: ldr x12, [sp, #32] 3019; CHECK-GI-NEXT: mov w13, #127 // =0x7f 3020; CHECK-GI-NEXT: and x9, x11, #0x7f 3021; CHECK-GI-NEXT: and x14, x12, #0x7f 3022; CHECK-GI-NEXT: mvn x15, x11 3023; CHECK-GI-NEXT: sub x8, x10, x9 3024; CHECK-GI-NEXT: sub x16, x9, #64 3025; CHECK-GI-NEXT: lsl x19, x1, x9 3026; CHECK-GI-NEXT: lsr x18, x0, x8 3027; CHECK-GI-NEXT: lsl x17, x0, x9 3028; CHECK-GI-NEXT: lsl x16, x0, x16 3029; CHECK-GI-NEXT: cmp x9, #64 3030; CHECK-GI-NEXT: bic x0, x13, x11 3031; CHECK-GI-NEXT: mvn x8, x12 3032; CHECK-GI-NEXT: orr x18, x18, x19 3033; CHECK-GI-NEXT: csel x9, x17, xzr, lo 3034; CHECK-GI-NEXT: sub x17, x14, #64 3035; CHECK-GI-NEXT: csel x16, x18, x16, lo 3036; CHECK-GI-NEXT: tst x11, #0x7f 3037; CHECK-GI-NEXT: sub x11, x10, x14 3038; CHECK-GI-NEXT: lsr x11, x2, x11 3039; CHECK-GI-NEXT: lsl x18, x3, x14 3040; CHECK-GI-NEXT: csel x16, x1, x16, eq 3041; CHECK-GI-NEXT: lsl x1, x2, x14 3042; CHECK-GI-NEXT: lsl x17, x2, x17 3043; CHECK-GI-NEXT: cmp x14, #64 3044; CHECK-GI-NEXT: lsl x14, x5, #63 3045; CHECK-GI-NEXT: orr x11, x11, x18 3046; CHECK-GI-NEXT: bic x13, x13, x12 3047; CHECK-GI-NEXT: csel x18, x1, xzr, lo 3048; CHECK-GI-NEXT: csel x11, x11, x17, lo 3049; CHECK-GI-NEXT: tst x12, #0x7f 3050; CHECK-GI-NEXT: lsr x12, x5, #1 3051; CHECK-GI-NEXT: orr x14, x14, x4, lsr #1 3052; CHECK-GI-NEXT: lsl x17, x7, #63 3053; CHECK-GI-NEXT: sub x1, x10, x0 3054; CHECK-GI-NEXT: csel x11, x3, x11, eq 3055; CHECK-GI-NEXT: sub x2, x0, #64 3056; CHECK-GI-NEXT: lsr x3, x14, x0 3057; CHECK-GI-NEXT: lsl x1, x12, x1 3058; CHECK-GI-NEXT: lsr x4, x7, #1 3059; CHECK-GI-NEXT: orr x17, x17, x6, lsr #1 3060; CHECK-GI-NEXT: lsr x2, x12, x2 3061; CHECK-GI-NEXT: cmp x0, #64 3062; CHECK-GI-NEXT: orr x1, x3, x1 3063; CHECK-GI-NEXT: sub x10, x10, x13 3064; CHECK-GI-NEXT: lsr x12, x12, x0 3065; CHECK-GI-NEXT: csel x1, x1, x2, lo 3066; CHECK-GI-NEXT: tst x15, #0x7f 3067; CHECK-GI-NEXT: sub x15, x13, #64 3068; CHECK-GI-NEXT: lsr x2, x17, x13 3069; CHECK-GI-NEXT: lsl x10, x4, x10 3070; CHECK-GI-NEXT: csel x14, x14, x1, eq 3071; CHECK-GI-NEXT: cmp x0, #64 3072; CHECK-GI-NEXT: lsr x15, x4, x15 3073; CHECK-GI-NEXT: lsr x0, x4, x13 3074; CHECK-GI-NEXT: csel x12, x12, xzr, lo 3075; CHECK-GI-NEXT: orr x10, x2, x10 3076; CHECK-GI-NEXT: cmp x13, #64 3077; CHECK-GI-NEXT: csel x10, x10, x15, lo 3078; CHECK-GI-NEXT: tst x8, #0x7f 3079; CHECK-GI-NEXT: orr x1, x16, x12 3080; CHECK-GI-NEXT: csel x8, x17, x10, eq 3081; CHECK-GI-NEXT: cmp x13, #64 3082; CHECK-GI-NEXT: csel x10, x0, xzr, lo 3083; CHECK-GI-NEXT: orr x0, x9, x14 3084; CHECK-GI-NEXT: orr x2, x18, x8 3085; CHECK-GI-NEXT: orr x3, x11, x10 3086; CHECK-GI-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload 3087; CHECK-GI-NEXT: ret 3088entry: 3089 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) 3090 ret <2 x i128> %d 3091} 3092 3093define <2 x i128> @fshr_v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) { 3094; CHECK-SD-LABEL: fshr_v2i128: 3095; CHECK-SD: // %bb.0: // %entry 3096; CHECK-SD-NEXT: ldr x8, [sp] 3097; CHECK-SD-NEXT: ldr x10, [sp, #16] 3098; CHECK-SD-NEXT: tst x8, #0x40 3099; CHECK-SD-NEXT: mvn w13, w8 3100; CHECK-SD-NEXT: csel x9, x4, x5, eq 3101; CHECK-SD-NEXT: csel x11, x5, x0, eq 3102; CHECK-SD-NEXT: csel x14, x0, x1, eq 3103; CHECK-SD-NEXT: tst x10, #0x40 3104; CHECK-SD-NEXT: lsr x9, x9, x8 3105; CHECK-SD-NEXT: lsl x12, x11, #1 3106; CHECK-SD-NEXT: lsr x8, x11, x8 3107; CHECK-SD-NEXT: lsl x11, x14, #1 3108; CHECK-SD-NEXT: csel x14, x7, x2, eq 3109; CHECK-SD-NEXT: csel x15, x2, x3, eq 3110; CHECK-SD-NEXT: csel x16, x6, x7, eq 3111; CHECK-SD-NEXT: lsl x17, x14, #1 3112; CHECK-SD-NEXT: lsl x15, x15, #1 3113; CHECK-SD-NEXT: lsl x12, x12, x13 3114; CHECK-SD-NEXT: lsl x11, x11, x13 3115; CHECK-SD-NEXT: lsr x13, x16, x10 3116; CHECK-SD-NEXT: mvn w16, w10 3117; CHECK-SD-NEXT: lsr x10, x14, x10 3118; CHECK-SD-NEXT: lsl x17, x17, x16 3119; CHECK-SD-NEXT: lsl x14, x15, x16 3120; CHECK-SD-NEXT: orr x0, x12, x9 3121; CHECK-SD-NEXT: orr x1, x11, x8 3122; CHECK-SD-NEXT: orr x2, x17, x13 3123; CHECK-SD-NEXT: orr x3, x14, x10 3124; CHECK-SD-NEXT: ret 3125; 3126; CHECK-GI-LABEL: fshr_v2i128: 3127; CHECK-GI: // %bb.0: // %entry 3128; CHECK-GI-NEXT: ldr x9, [sp] 3129; CHECK-GI-NEXT: lsl x12, x1, #1 3130; CHECK-GI-NEXT: mov w11, #127 // =0x7f 3131; CHECK-GI-NEXT: mov w14, #64 // =0x40 3132; CHECK-GI-NEXT: lsl x15, x0, #1 3133; CHECK-GI-NEXT: ldr x8, [sp, #16] 3134; CHECK-GI-NEXT: bic x13, x11, x9 3135; CHECK-GI-NEXT: orr x12, x12, x0, lsr #63 3136; CHECK-GI-NEXT: lsl x1, x3, #1 3137; CHECK-GI-NEXT: sub x17, x14, x13 3138; CHECK-GI-NEXT: sub x18, x13, #64 3139; CHECK-GI-NEXT: lsl x3, x15, x13 3140; CHECK-GI-NEXT: lsr x17, x15, x17 3141; CHECK-GI-NEXT: lsl x0, x12, x13 3142; CHECK-GI-NEXT: lsl x15, x15, x18 3143; CHECK-GI-NEXT: bic x11, x11, x8 3144; CHECK-GI-NEXT: lsl x18, x2, #1 3145; CHECK-GI-NEXT: cmp x13, #64 3146; CHECK-GI-NEXT: orr x17, x17, x0 3147; CHECK-GI-NEXT: orr x13, x1, x2, lsr #63 3148; CHECK-GI-NEXT: mvn x16, x9 3149; CHECK-GI-NEXT: csel x15, x17, x15, lo 3150; CHECK-GI-NEXT: sub x17, x14, x11 3151; CHECK-GI-NEXT: csel x0, x3, xzr, lo 3152; CHECK-GI-NEXT: tst x16, #0x7f 3153; CHECK-GI-NEXT: sub x16, x11, #64 3154; CHECK-GI-NEXT: lsr x17, x18, x17 3155; CHECK-GI-NEXT: lsl x2, x13, x11 3156; CHECK-GI-NEXT: lsl x1, x18, x11 3157; CHECK-GI-NEXT: csel x12, x12, x15, eq 3158; CHECK-GI-NEXT: lsl x15, x18, x16 3159; CHECK-GI-NEXT: and x10, x9, #0x7f 3160; CHECK-GI-NEXT: cmp x11, #64 3161; CHECK-GI-NEXT: mvn x11, x8 3162; CHECK-GI-NEXT: orr x16, x17, x2 3163; CHECK-GI-NEXT: csel x17, x1, xzr, lo 3164; CHECK-GI-NEXT: csel x15, x16, x15, lo 3165; CHECK-GI-NEXT: tst x11, #0x7f 3166; CHECK-GI-NEXT: sub x11, x14, x10 3167; CHECK-GI-NEXT: sub x16, x10, #64 3168; CHECK-GI-NEXT: lsr x18, x4, x10 3169; CHECK-GI-NEXT: lsl x11, x5, x11 3170; CHECK-GI-NEXT: csel x13, x13, x15, eq 3171; CHECK-GI-NEXT: lsr x15, x5, x16 3172; CHECK-GI-NEXT: and x1, x8, #0x7f 3173; CHECK-GI-NEXT: orr x11, x18, x11 3174; CHECK-GI-NEXT: cmp x10, #64 3175; CHECK-GI-NEXT: lsr x16, x5, x10 3176; CHECK-GI-NEXT: csel x11, x11, x15, lo 3177; CHECK-GI-NEXT: tst x9, #0x7f 3178; CHECK-GI-NEXT: sub x9, x14, x1 3179; CHECK-GI-NEXT: sub x14, x1, #64 3180; CHECK-GI-NEXT: lsr x15, x6, x1 3181; CHECK-GI-NEXT: lsl x9, x7, x9 3182; CHECK-GI-NEXT: csel x11, x4, x11, eq 3183; CHECK-GI-NEXT: cmp x10, #64 3184; CHECK-GI-NEXT: lsr x10, x7, x14 3185; CHECK-GI-NEXT: csel x14, x16, xzr, lo 3186; CHECK-GI-NEXT: orr x9, x15, x9 3187; CHECK-GI-NEXT: cmp x1, #64 3188; CHECK-GI-NEXT: lsr x15, x7, x1 3189; CHECK-GI-NEXT: csel x9, x9, x10, lo 3190; CHECK-GI-NEXT: tst x8, #0x7f 3191; CHECK-GI-NEXT: csel x8, x6, x9, eq 3192; CHECK-GI-NEXT: cmp x1, #64 3193; CHECK-GI-NEXT: orr x0, x0, x11 3194; CHECK-GI-NEXT: csel x9, x15, xzr, lo 3195; CHECK-GI-NEXT: orr x1, x12, x14 3196; CHECK-GI-NEXT: orr x2, x17, x8 3197; CHECK-GI-NEXT: orr x3, x13, x9 3198; CHECK-GI-NEXT: ret 3199entry: 3200 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) 3201 ret <2 x i128> %d 3202} 3203 3204define <8 x i8> @rotl_v8i8_c(<8 x i8> %a) { 3205; CHECK-SD-LABEL: rotl_v8i8_c: 3206; CHECK-SD: // %bb.0: // %entry 3207; CHECK-SD-NEXT: shl v1.8b, v0.8b, #3 3208; CHECK-SD-NEXT: usra v1.8b, v0.8b, #5 3209; CHECK-SD-NEXT: fmov d0, d1 3210; CHECK-SD-NEXT: ret 3211; 3212; CHECK-GI-LABEL: rotl_v8i8_c: 3213; CHECK-GI: // %bb.0: // %entry 3214; CHECK-GI-NEXT: shl v1.8b, v0.8b, #3 3215; CHECK-GI-NEXT: ushr v0.8b, v0.8b, #5 3216; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 3217; CHECK-GI-NEXT: ret 3218entry: 3219 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %a, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3220 ret <8 x i8> %d 3221} 3222 3223define <8 x i8> @rotr_v8i8_c(<8 x i8> %a) { 3224; CHECK-SD-LABEL: rotr_v8i8_c: 3225; CHECK-SD: // %bb.0: // %entry 3226; CHECK-SD-NEXT: shl v1.8b, v0.8b, #5 3227; CHECK-SD-NEXT: usra v1.8b, v0.8b, #3 3228; CHECK-SD-NEXT: fmov d0, d1 3229; CHECK-SD-NEXT: ret 3230; 3231; CHECK-GI-LABEL: rotr_v8i8_c: 3232; CHECK-GI: // %bb.0: // %entry 3233; CHECK-GI-NEXT: ushr v1.8b, v0.8b, #3 3234; CHECK-GI-NEXT: shl v0.8b, v0.8b, #5 3235; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 3236; CHECK-GI-NEXT: ret 3237entry: 3238 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %a, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3239 ret <8 x i8> %d 3240} 3241 3242define <16 x i8> @rotl_v16i8_c(<16 x i8> %a) { 3243; CHECK-SD-LABEL: rotl_v16i8_c: 3244; CHECK-SD: // %bb.0: // %entry 3245; CHECK-SD-NEXT: shl v1.16b, v0.16b, #3 3246; CHECK-SD-NEXT: usra v1.16b, v0.16b, #5 3247; CHECK-SD-NEXT: mov v0.16b, v1.16b 3248; CHECK-SD-NEXT: ret 3249; 3250; CHECK-GI-LABEL: rotl_v16i8_c: 3251; CHECK-GI: // %bb.0: // %entry 3252; CHECK-GI-NEXT: shl v1.16b, v0.16b, #3 3253; CHECK-GI-NEXT: ushr v0.16b, v0.16b, #5 3254; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3255; CHECK-GI-NEXT: ret 3256entry: 3257 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3258 ret <16 x i8> %d 3259} 3260 3261define <16 x i8> @rotr_v16i8_c(<16 x i8> %a) { 3262; CHECK-SD-LABEL: rotr_v16i8_c: 3263; CHECK-SD: // %bb.0: // %entry 3264; CHECK-SD-NEXT: shl v1.16b, v0.16b, #5 3265; CHECK-SD-NEXT: usra v1.16b, v0.16b, #3 3266; CHECK-SD-NEXT: mov v0.16b, v1.16b 3267; CHECK-SD-NEXT: ret 3268; 3269; CHECK-GI-LABEL: rotr_v16i8_c: 3270; CHECK-GI: // %bb.0: // %entry 3271; CHECK-GI-NEXT: ushr v1.16b, v0.16b, #3 3272; CHECK-GI-NEXT: shl v0.16b, v0.16b, #5 3273; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3274; CHECK-GI-NEXT: ret 3275entry: 3276 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3277 ret <16 x i8> %d 3278} 3279 3280define <4 x i16> @rotl_v4i16_c(<4 x i16> %a) { 3281; CHECK-SD-LABEL: rotl_v4i16_c: 3282; CHECK-SD: // %bb.0: // %entry 3283; CHECK-SD-NEXT: shl v1.4h, v0.4h, #3 3284; CHECK-SD-NEXT: usra v1.4h, v0.4h, #13 3285; CHECK-SD-NEXT: fmov d0, d1 3286; CHECK-SD-NEXT: ret 3287; 3288; CHECK-GI-LABEL: rotl_v4i16_c: 3289; CHECK-GI: // %bb.0: // %entry 3290; CHECK-GI-NEXT: shl v1.4h, v0.4h, #3 3291; CHECK-GI-NEXT: ushr v0.4h, v0.4h, #13 3292; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 3293; CHECK-GI-NEXT: ret 3294entry: 3295 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %a, <4 x i16> <i16 3, i16 3, i16 3, i16 3>) 3296 ret <4 x i16> %d 3297} 3298 3299define <4 x i16> @rotr_v4i16_c(<4 x i16> %a) { 3300; CHECK-SD-LABEL: rotr_v4i16_c: 3301; CHECK-SD: // %bb.0: // %entry 3302; CHECK-SD-NEXT: shl v1.4h, v0.4h, #13 3303; CHECK-SD-NEXT: usra v1.4h, v0.4h, #3 3304; CHECK-SD-NEXT: fmov d0, d1 3305; CHECK-SD-NEXT: ret 3306; 3307; CHECK-GI-LABEL: rotr_v4i16_c: 3308; CHECK-GI: // %bb.0: // %entry 3309; CHECK-GI-NEXT: ushr v1.4h, v0.4h, #3 3310; CHECK-GI-NEXT: shl v0.4h, v0.4h, #13 3311; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 3312; CHECK-GI-NEXT: ret 3313entry: 3314 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %a, <4 x i16> <i16 3, i16 3, i16 3, i16 3>) 3315 ret <4 x i16> %d 3316} 3317 3318define <7 x i16> @rotl_v7i16_c(<7 x i16> %a) { 3319; CHECK-SD-LABEL: rotl_v7i16_c: 3320; CHECK-SD: // %bb.0: // %entry 3321; CHECK-SD-NEXT: adrp x8, .LCPI98_0 3322; CHECK-SD-NEXT: adrp x9, .LCPI98_1 3323; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI98_0] 3324; CHECK-SD-NEXT: ldr q2, [x9, :lo12:.LCPI98_1] 3325; CHECK-SD-NEXT: ushl v1.8h, v0.8h, v1.8h 3326; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 3327; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 3328; CHECK-SD-NEXT: ret 3329; 3330; CHECK-GI-LABEL: rotl_v7i16_c: 3331; CHECK-GI: // %bb.0: // %entry 3332; CHECK-GI-NEXT: mov w8, #13 // =0xd 3333; CHECK-GI-NEXT: mov w9, #3 // =0x3 3334; CHECK-GI-NEXT: fmov s1, w8 3335; CHECK-GI-NEXT: fmov s2, w9 3336; CHECK-GI-NEXT: mov v1.h[1], w8 3337; CHECK-GI-NEXT: mov v2.h[1], w9 3338; CHECK-GI-NEXT: mov v1.h[2], w8 3339; CHECK-GI-NEXT: mov v2.h[2], w9 3340; CHECK-GI-NEXT: mov v1.h[3], w8 3341; CHECK-GI-NEXT: mov v2.h[3], w9 3342; CHECK-GI-NEXT: mov v1.h[4], w8 3343; CHECK-GI-NEXT: mov v2.h[4], w9 3344; CHECK-GI-NEXT: mov v1.h[5], w8 3345; CHECK-GI-NEXT: mov v2.h[5], w9 3346; CHECK-GI-NEXT: mov v1.h[6], w8 3347; CHECK-GI-NEXT: mov v2.h[6], w9 3348; CHECK-GI-NEXT: neg v1.8h, v1.8h 3349; CHECK-GI-NEXT: ushl v2.8h, v0.8h, v2.8h 3350; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v1.8h 3351; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3352; CHECK-GI-NEXT: ret 3353entry: 3354 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %a, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 3355 ret <7 x i16> %d 3356} 3357 3358define <7 x i16> @rotr_v7i16_c(<7 x i16> %a) { 3359; CHECK-SD-LABEL: rotr_v7i16_c: 3360; CHECK-SD: // %bb.0: // %entry 3361; CHECK-SD-NEXT: adrp x8, .LCPI99_0 3362; CHECK-SD-NEXT: adrp x9, .LCPI99_1 3363; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI99_0] 3364; CHECK-SD-NEXT: ldr q2, [x9, :lo12:.LCPI99_1] 3365; CHECK-SD-NEXT: ushl v1.8h, v0.8h, v1.8h 3366; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h 3367; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 3368; CHECK-SD-NEXT: ret 3369; 3370; CHECK-GI-LABEL: rotr_v7i16_c: 3371; CHECK-GI: // %bb.0: // %entry 3372; CHECK-GI-NEXT: mov w8, #3 // =0x3 3373; CHECK-GI-NEXT: mov w9, #13 // =0xd 3374; CHECK-GI-NEXT: fmov s1, w8 3375; CHECK-GI-NEXT: fmov s2, w9 3376; CHECK-GI-NEXT: mov v1.h[1], w8 3377; CHECK-GI-NEXT: mov v2.h[1], w9 3378; CHECK-GI-NEXT: mov v1.h[2], w8 3379; CHECK-GI-NEXT: mov v2.h[2], w9 3380; CHECK-GI-NEXT: mov v1.h[3], w8 3381; CHECK-GI-NEXT: mov v2.h[3], w9 3382; CHECK-GI-NEXT: mov v1.h[4], w8 3383; CHECK-GI-NEXT: mov v2.h[4], w9 3384; CHECK-GI-NEXT: mov v1.h[5], w8 3385; CHECK-GI-NEXT: mov v2.h[5], w9 3386; CHECK-GI-NEXT: mov v1.h[6], w8 3387; CHECK-GI-NEXT: mov v2.h[6], w9 3388; CHECK-GI-NEXT: neg v1.8h, v1.8h 3389; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h 3390; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h 3391; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3392; CHECK-GI-NEXT: ret 3393entry: 3394 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %a, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 3395 ret <7 x i16> %d 3396} 3397 3398define <8 x i16> @rotl_v8i16_c(<8 x i16> %a) { 3399; CHECK-SD-LABEL: rotl_v8i16_c: 3400; CHECK-SD: // %bb.0: // %entry 3401; CHECK-SD-NEXT: shl v1.8h, v0.8h, #3 3402; CHECK-SD-NEXT: usra v1.8h, v0.8h, #13 3403; CHECK-SD-NEXT: mov v0.16b, v1.16b 3404; CHECK-SD-NEXT: ret 3405; 3406; CHECK-GI-LABEL: rotl_v8i16_c: 3407; CHECK-GI: // %bb.0: // %entry 3408; CHECK-GI-NEXT: shl v1.8h, v0.8h, #3 3409; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #13 3410; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3411; CHECK-GI-NEXT: ret 3412entry: 3413 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %a, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 3414 ret <8 x i16> %d 3415} 3416 3417define <8 x i16> @rotr_v8i16_c(<8 x i16> %a) { 3418; CHECK-SD-LABEL: rotr_v8i16_c: 3419; CHECK-SD: // %bb.0: // %entry 3420; CHECK-SD-NEXT: shl v1.8h, v0.8h, #13 3421; CHECK-SD-NEXT: usra v1.8h, v0.8h, #3 3422; CHECK-SD-NEXT: mov v0.16b, v1.16b 3423; CHECK-SD-NEXT: ret 3424; 3425; CHECK-GI-LABEL: rotr_v8i16_c: 3426; CHECK-GI: // %bb.0: // %entry 3427; CHECK-GI-NEXT: ushr v1.8h, v0.8h, #3 3428; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13 3429; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3430; CHECK-GI-NEXT: ret 3431entry: 3432 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %a, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 3433 ret <8 x i16> %d 3434} 3435 3436define <16 x i16> @rotl_v16i16_c(<16 x i16> %a) { 3437; CHECK-SD-LABEL: rotl_v16i16_c: 3438; CHECK-SD: // %bb.0: // %entry 3439; CHECK-SD-NEXT: shl v2.8h, v0.8h, #3 3440; CHECK-SD-NEXT: shl v3.8h, v1.8h, #3 3441; CHECK-SD-NEXT: usra v2.8h, v0.8h, #13 3442; CHECK-SD-NEXT: usra v3.8h, v1.8h, #13 3443; CHECK-SD-NEXT: mov v0.16b, v2.16b 3444; CHECK-SD-NEXT: mov v1.16b, v3.16b 3445; CHECK-SD-NEXT: ret 3446; 3447; CHECK-GI-LABEL: rotl_v16i16_c: 3448; CHECK-GI: // %bb.0: // %entry 3449; CHECK-GI-NEXT: shl v2.8h, v0.8h, #3 3450; CHECK-GI-NEXT: shl v3.8h, v1.8h, #3 3451; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #13 3452; CHECK-GI-NEXT: ushr v1.8h, v1.8h, #13 3453; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3454; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 3455; CHECK-GI-NEXT: ret 3456entry: 3457 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %a, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 3458 ret <16 x i16> %d 3459} 3460 3461define <16 x i16> @rotr_v16i16_c(<16 x i16> %a) { 3462; CHECK-SD-LABEL: rotr_v16i16_c: 3463; CHECK-SD: // %bb.0: // %entry 3464; CHECK-SD-NEXT: shl v2.8h, v0.8h, #13 3465; CHECK-SD-NEXT: shl v3.8h, v1.8h, #13 3466; CHECK-SD-NEXT: usra v2.8h, v0.8h, #3 3467; CHECK-SD-NEXT: usra v3.8h, v1.8h, #3 3468; CHECK-SD-NEXT: mov v0.16b, v2.16b 3469; CHECK-SD-NEXT: mov v1.16b, v3.16b 3470; CHECK-SD-NEXT: ret 3471; 3472; CHECK-GI-LABEL: rotr_v16i16_c: 3473; CHECK-GI: // %bb.0: // %entry 3474; CHECK-GI-NEXT: ushr v2.8h, v0.8h, #3 3475; CHECK-GI-NEXT: ushr v3.8h, v1.8h, #3 3476; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13 3477; CHECK-GI-NEXT: shl v1.8h, v1.8h, #13 3478; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3479; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 3480; CHECK-GI-NEXT: ret 3481entry: 3482 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %a, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 3483 ret <16 x i16> %d 3484} 3485 3486define <2 x i32> @rotl_v2i32_c(<2 x i32> %a) { 3487; CHECK-SD-LABEL: rotl_v2i32_c: 3488; CHECK-SD: // %bb.0: // %entry 3489; CHECK-SD-NEXT: shl v1.2s, v0.2s, #3 3490; CHECK-SD-NEXT: usra v1.2s, v0.2s, #29 3491; CHECK-SD-NEXT: fmov d0, d1 3492; CHECK-SD-NEXT: ret 3493; 3494; CHECK-GI-LABEL: rotl_v2i32_c: 3495; CHECK-GI: // %bb.0: // %entry 3496; CHECK-GI-NEXT: shl v1.2s, v0.2s, #3 3497; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #29 3498; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 3499; CHECK-GI-NEXT: ret 3500entry: 3501 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %a, <2 x i32> <i32 3, i32 3>) 3502 ret <2 x i32> %d 3503} 3504 3505define <2 x i32> @rotr_v2i32_c(<2 x i32> %a) { 3506; CHECK-SD-LABEL: rotr_v2i32_c: 3507; CHECK-SD: // %bb.0: // %entry 3508; CHECK-SD-NEXT: shl v1.2s, v0.2s, #29 3509; CHECK-SD-NEXT: usra v1.2s, v0.2s, #3 3510; CHECK-SD-NEXT: fmov d0, d1 3511; CHECK-SD-NEXT: ret 3512; 3513; CHECK-GI-LABEL: rotr_v2i32_c: 3514; CHECK-GI: // %bb.0: // %entry 3515; CHECK-GI-NEXT: ushr v1.2s, v0.2s, #3 3516; CHECK-GI-NEXT: shl v0.2s, v0.2s, #29 3517; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b 3518; CHECK-GI-NEXT: ret 3519entry: 3520 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %a, <2 x i32> <i32 3, i32 3>) 3521 ret <2 x i32> %d 3522} 3523 3524define <4 x i32> @rotl_v4i32_c(<4 x i32> %a) { 3525; CHECK-SD-LABEL: rotl_v4i32_c: 3526; CHECK-SD: // %bb.0: // %entry 3527; CHECK-SD-NEXT: shl v1.4s, v0.4s, #3 3528; CHECK-SD-NEXT: usra v1.4s, v0.4s, #29 3529; CHECK-SD-NEXT: mov v0.16b, v1.16b 3530; CHECK-SD-NEXT: ret 3531; 3532; CHECK-GI-LABEL: rotl_v4i32_c: 3533; CHECK-GI: // %bb.0: // %entry 3534; CHECK-GI-NEXT: shl v1.4s, v0.4s, #3 3535; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #29 3536; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3537; CHECK-GI-NEXT: ret 3538entry: 3539 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) 3540 ret <4 x i32> %d 3541} 3542 3543define <4 x i32> @rotr_v4i32_c(<4 x i32> %a) { 3544; CHECK-SD-LABEL: rotr_v4i32_c: 3545; CHECK-SD: // %bb.0: // %entry 3546; CHECK-SD-NEXT: shl v1.4s, v0.4s, #29 3547; CHECK-SD-NEXT: usra v1.4s, v0.4s, #3 3548; CHECK-SD-NEXT: mov v0.16b, v1.16b 3549; CHECK-SD-NEXT: ret 3550; 3551; CHECK-GI-LABEL: rotr_v4i32_c: 3552; CHECK-GI: // %bb.0: // %entry 3553; CHECK-GI-NEXT: ushr v1.4s, v0.4s, #3 3554; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 3555; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3556; CHECK-GI-NEXT: ret 3557entry: 3558 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) 3559 ret <4 x i32> %d 3560} 3561 3562define <7 x i32> @rotl_v7i32_c(<7 x i32> %a) { 3563; CHECK-SD-LABEL: rotl_v7i32_c: 3564; CHECK-SD: // %bb.0: // %entry 3565; CHECK-SD-NEXT: fmov s0, w0 3566; CHECK-SD-NEXT: fmov s1, w4 3567; CHECK-SD-NEXT: adrp x8, .LCPI108_0 3568; CHECK-SD-NEXT: adrp x9, .LCPI108_1 3569; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI108_0] 3570; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI108_1] 3571; CHECK-SD-NEXT: mov v0.s[1], w1 3572; CHECK-SD-NEXT: mov v1.s[1], w5 3573; CHECK-SD-NEXT: mov v0.s[2], w2 3574; CHECK-SD-NEXT: mov v1.s[2], w6 3575; CHECK-SD-NEXT: mov v0.s[3], w3 3576; CHECK-SD-NEXT: ushl v2.4s, v1.4s, v2.4s 3577; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s 3578; CHECK-SD-NEXT: shl v4.4s, v0.4s, #3 3579; CHECK-SD-NEXT: usra v4.4s, v0.4s, #29 3580; CHECK-SD-NEXT: orr v0.16b, v1.16b, v2.16b 3581; CHECK-SD-NEXT: mov w1, v4.s[1] 3582; CHECK-SD-NEXT: mov w2, v4.s[2] 3583; CHECK-SD-NEXT: mov w3, v4.s[3] 3584; CHECK-SD-NEXT: mov w5, v0.s[1] 3585; CHECK-SD-NEXT: mov w6, v0.s[2] 3586; CHECK-SD-NEXT: fmov w0, s4 3587; CHECK-SD-NEXT: fmov w4, s0 3588; CHECK-SD-NEXT: ret 3589; 3590; CHECK-GI-LABEL: rotl_v7i32_c: 3591; CHECK-GI: // %bb.0: // %entry 3592; CHECK-GI-NEXT: mov v0.s[0], w0 3593; CHECK-GI-NEXT: mov v1.s[0], w0 3594; CHECK-GI-NEXT: mov w8, #29 // =0x1d 3595; CHECK-GI-NEXT: mov v2.s[0], w8 3596; CHECK-GI-NEXT: mov w9, #3 // =0x3 3597; CHECK-GI-NEXT: mov v3.s[0], w4 3598; CHECK-GI-NEXT: mov v4.s[0], w9 3599; CHECK-GI-NEXT: mov v5.s[0], w4 3600; CHECK-GI-NEXT: mov v0.s[1], w1 3601; CHECK-GI-NEXT: mov v1.s[1], w1 3602; CHECK-GI-NEXT: mov v2.s[1], w8 3603; CHECK-GI-NEXT: mov v3.s[1], w5 3604; CHECK-GI-NEXT: mov v4.s[1], w9 3605; CHECK-GI-NEXT: mov v5.s[1], w5 3606; CHECK-GI-NEXT: mov v0.s[2], w2 3607; CHECK-GI-NEXT: mov v1.s[2], w2 3608; CHECK-GI-NEXT: mov v2.s[2], w8 3609; CHECK-GI-NEXT: mov v3.s[2], w6 3610; CHECK-GI-NEXT: mov v4.s[2], w9 3611; CHECK-GI-NEXT: mov v5.s[2], w6 3612; CHECK-GI-NEXT: mov v0.s[3], w3 3613; CHECK-GI-NEXT: mov v1.s[3], w3 3614; CHECK-GI-NEXT: neg v2.4s, v2.4s 3615; CHECK-GI-NEXT: ushl v3.4s, v3.4s, v4.4s 3616; CHECK-GI-NEXT: shl v0.4s, v0.4s, #3 3617; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #29 3618; CHECK-GI-NEXT: ushl v2.4s, v5.4s, v2.4s 3619; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 3620; CHECK-GI-NEXT: orr v1.16b, v3.16b, v2.16b 3621; CHECK-GI-NEXT: mov s2, v0.s[1] 3622; CHECK-GI-NEXT: mov s3, v0.s[2] 3623; CHECK-GI-NEXT: mov s4, v0.s[3] 3624; CHECK-GI-NEXT: mov s5, v1.s[1] 3625; CHECK-GI-NEXT: mov s6, v1.s[2] 3626; CHECK-GI-NEXT: fmov w0, s0 3627; CHECK-GI-NEXT: fmov w4, s1 3628; CHECK-GI-NEXT: fmov w1, s2 3629; CHECK-GI-NEXT: fmov w2, s3 3630; CHECK-GI-NEXT: fmov w3, s4 3631; CHECK-GI-NEXT: fmov w5, s5 3632; CHECK-GI-NEXT: fmov w6, s6 3633; CHECK-GI-NEXT: ret 3634entry: 3635 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %a, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 3636 ret <7 x i32> %d 3637} 3638 3639define <7 x i32> @rotr_v7i32_c(<7 x i32> %a) { 3640; CHECK-SD-LABEL: rotr_v7i32_c: 3641; CHECK-SD: // %bb.0: // %entry 3642; CHECK-SD-NEXT: fmov s0, w0 3643; CHECK-SD-NEXT: fmov s1, w4 3644; CHECK-SD-NEXT: adrp x8, .LCPI109_0 3645; CHECK-SD-NEXT: adrp x9, .LCPI109_1 3646; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI109_0] 3647; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI109_1] 3648; CHECK-SD-NEXT: mov v0.s[1], w1 3649; CHECK-SD-NEXT: mov v1.s[1], w5 3650; CHECK-SD-NEXT: mov v0.s[2], w2 3651; CHECK-SD-NEXT: mov v1.s[2], w6 3652; CHECK-SD-NEXT: mov v0.s[3], w3 3653; CHECK-SD-NEXT: ushl v2.4s, v1.4s, v2.4s 3654; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s 3655; CHECK-SD-NEXT: shl v4.4s, v0.4s, #29 3656; CHECK-SD-NEXT: usra v4.4s, v0.4s, #3 3657; CHECK-SD-NEXT: orr v0.16b, v1.16b, v2.16b 3658; CHECK-SD-NEXT: mov w1, v4.s[1] 3659; CHECK-SD-NEXT: mov w2, v4.s[2] 3660; CHECK-SD-NEXT: mov w3, v4.s[3] 3661; CHECK-SD-NEXT: mov w5, v0.s[1] 3662; CHECK-SD-NEXT: mov w6, v0.s[2] 3663; CHECK-SD-NEXT: fmov w0, s4 3664; CHECK-SD-NEXT: fmov w4, s0 3665; CHECK-SD-NEXT: ret 3666; 3667; CHECK-GI-LABEL: rotr_v7i32_c: 3668; CHECK-GI: // %bb.0: // %entry 3669; CHECK-GI-NEXT: mov v0.s[0], w0 3670; CHECK-GI-NEXT: mov v1.s[0], w0 3671; CHECK-GI-NEXT: mov w8, #3 // =0x3 3672; CHECK-GI-NEXT: mov v2.s[0], w8 3673; CHECK-GI-NEXT: mov w9, #29 // =0x1d 3674; CHECK-GI-NEXT: mov v3.s[0], w4 3675; CHECK-GI-NEXT: mov v4.s[0], w4 3676; CHECK-GI-NEXT: mov v5.s[0], w9 3677; CHECK-GI-NEXT: mov v0.s[1], w1 3678; CHECK-GI-NEXT: mov v1.s[1], w1 3679; CHECK-GI-NEXT: mov v2.s[1], w8 3680; CHECK-GI-NEXT: mov v3.s[1], w5 3681; CHECK-GI-NEXT: mov v4.s[1], w5 3682; CHECK-GI-NEXT: mov v5.s[1], w9 3683; CHECK-GI-NEXT: mov v0.s[2], w2 3684; CHECK-GI-NEXT: mov v1.s[2], w2 3685; CHECK-GI-NEXT: mov v2.s[2], w8 3686; CHECK-GI-NEXT: mov v3.s[2], w6 3687; CHECK-GI-NEXT: mov v4.s[2], w6 3688; CHECK-GI-NEXT: mov v5.s[2], w9 3689; CHECK-GI-NEXT: mov v0.s[3], w3 3690; CHECK-GI-NEXT: mov v1.s[3], w3 3691; CHECK-GI-NEXT: neg v2.4s, v2.4s 3692; CHECK-GI-NEXT: ushl v4.4s, v4.4s, v5.4s 3693; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #3 3694; CHECK-GI-NEXT: shl v1.4s, v1.4s, #29 3695; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s 3696; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 3697; CHECK-GI-NEXT: orr v1.16b, v2.16b, v4.16b 3698; CHECK-GI-NEXT: mov s2, v0.s[1] 3699; CHECK-GI-NEXT: mov s3, v0.s[2] 3700; CHECK-GI-NEXT: mov s4, v0.s[3] 3701; CHECK-GI-NEXT: mov s5, v1.s[1] 3702; CHECK-GI-NEXT: mov s6, v1.s[2] 3703; CHECK-GI-NEXT: fmov w0, s0 3704; CHECK-GI-NEXT: fmov w4, s1 3705; CHECK-GI-NEXT: fmov w1, s2 3706; CHECK-GI-NEXT: fmov w2, s3 3707; CHECK-GI-NEXT: fmov w3, s4 3708; CHECK-GI-NEXT: fmov w5, s5 3709; CHECK-GI-NEXT: fmov w6, s6 3710; CHECK-GI-NEXT: ret 3711entry: 3712 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %a, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 3713 ret <7 x i32> %d 3714} 3715 3716define <8 x i32> @rotl_v8i32_c(<8 x i32> %a) { 3717; CHECK-SD-LABEL: rotl_v8i32_c: 3718; CHECK-SD: // %bb.0: // %entry 3719; CHECK-SD-NEXT: shl v2.4s, v0.4s, #3 3720; CHECK-SD-NEXT: shl v3.4s, v1.4s, #3 3721; CHECK-SD-NEXT: usra v2.4s, v0.4s, #29 3722; CHECK-SD-NEXT: usra v3.4s, v1.4s, #29 3723; CHECK-SD-NEXT: mov v0.16b, v2.16b 3724; CHECK-SD-NEXT: mov v1.16b, v3.16b 3725; CHECK-SD-NEXT: ret 3726; 3727; CHECK-GI-LABEL: rotl_v8i32_c: 3728; CHECK-GI: // %bb.0: // %entry 3729; CHECK-GI-NEXT: shl v2.4s, v0.4s, #3 3730; CHECK-GI-NEXT: shl v3.4s, v1.4s, #3 3731; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #29 3732; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #29 3733; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3734; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 3735; CHECK-GI-NEXT: ret 3736entry: 3737 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %a, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 3738 ret <8 x i32> %d 3739} 3740 3741define <8 x i32> @rotr_v8i32_c(<8 x i32> %a) { 3742; CHECK-SD-LABEL: rotr_v8i32_c: 3743; CHECK-SD: // %bb.0: // %entry 3744; CHECK-SD-NEXT: shl v2.4s, v0.4s, #29 3745; CHECK-SD-NEXT: shl v3.4s, v1.4s, #29 3746; CHECK-SD-NEXT: usra v2.4s, v0.4s, #3 3747; CHECK-SD-NEXT: usra v3.4s, v1.4s, #3 3748; CHECK-SD-NEXT: mov v0.16b, v2.16b 3749; CHECK-SD-NEXT: mov v1.16b, v3.16b 3750; CHECK-SD-NEXT: ret 3751; 3752; CHECK-GI-LABEL: rotr_v8i32_c: 3753; CHECK-GI: // %bb.0: // %entry 3754; CHECK-GI-NEXT: ushr v2.4s, v0.4s, #3 3755; CHECK-GI-NEXT: ushr v3.4s, v1.4s, #3 3756; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 3757; CHECK-GI-NEXT: shl v1.4s, v1.4s, #29 3758; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3759; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 3760; CHECK-GI-NEXT: ret 3761entry: 3762 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %a, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 3763 ret <8 x i32> %d 3764} 3765 3766define <2 x i64> @rotl_v2i64_c(<2 x i64> %a) { 3767; CHECK-SD-LABEL: rotl_v2i64_c: 3768; CHECK-SD: // %bb.0: // %entry 3769; CHECK-SD-NEXT: shl v1.2d, v0.2d, #3 3770; CHECK-SD-NEXT: usra v1.2d, v0.2d, #61 3771; CHECK-SD-NEXT: mov v0.16b, v1.16b 3772; CHECK-SD-NEXT: ret 3773; 3774; CHECK-GI-LABEL: rotl_v2i64_c: 3775; CHECK-GI: // %bb.0: // %entry 3776; CHECK-GI-NEXT: shl v1.2d, v0.2d, #3 3777; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #61 3778; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3779; CHECK-GI-NEXT: ret 3780entry: 3781 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 3, i64 3>) 3782 ret <2 x i64> %d 3783} 3784 3785define <2 x i64> @rotr_v2i64_c(<2 x i64> %a) { 3786; CHECK-SD-LABEL: rotr_v2i64_c: 3787; CHECK-SD: // %bb.0: // %entry 3788; CHECK-SD-NEXT: shl v1.2d, v0.2d, #61 3789; CHECK-SD-NEXT: usra v1.2d, v0.2d, #3 3790; CHECK-SD-NEXT: mov v0.16b, v1.16b 3791; CHECK-SD-NEXT: ret 3792; 3793; CHECK-GI-LABEL: rotr_v2i64_c: 3794; CHECK-GI: // %bb.0: // %entry 3795; CHECK-GI-NEXT: ushr v1.2d, v0.2d, #3 3796; CHECK-GI-NEXT: shl v0.2d, v0.2d, #61 3797; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b 3798; CHECK-GI-NEXT: ret 3799entry: 3800 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 3, i64 3>) 3801 ret <2 x i64> %d 3802} 3803 3804define <4 x i64> @rotl_v4i64_c(<4 x i64> %a) { 3805; CHECK-SD-LABEL: rotl_v4i64_c: 3806; CHECK-SD: // %bb.0: // %entry 3807; CHECK-SD-NEXT: shl v2.2d, v0.2d, #3 3808; CHECK-SD-NEXT: shl v3.2d, v1.2d, #3 3809; CHECK-SD-NEXT: usra v2.2d, v0.2d, #61 3810; CHECK-SD-NEXT: usra v3.2d, v1.2d, #61 3811; CHECK-SD-NEXT: mov v0.16b, v2.16b 3812; CHECK-SD-NEXT: mov v1.16b, v3.16b 3813; CHECK-SD-NEXT: ret 3814; 3815; CHECK-GI-LABEL: rotl_v4i64_c: 3816; CHECK-GI: // %bb.0: // %entry 3817; CHECK-GI-NEXT: shl v2.2d, v0.2d, #3 3818; CHECK-GI-NEXT: shl v3.2d, v1.2d, #3 3819; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #61 3820; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #61 3821; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3822; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 3823; CHECK-GI-NEXT: ret 3824entry: 3825 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %a, <4 x i64> <i64 3, i64 3, i64 3, i64 3>) 3826 ret <4 x i64> %d 3827} 3828 3829define <4 x i64> @rotr_v4i64_c(<4 x i64> %a) { 3830; CHECK-SD-LABEL: rotr_v4i64_c: 3831; CHECK-SD: // %bb.0: // %entry 3832; CHECK-SD-NEXT: shl v2.2d, v0.2d, #61 3833; CHECK-SD-NEXT: shl v3.2d, v1.2d, #61 3834; CHECK-SD-NEXT: usra v2.2d, v0.2d, #3 3835; CHECK-SD-NEXT: usra v3.2d, v1.2d, #3 3836; CHECK-SD-NEXT: mov v0.16b, v2.16b 3837; CHECK-SD-NEXT: mov v1.16b, v3.16b 3838; CHECK-SD-NEXT: ret 3839; 3840; CHECK-GI-LABEL: rotr_v4i64_c: 3841; CHECK-GI: // %bb.0: // %entry 3842; CHECK-GI-NEXT: ushr v2.2d, v0.2d, #3 3843; CHECK-GI-NEXT: ushr v3.2d, v1.2d, #3 3844; CHECK-GI-NEXT: shl v0.2d, v0.2d, #61 3845; CHECK-GI-NEXT: shl v1.2d, v1.2d, #61 3846; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b 3847; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b 3848; CHECK-GI-NEXT: ret 3849entry: 3850 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %a, <4 x i64> <i64 3, i64 3, i64 3, i64 3>) 3851 ret <4 x i64> %d 3852} 3853 3854define <2 x i128> @rotl_v2i128_c(<2 x i128> %a) { 3855; CHECK-SD-LABEL: rotl_v2i128_c: 3856; CHECK-SD: // %bb.0: // %entry 3857; CHECK-SD-NEXT: extr x8, x2, x3, #61 3858; CHECK-SD-NEXT: extr x9, x0, x1, #61 3859; CHECK-SD-NEXT: extr x1, x1, x0, #61 3860; CHECK-SD-NEXT: extr x3, x3, x2, #61 3861; CHECK-SD-NEXT: mov x0, x9 3862; CHECK-SD-NEXT: mov x2, x8 3863; CHECK-SD-NEXT: ret 3864; 3865; CHECK-GI-LABEL: rotl_v2i128_c: 3866; CHECK-GI: // %bb.0: // %entry 3867; CHECK-GI-NEXT: lsr x8, x1, #61 3868; CHECK-GI-NEXT: lsl x9, x1, #3 3869; CHECK-GI-NEXT: lsl x10, x3, #3 3870; CHECK-GI-NEXT: lsr x11, x3, #61 3871; CHECK-GI-NEXT: orr x8, x8, x0, lsl #3 3872; CHECK-GI-NEXT: orr x1, x9, x0, lsr #61 3873; CHECK-GI-NEXT: orr x3, x10, x2, lsr #61 3874; CHECK-GI-NEXT: orr x2, x11, x2, lsl #3 3875; CHECK-GI-NEXT: mov x0, x8 3876; CHECK-GI-NEXT: ret 3877entry: 3878 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %a, <2 x i128> <i128 3, i128 3>) 3879 ret <2 x i128> %d 3880} 3881 3882define <2 x i128> @rotr_v2i128_c(<2 x i128> %a) { 3883; CHECK-SD-LABEL: rotr_v2i128_c: 3884; CHECK-SD: // %bb.0: // %entry 3885; CHECK-SD-NEXT: extr x8, x3, x2, #3 3886; CHECK-SD-NEXT: extr x9, x1, x0, #3 3887; CHECK-SD-NEXT: extr x1, x0, x1, #3 3888; CHECK-SD-NEXT: extr x3, x2, x3, #3 3889; CHECK-SD-NEXT: mov x0, x9 3890; CHECK-SD-NEXT: mov x2, x8 3891; CHECK-SD-NEXT: ret 3892; 3893; CHECK-GI-LABEL: rotr_v2i128_c: 3894; CHECK-GI: // %bb.0: // %entry 3895; CHECK-GI-NEXT: lsl x8, x1, #61 3896; CHECK-GI-NEXT: lsl x9, x3, #61 3897; CHECK-GI-NEXT: lsl x10, x0, #61 3898; CHECK-GI-NEXT: lsl x11, x2, #61 3899; CHECK-GI-NEXT: orr x0, x8, x0, lsr #3 3900; CHECK-GI-NEXT: orr x2, x9, x2, lsr #3 3901; CHECK-GI-NEXT: orr x1, x10, x1, lsr #3 3902; CHECK-GI-NEXT: orr x3, x11, x3, lsr #3 3903; CHECK-GI-NEXT: ret 3904entry: 3905 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %a, <2 x i128> <i128 3, i128 3>) 3906 ret <2 x i128> %d 3907} 3908 3909define <8 x i8> @fshl_v8i8_c(<8 x i8> %a, <8 x i8> %b) { 3910; CHECK-SD-LABEL: fshl_v8i8_c: 3911; CHECK-SD: // %bb.0: // %entry 3912; CHECK-SD-NEXT: ushr v1.8b, v1.8b, #1 3913; CHECK-SD-NEXT: shl v0.8b, v0.8b, #3 3914; CHECK-SD-NEXT: usra v0.8b, v1.8b, #4 3915; CHECK-SD-NEXT: ret 3916; 3917; CHECK-GI-LABEL: fshl_v8i8_c: 3918; CHECK-GI: // %bb.0: // %entry 3919; CHECK-GI-NEXT: shl v0.8b, v0.8b, #3 3920; CHECK-GI-NEXT: ushr v1.8b, v1.8b, #5 3921; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 3922; CHECK-GI-NEXT: ret 3923entry: 3924 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %b, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3925 ret <8 x i8> %d 3926} 3927 3928define <8 x i8> @fshr_v8i8_c(<8 x i8> %a, <8 x i8> %b) { 3929; CHECK-SD-LABEL: fshr_v8i8_c: 3930; CHECK-SD: // %bb.0: // %entry 3931; CHECK-SD-NEXT: add v0.8b, v0.8b, v0.8b 3932; CHECK-SD-NEXT: shl v0.8b, v0.8b, #4 3933; CHECK-SD-NEXT: usra v0.8b, v1.8b, #3 3934; CHECK-SD-NEXT: ret 3935; 3936; CHECK-GI-LABEL: fshr_v8i8_c: 3937; CHECK-GI: // %bb.0: // %entry 3938; CHECK-GI-NEXT: shl v0.8b, v0.8b, #5 3939; CHECK-GI-NEXT: ushr v1.8b, v1.8b, #3 3940; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 3941; CHECK-GI-NEXT: ret 3942entry: 3943 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %b, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3944 ret <8 x i8> %d 3945} 3946 3947define <16 x i8> @fshl_v16i8_c(<16 x i8> %a, <16 x i8> %b) { 3948; CHECK-SD-LABEL: fshl_v16i8_c: 3949; CHECK-SD: // %bb.0: // %entry 3950; CHECK-SD-NEXT: ushr v1.16b, v1.16b, #1 3951; CHECK-SD-NEXT: shl v0.16b, v0.16b, #3 3952; CHECK-SD-NEXT: usra v0.16b, v1.16b, #4 3953; CHECK-SD-NEXT: ret 3954; 3955; CHECK-GI-LABEL: fshl_v16i8_c: 3956; CHECK-GI: // %bb.0: // %entry 3957; CHECK-GI-NEXT: shl v0.16b, v0.16b, #3 3958; CHECK-GI-NEXT: ushr v1.16b, v1.16b, #5 3959; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 3960; CHECK-GI-NEXT: ret 3961entry: 3962 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3963 ret <16 x i8> %d 3964} 3965 3966define <16 x i8> @fshr_v16i8_c(<16 x i8> %a, <16 x i8> %b) { 3967; CHECK-SD-LABEL: fshr_v16i8_c: 3968; CHECK-SD: // %bb.0: // %entry 3969; CHECK-SD-NEXT: add v0.16b, v0.16b, v0.16b 3970; CHECK-SD-NEXT: shl v0.16b, v0.16b, #4 3971; CHECK-SD-NEXT: usra v0.16b, v1.16b, #3 3972; CHECK-SD-NEXT: ret 3973; 3974; CHECK-GI-LABEL: fshr_v16i8_c: 3975; CHECK-GI: // %bb.0: // %entry 3976; CHECK-GI-NEXT: shl v0.16b, v0.16b, #5 3977; CHECK-GI-NEXT: ushr v1.16b, v1.16b, #3 3978; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 3979; CHECK-GI-NEXT: ret 3980entry: 3981 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>) 3982 ret <16 x i8> %d 3983} 3984 3985define <4 x i16> @fshl_v4i16_c(<4 x i16> %a, <4 x i16> %b) { 3986; CHECK-SD-LABEL: fshl_v4i16_c: 3987; CHECK-SD: // %bb.0: // %entry 3988; CHECK-SD-NEXT: ushr v1.4h, v1.4h, #1 3989; CHECK-SD-NEXT: shl v0.4h, v0.4h, #3 3990; CHECK-SD-NEXT: usra v0.4h, v1.4h, #12 3991; CHECK-SD-NEXT: ret 3992; 3993; CHECK-GI-LABEL: fshl_v4i16_c: 3994; CHECK-GI: // %bb.0: // %entry 3995; CHECK-GI-NEXT: shl v0.4h, v0.4h, #3 3996; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #13 3997; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 3998; CHECK-GI-NEXT: ret 3999entry: 4000 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %b, <4 x i16> <i16 3, i16 3, i16 3, i16 3>) 4001 ret <4 x i16> %d 4002} 4003 4004define <4 x i16> @fshr_v4i16_c(<4 x i16> %a, <4 x i16> %b) { 4005; CHECK-SD-LABEL: fshr_v4i16_c: 4006; CHECK-SD: // %bb.0: // %entry 4007; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h 4008; CHECK-SD-NEXT: shl v0.4h, v0.4h, #12 4009; CHECK-SD-NEXT: usra v0.4h, v1.4h, #3 4010; CHECK-SD-NEXT: ret 4011; 4012; CHECK-GI-LABEL: fshr_v4i16_c: 4013; CHECK-GI: // %bb.0: // %entry 4014; CHECK-GI-NEXT: shl v0.4h, v0.4h, #13 4015; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #3 4016; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 4017; CHECK-GI-NEXT: ret 4018entry: 4019 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %b, <4 x i16> <i16 3, i16 3, i16 3, i16 3>) 4020 ret <4 x i16> %d 4021} 4022 4023define <7 x i16> @fshl_v7i16_c(<7 x i16> %a, <7 x i16> %b) { 4024; CHECK-SD-LABEL: fshl_v7i16_c: 4025; CHECK-SD: // %bb.0: // %entry 4026; CHECK-SD-NEXT: adrp x8, .LCPI124_0 4027; CHECK-SD-NEXT: ushr v1.8h, v1.8h, #1 4028; CHECK-SD-NEXT: adrp x9, .LCPI124_1 4029; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI124_0] 4030; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI124_1] 4031; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v2.8h 4032; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v3.8h 4033; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 4034; CHECK-SD-NEXT: ret 4035; 4036; CHECK-GI-LABEL: fshl_v7i16_c: 4037; CHECK-GI: // %bb.0: // %entry 4038; CHECK-GI-NEXT: mov w8, #13 // =0xd 4039; CHECK-GI-NEXT: mov w9, #3 // =0x3 4040; CHECK-GI-NEXT: fmov s2, w8 4041; CHECK-GI-NEXT: fmov s3, w9 4042; CHECK-GI-NEXT: mov v2.h[1], w8 4043; CHECK-GI-NEXT: mov v3.h[1], w9 4044; CHECK-GI-NEXT: mov v2.h[2], w8 4045; CHECK-GI-NEXT: mov v3.h[2], w9 4046; CHECK-GI-NEXT: mov v2.h[3], w8 4047; CHECK-GI-NEXT: mov v3.h[3], w9 4048; CHECK-GI-NEXT: mov v2.h[4], w8 4049; CHECK-GI-NEXT: mov v3.h[4], w9 4050; CHECK-GI-NEXT: mov v2.h[5], w8 4051; CHECK-GI-NEXT: mov v3.h[5], w9 4052; CHECK-GI-NEXT: mov v2.h[6], w8 4053; CHECK-GI-NEXT: mov v3.h[6], w9 4054; CHECK-GI-NEXT: neg v2.8h, v2.8h 4055; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v3.8h 4056; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v2.8h 4057; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4058; CHECK-GI-NEXT: ret 4059entry: 4060 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %b, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 4061 ret <7 x i16> %d 4062} 4063 4064define <7 x i16> @fshr_v7i16_c(<7 x i16> %a, <7 x i16> %b) { 4065; CHECK-SD-LABEL: fshr_v7i16_c: 4066; CHECK-SD: // %bb.0: // %entry 4067; CHECK-SD-NEXT: adrp x8, .LCPI125_0 4068; CHECK-SD-NEXT: adrp x9, .LCPI125_1 4069; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h 4070; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI125_0] 4071; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI125_1] 4072; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v2.8h 4073; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v3.8h 4074; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b 4075; CHECK-SD-NEXT: ret 4076; 4077; CHECK-GI-LABEL: fshr_v7i16_c: 4078; CHECK-GI: // %bb.0: // %entry 4079; CHECK-GI-NEXT: mov w8, #3 // =0x3 4080; CHECK-GI-NEXT: mov w9, #13 // =0xd 4081; CHECK-GI-NEXT: fmov s2, w8 4082; CHECK-GI-NEXT: fmov s3, w9 4083; CHECK-GI-NEXT: mov v2.h[1], w8 4084; CHECK-GI-NEXT: mov v3.h[1], w9 4085; CHECK-GI-NEXT: mov v2.h[2], w8 4086; CHECK-GI-NEXT: mov v3.h[2], w9 4087; CHECK-GI-NEXT: mov v2.h[3], w8 4088; CHECK-GI-NEXT: mov v3.h[3], w9 4089; CHECK-GI-NEXT: mov v2.h[4], w8 4090; CHECK-GI-NEXT: mov v3.h[4], w9 4091; CHECK-GI-NEXT: mov v2.h[5], w8 4092; CHECK-GI-NEXT: mov v3.h[5], w9 4093; CHECK-GI-NEXT: mov v2.h[6], w8 4094; CHECK-GI-NEXT: mov v3.h[6], w9 4095; CHECK-GI-NEXT: neg v2.8h, v2.8h 4096; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v3.8h 4097; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v2.8h 4098; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4099; CHECK-GI-NEXT: ret 4100entry: 4101 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %b, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 4102 ret <7 x i16> %d 4103} 4104 4105define <8 x i16> @fshl_v8i16_c(<8 x i16> %a, <8 x i16> %b) { 4106; CHECK-SD-LABEL: fshl_v8i16_c: 4107; CHECK-SD: // %bb.0: // %entry 4108; CHECK-SD-NEXT: ushr v1.8h, v1.8h, #1 4109; CHECK-SD-NEXT: shl v0.8h, v0.8h, #3 4110; CHECK-SD-NEXT: usra v0.8h, v1.8h, #12 4111; CHECK-SD-NEXT: ret 4112; 4113; CHECK-GI-LABEL: fshl_v8i16_c: 4114; CHECK-GI: // %bb.0: // %entry 4115; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3 4116; CHECK-GI-NEXT: ushr v1.8h, v1.8h, #13 4117; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4118; CHECK-GI-NEXT: ret 4119entry: 4120 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 4121 ret <8 x i16> %d 4122} 4123 4124define <8 x i16> @fshr_v8i16_c(<8 x i16> %a, <8 x i16> %b) { 4125; CHECK-SD-LABEL: fshr_v8i16_c: 4126; CHECK-SD: // %bb.0: // %entry 4127; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h 4128; CHECK-SD-NEXT: shl v0.8h, v0.8h, #12 4129; CHECK-SD-NEXT: usra v0.8h, v1.8h, #3 4130; CHECK-SD-NEXT: ret 4131; 4132; CHECK-GI-LABEL: fshr_v8i16_c: 4133; CHECK-GI: // %bb.0: // %entry 4134; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13 4135; CHECK-GI-NEXT: ushr v1.8h, v1.8h, #3 4136; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4137; CHECK-GI-NEXT: ret 4138entry: 4139 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 4140 ret <8 x i16> %d 4141} 4142 4143define <16 x i16> @fshl_v16i16_c(<16 x i16> %a, <16 x i16> %b) { 4144; CHECK-SD-LABEL: fshl_v16i16_c: 4145; CHECK-SD: // %bb.0: // %entry 4146; CHECK-SD-NEXT: ushr v2.8h, v2.8h, #1 4147; CHECK-SD-NEXT: shl v0.8h, v0.8h, #3 4148; CHECK-SD-NEXT: ushr v3.8h, v3.8h, #1 4149; CHECK-SD-NEXT: shl v1.8h, v1.8h, #3 4150; CHECK-SD-NEXT: usra v0.8h, v2.8h, #12 4151; CHECK-SD-NEXT: usra v1.8h, v3.8h, #12 4152; CHECK-SD-NEXT: ret 4153; 4154; CHECK-GI-LABEL: fshl_v16i16_c: 4155; CHECK-GI: // %bb.0: // %entry 4156; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3 4157; CHECK-GI-NEXT: shl v1.8h, v1.8h, #3 4158; CHECK-GI-NEXT: ushr v2.8h, v2.8h, #13 4159; CHECK-GI-NEXT: ushr v3.8h, v3.8h, #13 4160; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 4161; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 4162; CHECK-GI-NEXT: ret 4163entry: 4164 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %b, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 4165 ret <16 x i16> %d 4166} 4167 4168define <16 x i16> @fshr_v16i16_c(<16 x i16> %a, <16 x i16> %b) { 4169; CHECK-SD-LABEL: fshr_v16i16_c: 4170; CHECK-SD: // %bb.0: // %entry 4171; CHECK-SD-NEXT: add v1.8h, v1.8h, v1.8h 4172; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h 4173; CHECK-SD-NEXT: shl v1.8h, v1.8h, #12 4174; CHECK-SD-NEXT: shl v0.8h, v0.8h, #12 4175; CHECK-SD-NEXT: usra v1.8h, v3.8h, #3 4176; CHECK-SD-NEXT: usra v0.8h, v2.8h, #3 4177; CHECK-SD-NEXT: ret 4178; 4179; CHECK-GI-LABEL: fshr_v16i16_c: 4180; CHECK-GI: // %bb.0: // %entry 4181; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13 4182; CHECK-GI-NEXT: shl v1.8h, v1.8h, #13 4183; CHECK-GI-NEXT: ushr v2.8h, v2.8h, #3 4184; CHECK-GI-NEXT: ushr v3.8h, v3.8h, #3 4185; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 4186; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 4187; CHECK-GI-NEXT: ret 4188entry: 4189 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %b, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>) 4190 ret <16 x i16> %d 4191} 4192 4193define <2 x i32> @fshl_v2i32_c(<2 x i32> %a, <2 x i32> %b) { 4194; CHECK-SD-LABEL: fshl_v2i32_c: 4195; CHECK-SD: // %bb.0: // %entry 4196; CHECK-SD-NEXT: shl v0.2s, v0.2s, #3 4197; CHECK-SD-NEXT: usra v0.2s, v1.2s, #29 4198; CHECK-SD-NEXT: ret 4199; 4200; CHECK-GI-LABEL: fshl_v2i32_c: 4201; CHECK-GI: // %bb.0: // %entry 4202; CHECK-GI-NEXT: shl v0.2s, v0.2s, #3 4203; CHECK-GI-NEXT: ushr v1.2s, v1.2s, #29 4204; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 4205; CHECK-GI-NEXT: ret 4206entry: 4207 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 3, i32 3>) 4208 ret <2 x i32> %d 4209} 4210 4211define <2 x i32> @fshr_v2i32_c(<2 x i32> %a, <2 x i32> %b) { 4212; CHECK-SD-LABEL: fshr_v2i32_c: 4213; CHECK-SD: // %bb.0: // %entry 4214; CHECK-SD-NEXT: shl v0.2s, v0.2s, #29 4215; CHECK-SD-NEXT: usra v0.2s, v1.2s, #3 4216; CHECK-SD-NEXT: ret 4217; 4218; CHECK-GI-LABEL: fshr_v2i32_c: 4219; CHECK-GI: // %bb.0: // %entry 4220; CHECK-GI-NEXT: shl v0.2s, v0.2s, #29 4221; CHECK-GI-NEXT: ushr v1.2s, v1.2s, #3 4222; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 4223; CHECK-GI-NEXT: ret 4224entry: 4225 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 3, i32 3>) 4226 ret <2 x i32> %d 4227} 4228 4229define <4 x i32> @fshl_v4i32_c(<4 x i32> %a, <4 x i32> %b) { 4230; CHECK-SD-LABEL: fshl_v4i32_c: 4231; CHECK-SD: // %bb.0: // %entry 4232; CHECK-SD-NEXT: shl v0.4s, v0.4s, #3 4233; CHECK-SD-NEXT: usra v0.4s, v1.4s, #29 4234; CHECK-SD-NEXT: ret 4235; 4236; CHECK-GI-LABEL: fshl_v4i32_c: 4237; CHECK-GI: // %bb.0: // %entry 4238; CHECK-GI-NEXT: shl v0.4s, v0.4s, #3 4239; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #29 4240; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4241; CHECK-GI-NEXT: ret 4242entry: 4243 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) 4244 ret <4 x i32> %d 4245} 4246 4247define <4 x i32> @fshr_v4i32_c(<4 x i32> %a, <4 x i32> %b) { 4248; CHECK-SD-LABEL: fshr_v4i32_c: 4249; CHECK-SD: // %bb.0: // %entry 4250; CHECK-SD-NEXT: shl v0.4s, v0.4s, #29 4251; CHECK-SD-NEXT: usra v0.4s, v1.4s, #3 4252; CHECK-SD-NEXT: ret 4253; 4254; CHECK-GI-LABEL: fshr_v4i32_c: 4255; CHECK-GI: // %bb.0: // %entry 4256; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 4257; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #3 4258; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4259; CHECK-GI-NEXT: ret 4260entry: 4261 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) 4262 ret <4 x i32> %d 4263} 4264 4265define <7 x i32> @fshl_v7i32_c(<7 x i32> %a, <7 x i32> %b) { 4266; CHECK-SD-LABEL: fshl_v7i32_c: 4267; CHECK-SD: // %bb.0: // %entry 4268; CHECK-SD-NEXT: fmov s0, w0 4269; CHECK-SD-NEXT: fmov s2, w4 4270; CHECK-SD-NEXT: ldr s1, [sp, #24] 4271; CHECK-SD-NEXT: fmov s3, w7 4272; CHECK-SD-NEXT: mov x8, sp 4273; CHECK-SD-NEXT: add x9, sp, #32 4274; CHECK-SD-NEXT: ld1 { v1.s }[1], [x9] 4275; CHECK-SD-NEXT: add x9, sp, #40 4276; CHECK-SD-NEXT: adrp x10, .LCPI134_1 4277; CHECK-SD-NEXT: mov v0.s[1], w1 4278; CHECK-SD-NEXT: mov v2.s[1], w5 4279; CHECK-SD-NEXT: ldr q5, [x10, :lo12:.LCPI134_1] 4280; CHECK-SD-NEXT: ld1 { v3.s }[1], [x8] 4281; CHECK-SD-NEXT: add x8, sp, #8 4282; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9] 4283; CHECK-SD-NEXT: add x9, sp, #16 4284; CHECK-SD-NEXT: mov v0.s[2], w2 4285; CHECK-SD-NEXT: mov v2.s[2], w6 4286; CHECK-SD-NEXT: ld1 { v3.s }[2], [x8] 4287; CHECK-SD-NEXT: adrp x8, .LCPI134_0 4288; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI134_0] 4289; CHECK-SD-NEXT: ld1 { v3.s }[3], [x9] 4290; CHECK-SD-NEXT: mov v0.s[3], w3 4291; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v4.4s 4292; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v5.4s 4293; CHECK-SD-NEXT: orr v1.16b, v2.16b, v1.16b 4294; CHECK-SD-NEXT: shl v0.4s, v0.4s, #3 4295; CHECK-SD-NEXT: mov w5, v1.s[1] 4296; CHECK-SD-NEXT: mov w6, v1.s[2] 4297; CHECK-SD-NEXT: fmov w4, s1 4298; CHECK-SD-NEXT: usra v0.4s, v3.4s, #29 4299; CHECK-SD-NEXT: mov w1, v0.s[1] 4300; CHECK-SD-NEXT: mov w2, v0.s[2] 4301; CHECK-SD-NEXT: mov w3, v0.s[3] 4302; CHECK-SD-NEXT: fmov w0, s0 4303; CHECK-SD-NEXT: ret 4304; 4305; CHECK-GI-LABEL: fshl_v7i32_c: 4306; CHECK-GI: // %bb.0: // %entry 4307; CHECK-GI-NEXT: mov v0.s[0], w0 4308; CHECK-GI-NEXT: mov v1.s[0], w7 4309; CHECK-GI-NEXT: mov w8, #29 // =0x1d 4310; CHECK-GI-NEXT: mov v3.s[0], w8 4311; CHECK-GI-NEXT: ldr s2, [sp] 4312; CHECK-GI-NEXT: mov w9, #3 // =0x3 4313; CHECK-GI-NEXT: mov v4.s[0], w9 4314; CHECK-GI-NEXT: ldr s5, [sp, #8] 4315; CHECK-GI-NEXT: ldr s6, [sp, #24] 4316; CHECK-GI-NEXT: ldr s7, [sp, #32] 4317; CHECK-GI-NEXT: mov v0.s[1], w1 4318; CHECK-GI-NEXT: mov v1.s[1], v2.s[0] 4319; CHECK-GI-NEXT: mov v2.s[0], w4 4320; CHECK-GI-NEXT: mov v3.s[1], w8 4321; CHECK-GI-NEXT: mov v6.s[1], v7.s[0] 4322; CHECK-GI-NEXT: ldr s7, [sp, #40] 4323; CHECK-GI-NEXT: mov v4.s[1], w9 4324; CHECK-GI-NEXT: mov v0.s[2], w2 4325; CHECK-GI-NEXT: mov v1.s[2], v5.s[0] 4326; CHECK-GI-NEXT: mov v2.s[1], w5 4327; CHECK-GI-NEXT: mov v3.s[2], w8 4328; CHECK-GI-NEXT: ldr s5, [sp, #16] 4329; CHECK-GI-NEXT: mov v6.s[2], v7.s[0] 4330; CHECK-GI-NEXT: mov v4.s[2], w9 4331; CHECK-GI-NEXT: mov v0.s[3], w3 4332; CHECK-GI-NEXT: mov v1.s[3], v5.s[0] 4333; CHECK-GI-NEXT: mov v2.s[2], w6 4334; CHECK-GI-NEXT: neg v3.4s, v3.4s 4335; CHECK-GI-NEXT: shl v0.4s, v0.4s, #3 4336; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #29 4337; CHECK-GI-NEXT: ushl v2.4s, v2.4s, v4.4s 4338; CHECK-GI-NEXT: ushl v3.4s, v6.4s, v3.4s 4339; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4340; CHECK-GI-NEXT: orr v1.16b, v2.16b, v3.16b 4341; CHECK-GI-NEXT: mov s2, v0.s[1] 4342; CHECK-GI-NEXT: mov s3, v0.s[2] 4343; CHECK-GI-NEXT: mov s4, v0.s[3] 4344; CHECK-GI-NEXT: mov s5, v1.s[1] 4345; CHECK-GI-NEXT: mov s6, v1.s[2] 4346; CHECK-GI-NEXT: fmov w0, s0 4347; CHECK-GI-NEXT: fmov w4, s1 4348; CHECK-GI-NEXT: fmov w1, s2 4349; CHECK-GI-NEXT: fmov w2, s3 4350; CHECK-GI-NEXT: fmov w3, s4 4351; CHECK-GI-NEXT: fmov w5, s5 4352; CHECK-GI-NEXT: fmov w6, s6 4353; CHECK-GI-NEXT: ret 4354entry: 4355 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %b, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 4356 ret <7 x i32> %d 4357} 4358 4359define <7 x i32> @fshr_v7i32_c(<7 x i32> %a, <7 x i32> %b) { 4360; CHECK-SD-LABEL: fshr_v7i32_c: 4361; CHECK-SD: // %bb.0: // %entry 4362; CHECK-SD-NEXT: fmov s0, w0 4363; CHECK-SD-NEXT: fmov s2, w4 4364; CHECK-SD-NEXT: ldr s1, [sp, #24] 4365; CHECK-SD-NEXT: fmov s3, w7 4366; CHECK-SD-NEXT: mov x8, sp 4367; CHECK-SD-NEXT: add x9, sp, #32 4368; CHECK-SD-NEXT: ld1 { v1.s }[1], [x9] 4369; CHECK-SD-NEXT: add x9, sp, #40 4370; CHECK-SD-NEXT: adrp x10, .LCPI135_1 4371; CHECK-SD-NEXT: mov v0.s[1], w1 4372; CHECK-SD-NEXT: mov v2.s[1], w5 4373; CHECK-SD-NEXT: ldr q5, [x10, :lo12:.LCPI135_1] 4374; CHECK-SD-NEXT: ld1 { v3.s }[1], [x8] 4375; CHECK-SD-NEXT: add x8, sp, #8 4376; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9] 4377; CHECK-SD-NEXT: add x9, sp, #16 4378; CHECK-SD-NEXT: mov v0.s[2], w2 4379; CHECK-SD-NEXT: mov v2.s[2], w6 4380; CHECK-SD-NEXT: ld1 { v3.s }[2], [x8] 4381; CHECK-SD-NEXT: adrp x8, .LCPI135_0 4382; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI135_0] 4383; CHECK-SD-NEXT: ld1 { v3.s }[3], [x9] 4384; CHECK-SD-NEXT: mov v0.s[3], w3 4385; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v4.4s 4386; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v5.4s 4387; CHECK-SD-NEXT: orr v1.16b, v2.16b, v1.16b 4388; CHECK-SD-NEXT: shl v0.4s, v0.4s, #29 4389; CHECK-SD-NEXT: mov w5, v1.s[1] 4390; CHECK-SD-NEXT: mov w6, v1.s[2] 4391; CHECK-SD-NEXT: fmov w4, s1 4392; CHECK-SD-NEXT: usra v0.4s, v3.4s, #3 4393; CHECK-SD-NEXT: mov w1, v0.s[1] 4394; CHECK-SD-NEXT: mov w2, v0.s[2] 4395; CHECK-SD-NEXT: mov w3, v0.s[3] 4396; CHECK-SD-NEXT: fmov w0, s0 4397; CHECK-SD-NEXT: ret 4398; 4399; CHECK-GI-LABEL: fshr_v7i32_c: 4400; CHECK-GI: // %bb.0: // %entry 4401; CHECK-GI-NEXT: mov v0.s[0], w0 4402; CHECK-GI-NEXT: mov v1.s[0], w7 4403; CHECK-GI-NEXT: mov w8, #3 // =0x3 4404; CHECK-GI-NEXT: mov v3.s[0], w8 4405; CHECK-GI-NEXT: ldr s2, [sp] 4406; CHECK-GI-NEXT: mov w9, #29 // =0x1d 4407; CHECK-GI-NEXT: mov v4.s[0], w9 4408; CHECK-GI-NEXT: ldr s5, [sp, #8] 4409; CHECK-GI-NEXT: ldr s6, [sp, #24] 4410; CHECK-GI-NEXT: ldr s7, [sp, #32] 4411; CHECK-GI-NEXT: mov v0.s[1], w1 4412; CHECK-GI-NEXT: mov v1.s[1], v2.s[0] 4413; CHECK-GI-NEXT: mov v2.s[0], w4 4414; CHECK-GI-NEXT: mov v3.s[1], w8 4415; CHECK-GI-NEXT: mov v6.s[1], v7.s[0] 4416; CHECK-GI-NEXT: ldr s7, [sp, #40] 4417; CHECK-GI-NEXT: mov v4.s[1], w9 4418; CHECK-GI-NEXT: mov v0.s[2], w2 4419; CHECK-GI-NEXT: mov v1.s[2], v5.s[0] 4420; CHECK-GI-NEXT: mov v2.s[1], w5 4421; CHECK-GI-NEXT: mov v3.s[2], w8 4422; CHECK-GI-NEXT: ldr s5, [sp, #16] 4423; CHECK-GI-NEXT: mov v6.s[2], v7.s[0] 4424; CHECK-GI-NEXT: mov v4.s[2], w9 4425; CHECK-GI-NEXT: mov v0.s[3], w3 4426; CHECK-GI-NEXT: mov v1.s[3], v5.s[0] 4427; CHECK-GI-NEXT: mov v2.s[2], w6 4428; CHECK-GI-NEXT: neg v3.4s, v3.4s 4429; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 4430; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #3 4431; CHECK-GI-NEXT: ushl v2.4s, v2.4s, v4.4s 4432; CHECK-GI-NEXT: ushl v3.4s, v6.4s, v3.4s 4433; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4434; CHECK-GI-NEXT: orr v1.16b, v2.16b, v3.16b 4435; CHECK-GI-NEXT: mov s2, v0.s[1] 4436; CHECK-GI-NEXT: mov s3, v0.s[2] 4437; CHECK-GI-NEXT: mov s4, v0.s[3] 4438; CHECK-GI-NEXT: mov s5, v1.s[1] 4439; CHECK-GI-NEXT: mov s6, v1.s[2] 4440; CHECK-GI-NEXT: fmov w0, s0 4441; CHECK-GI-NEXT: fmov w4, s1 4442; CHECK-GI-NEXT: fmov w1, s2 4443; CHECK-GI-NEXT: fmov w2, s3 4444; CHECK-GI-NEXT: fmov w3, s4 4445; CHECK-GI-NEXT: fmov w5, s5 4446; CHECK-GI-NEXT: fmov w6, s6 4447; CHECK-GI-NEXT: ret 4448entry: 4449 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %b, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 4450 ret <7 x i32> %d 4451} 4452 4453define <8 x i32> @fshl_v8i32_c(<8 x i32> %a, <8 x i32> %b) { 4454; CHECK-SD-LABEL: fshl_v8i32_c: 4455; CHECK-SD: // %bb.0: // %entry 4456; CHECK-SD-NEXT: shl v1.4s, v1.4s, #3 4457; CHECK-SD-NEXT: shl v0.4s, v0.4s, #3 4458; CHECK-SD-NEXT: usra v1.4s, v3.4s, #29 4459; CHECK-SD-NEXT: usra v0.4s, v2.4s, #29 4460; CHECK-SD-NEXT: ret 4461; 4462; CHECK-GI-LABEL: fshl_v8i32_c: 4463; CHECK-GI: // %bb.0: // %entry 4464; CHECK-GI-NEXT: shl v0.4s, v0.4s, #3 4465; CHECK-GI-NEXT: shl v1.4s, v1.4s, #3 4466; CHECK-GI-NEXT: ushr v2.4s, v2.4s, #29 4467; CHECK-GI-NEXT: ushr v3.4s, v3.4s, #29 4468; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 4469; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 4470; CHECK-GI-NEXT: ret 4471entry: 4472 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 4473 ret <8 x i32> %d 4474} 4475 4476define <8 x i32> @fshr_v8i32_c(<8 x i32> %a, <8 x i32> %b) { 4477; CHECK-SD-LABEL: fshr_v8i32_c: 4478; CHECK-SD: // %bb.0: // %entry 4479; CHECK-SD-NEXT: shl v1.4s, v1.4s, #29 4480; CHECK-SD-NEXT: shl v0.4s, v0.4s, #29 4481; CHECK-SD-NEXT: usra v1.4s, v3.4s, #3 4482; CHECK-SD-NEXT: usra v0.4s, v2.4s, #3 4483; CHECK-SD-NEXT: ret 4484; 4485; CHECK-GI-LABEL: fshr_v8i32_c: 4486; CHECK-GI: // %bb.0: // %entry 4487; CHECK-GI-NEXT: shl v0.4s, v0.4s, #29 4488; CHECK-GI-NEXT: shl v1.4s, v1.4s, #29 4489; CHECK-GI-NEXT: ushr v2.4s, v2.4s, #3 4490; CHECK-GI-NEXT: ushr v3.4s, v3.4s, #3 4491; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 4492; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 4493; CHECK-GI-NEXT: ret 4494entry: 4495 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>) 4496 ret <8 x i32> %d 4497} 4498 4499define <2 x i64> @fshl_v2i64_c(<2 x i64> %a, <2 x i64> %b) { 4500; CHECK-SD-LABEL: fshl_v2i64_c: 4501; CHECK-SD: // %bb.0: // %entry 4502; CHECK-SD-NEXT: shl v0.2d, v0.2d, #3 4503; CHECK-SD-NEXT: usra v0.2d, v1.2d, #61 4504; CHECK-SD-NEXT: ret 4505; 4506; CHECK-GI-LABEL: fshl_v2i64_c: 4507; CHECK-GI: // %bb.0: // %entry 4508; CHECK-GI-NEXT: shl v0.2d, v0.2d, #3 4509; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #61 4510; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4511; CHECK-GI-NEXT: ret 4512entry: 4513 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 3, i64 3>) 4514 ret <2 x i64> %d 4515} 4516 4517define <2 x i64> @fshr_v2i64_c(<2 x i64> %a, <2 x i64> %b) { 4518; CHECK-SD-LABEL: fshr_v2i64_c: 4519; CHECK-SD: // %bb.0: // %entry 4520; CHECK-SD-NEXT: shl v0.2d, v0.2d, #61 4521; CHECK-SD-NEXT: usra v0.2d, v1.2d, #3 4522; CHECK-SD-NEXT: ret 4523; 4524; CHECK-GI-LABEL: fshr_v2i64_c: 4525; CHECK-GI: // %bb.0: // %entry 4526; CHECK-GI-NEXT: shl v0.2d, v0.2d, #61 4527; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #3 4528; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4529; CHECK-GI-NEXT: ret 4530entry: 4531 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 3, i64 3>) 4532 ret <2 x i64> %d 4533} 4534 4535define <4 x i64> @fshl_v4i64_c(<4 x i64> %a, <4 x i64> %b) { 4536; CHECK-SD-LABEL: fshl_v4i64_c: 4537; CHECK-SD: // %bb.0: // %entry 4538; CHECK-SD-NEXT: shl v1.2d, v1.2d, #3 4539; CHECK-SD-NEXT: shl v0.2d, v0.2d, #3 4540; CHECK-SD-NEXT: usra v1.2d, v3.2d, #61 4541; CHECK-SD-NEXT: usra v0.2d, v2.2d, #61 4542; CHECK-SD-NEXT: ret 4543; 4544; CHECK-GI-LABEL: fshl_v4i64_c: 4545; CHECK-GI: // %bb.0: // %entry 4546; CHECK-GI-NEXT: shl v0.2d, v0.2d, #3 4547; CHECK-GI-NEXT: shl v1.2d, v1.2d, #3 4548; CHECK-GI-NEXT: ushr v2.2d, v2.2d, #61 4549; CHECK-GI-NEXT: ushr v3.2d, v3.2d, #61 4550; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 4551; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 4552; CHECK-GI-NEXT: ret 4553entry: 4554 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %b, <4 x i64> <i64 3, i64 3, i64 3, i64 3>) 4555 ret <4 x i64> %d 4556} 4557 4558define <4 x i64> @fshr_v4i64_c(<4 x i64> %a, <4 x i64> %b) { 4559; CHECK-SD-LABEL: fshr_v4i64_c: 4560; CHECK-SD: // %bb.0: // %entry 4561; CHECK-SD-NEXT: shl v1.2d, v1.2d, #61 4562; CHECK-SD-NEXT: shl v0.2d, v0.2d, #61 4563; CHECK-SD-NEXT: usra v1.2d, v3.2d, #3 4564; CHECK-SD-NEXT: usra v0.2d, v2.2d, #3 4565; CHECK-SD-NEXT: ret 4566; 4567; CHECK-GI-LABEL: fshr_v4i64_c: 4568; CHECK-GI: // %bb.0: // %entry 4569; CHECK-GI-NEXT: shl v0.2d, v0.2d, #61 4570; CHECK-GI-NEXT: shl v1.2d, v1.2d, #61 4571; CHECK-GI-NEXT: ushr v2.2d, v2.2d, #3 4572; CHECK-GI-NEXT: ushr v3.2d, v3.2d, #3 4573; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 4574; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 4575; CHECK-GI-NEXT: ret 4576entry: 4577 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %b, <4 x i64> <i64 3, i64 3, i64 3, i64 3>) 4578 ret <4 x i64> %d 4579} 4580 4581define <2 x i128> @fshl_v2i128_c(<2 x i128> %a, <2 x i128> %b) { 4582; CHECK-SD-LABEL: fshl_v2i128_c: 4583; CHECK-SD: // %bb.0: // %entry 4584; CHECK-SD-NEXT: extr x8, x0, x5, #61 4585; CHECK-SD-NEXT: extr x9, x2, x7, #61 4586; CHECK-SD-NEXT: extr x1, x1, x0, #61 4587; CHECK-SD-NEXT: extr x3, x3, x2, #61 4588; CHECK-SD-NEXT: mov x0, x8 4589; CHECK-SD-NEXT: mov x2, x9 4590; CHECK-SD-NEXT: ret 4591; 4592; CHECK-GI-LABEL: fshl_v2i128_c: 4593; CHECK-GI: // %bb.0: // %entry 4594; CHECK-GI-NEXT: lsr x8, x5, #61 4595; CHECK-GI-NEXT: lsl x9, x1, #3 4596; CHECK-GI-NEXT: lsl x10, x3, #3 4597; CHECK-GI-NEXT: lsr x11, x7, #61 4598; CHECK-GI-NEXT: orr x8, x8, x0, lsl #3 4599; CHECK-GI-NEXT: orr x1, x9, x0, lsr #61 4600; CHECK-GI-NEXT: orr x3, x10, x2, lsr #61 4601; CHECK-GI-NEXT: orr x2, x11, x2, lsl #3 4602; CHECK-GI-NEXT: mov x0, x8 4603; CHECK-GI-NEXT: ret 4604entry: 4605 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>) 4606 ret <2 x i128> %d 4607} 4608 4609define <2 x i128> @fshr_v2i128_c(<2 x i128> %a, <2 x i128> %b) { 4610; CHECK-SD-LABEL: fshr_v2i128_c: 4611; CHECK-SD: // %bb.0: // %entry 4612; CHECK-SD-NEXT: extr x8, x5, x4, #3 4613; CHECK-SD-NEXT: extr x9, x7, x6, #3 4614; CHECK-SD-NEXT: extr x1, x0, x5, #3 4615; CHECK-SD-NEXT: extr x3, x2, x7, #3 4616; CHECK-SD-NEXT: mov x0, x8 4617; CHECK-SD-NEXT: mov x2, x9 4618; CHECK-SD-NEXT: ret 4619; 4620; CHECK-GI-LABEL: fshr_v2i128_c: 4621; CHECK-GI: // %bb.0: // %entry 4622; CHECK-GI-NEXT: lsl x8, x5, #61 4623; CHECK-GI-NEXT: lsl x9, x7, #61 4624; CHECK-GI-NEXT: lsr x10, x5, #3 4625; CHECK-GI-NEXT: lsr x11, x7, #3 4626; CHECK-GI-NEXT: orr x8, x8, x4, lsr #3 4627; CHECK-GI-NEXT: orr x9, x9, x6, lsr #3 4628; CHECK-GI-NEXT: orr x1, x10, x0, lsl #61 4629; CHECK-GI-NEXT: orr x3, x11, x2, lsl #61 4630; CHECK-GI-NEXT: mov x0, x8 4631; CHECK-GI-NEXT: mov x2, x9 4632; CHECK-GI-NEXT: ret 4633entry: 4634 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>) 4635 ret <2 x i128> %d 4636} 4637