1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s --mtriple=aarch64 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc < %s --mtriple=aarch64 -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5declare i8 @llvm.ctlz.i8(i8, i1) 6declare i16 @llvm.ctlz.i16(i16, i1) 7declare i32 @llvm.ctlz.i32(i32, i1) 8declare i64 @llvm.ctlz.i64(i64, i1) 9 10define i8 @ctlo_i8(i8 %x) { 11; CHECK-SD-LABEL: ctlo_i8: 12; CHECK-SD: // %bb.0: 13; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff 14; CHECK-SD-NEXT: eor w8, w8, w0, lsl #24 15; CHECK-SD-NEXT: clz w0, w8 16; CHECK-SD-NEXT: ret 17; 18; CHECK-GI-LABEL: ctlo_i8: 19; CHECK-GI: // %bb.0: 20; CHECK-GI-NEXT: mov w8, #255 // =0xff 21; CHECK-GI-NEXT: bic w8, w8, w0 22; CHECK-GI-NEXT: clz w8, w8 23; CHECK-GI-NEXT: sub w0, w8, #24 24; CHECK-GI-NEXT: ret 25 %tmp1 = xor i8 %x, -1 26 %tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 false ) 27 ret i8 %tmp2 28} 29 30define i8 @ctlo_i8_undef(i8 %x) { 31; CHECK-SD-LABEL: ctlo_i8_undef: 32; CHECK-SD: // %bb.0: 33; CHECK-SD-NEXT: mvn w8, w0 34; CHECK-SD-NEXT: lsl w8, w8, #24 35; CHECK-SD-NEXT: clz w0, w8 36; CHECK-SD-NEXT: ret 37; 38; CHECK-GI-LABEL: ctlo_i8_undef: 39; CHECK-GI: // %bb.0: 40; CHECK-GI-NEXT: mov w8, #255 // =0xff 41; CHECK-GI-NEXT: bic w8, w8, w0 42; CHECK-GI-NEXT: clz w8, w8 43; CHECK-GI-NEXT: sub w0, w8, #24 44; CHECK-GI-NEXT: ret 45 %tmp1 = xor i8 %x, -1 46 %tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 true ) 47 ret i8 %tmp2 48} 49 50define i16 @ctlo_i16(i16 %x) { 51; CHECK-SD-LABEL: ctlo_i16: 52; CHECK-SD: // %bb.0: 53; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff 54; CHECK-SD-NEXT: eor w8, w8, w0, lsl #16 55; CHECK-SD-NEXT: clz w0, w8 56; CHECK-SD-NEXT: ret 57; 58; CHECK-GI-LABEL: ctlo_i16: 59; CHECK-GI: // %bb.0: 60; CHECK-GI-NEXT: mov w8, #65535 // =0xffff 61; CHECK-GI-NEXT: bic w8, w8, w0 62; CHECK-GI-NEXT: clz w8, w8 63; CHECK-GI-NEXT: sub w0, w8, #16 64; CHECK-GI-NEXT: ret 65 %tmp1 = xor i16 %x, -1 66 %tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 false ) 67 ret i16 %tmp2 68} 69 70define i16 @ctlo_i16_undef(i16 %x) { 71; CHECK-SD-LABEL: ctlo_i16_undef: 72; CHECK-SD: // %bb.0: 73; CHECK-SD-NEXT: mvn w8, w0 74; CHECK-SD-NEXT: lsl w8, w8, #16 75; CHECK-SD-NEXT: clz w0, w8 76; CHECK-SD-NEXT: ret 77; 78; CHECK-GI-LABEL: ctlo_i16_undef: 79; CHECK-GI: // %bb.0: 80; CHECK-GI-NEXT: mov w8, #65535 // =0xffff 81; CHECK-GI-NEXT: bic w8, w8, w0 82; CHECK-GI-NEXT: clz w8, w8 83; CHECK-GI-NEXT: sub w0, w8, #16 84; CHECK-GI-NEXT: ret 85 %tmp1 = xor i16 %x, -1 86 %tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true ) 87 ret i16 %tmp2 88} 89 90define i32 @ctlo_i32(i32 %x) { 91; CHECK-LABEL: ctlo_i32: 92; CHECK: // %bb.0: 93; CHECK-NEXT: mvn w8, w0 94; CHECK-NEXT: clz w0, w8 95; CHECK-NEXT: ret 96 %tmp1 = xor i32 %x, -1 97 %tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 false ) 98 ret i32 %tmp2 99} 100 101define i32 @ctlo_i32_undef(i32 %x) { 102; CHECK-LABEL: ctlo_i32_undef: 103; CHECK: // %bb.0: 104; CHECK-NEXT: mvn w8, w0 105; CHECK-NEXT: clz w0, w8 106; CHECK-NEXT: ret 107 %tmp1 = xor i32 %x, -1 108 %tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 true ) 109 ret i32 %tmp2 110} 111 112define i64 @ctlo_i64(i64 %x) { 113; CHECK-LABEL: ctlo_i64: 114; CHECK: // %bb.0: 115; CHECK-NEXT: mvn x8, x0 116; CHECK-NEXT: clz x0, x8 117; CHECK-NEXT: ret 118 %tmp1 = xor i64 %x, -1 119 %tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 false ) 120 ret i64 %tmp2 121} 122 123define i64 @ctlo_i64_undef(i64 %x) { 124; CHECK-LABEL: ctlo_i64_undef: 125; CHECK: // %bb.0: 126; CHECK-NEXT: mvn x8, x0 127; CHECK-NEXT: clz x0, x8 128; CHECK-NEXT: ret 129 %tmp1 = xor i64 %x, -1 130 %tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 true ) 131 ret i64 %tmp2 132} 133