xref: /llvm-project/llvm/test/CodeGen/AArch64/block-placement-optimize-branches.ll (revision b8d6659bff25458693c99a7c53372afcf6d66d7d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
3
4; When consuming profile data we sometimes flip a branch to improve runtime
5; performance. If we are optimizing for size, we avoid changing the branch to
6; improve outlining and ICF.
7
8define i8 @foo_optsize(i32 %v4) optsize {
9; CHECK-LABEL: foo_optsize:
10; CHECK:       // %bb.0: // %entry
11; CHECK-NEXT:    cbz wzr, .LBB0_2
12; CHECK-NEXT:  .LBB0_1:
13; CHECK-NEXT:    mov w0, wzr
14; CHECK-NEXT:    ret
15; CHECK-NEXT:  .LBB0_2: // %b1
16; CHECK-NEXT:    cbnz w0, .LBB0_4
17; CHECK-NEXT:  .LBB0_3: // %b2
18; CHECK-NEXT:    mov w0, #1 // =0x1
19; CHECK-NEXT:    ret
20; CHECK-NEXT:  .LBB0_4: // %b1
21; CHECK-NEXT:    cmp w0, #1
22; CHECK-NEXT:    b.ne .LBB0_1
23; CHECK-NEXT:  // %bb.5: // %b3
24; CHECK-NEXT:    cbz wzr, .LBB0_1
25; CHECK-NEXT:    b .LBB0_3
26entry:
27  %v2 = icmp eq i32 0, 0
28  br i1 %v2, label %b1, label %b4
29
30b1:
31  switch i32 %v4, label %b4 [
32    i32 1, label %b3
33    i32 0, label %b2
34  ], !prof !0
35
36b2:
37  br label %b4
38
39b3:
40  %v3 = icmp eq i32 0, 0
41  br i1 %v3, label %b4, label %b2
42
43b4:
44  %v16 = phi i8 [ 1, %b2 ], [ 0, %entry ], [ 0, %b3 ], [ 0, %b1 ]
45  ret i8 %v16
46}
47
48define i8 @foo_optspeed(i32 %v4) {
49; CHECK-LABEL: foo_optspeed:
50; CHECK:       // %bb.0: // %entry
51; CHECK-NEXT:    cbz wzr, .LBB1_2
52; CHECK-NEXT:  .LBB1_1:
53; CHECK-NEXT:    mov w0, wzr
54; CHECK-NEXT:    ret
55; CHECK-NEXT:  .LBB1_2: // %b1
56; CHECK-NEXT:    cbnz w0, .LBB1_4
57; CHECK-NEXT:  .LBB1_3: // %b2
58; CHECK-NEXT:    mov w0, #1 // =0x1
59; CHECK-NEXT:    ret
60; CHECK-NEXT:  .LBB1_4: // %b1
61; CHECK-NEXT:    cmp w0, #1
62; CHECK-NEXT:    b.ne .LBB1_1
63; CHECK-NEXT:  // %bb.5: // %b3
64; CHECK-NEXT:    cbnz wzr, .LBB1_3
65; CHECK-NEXT:    b .LBB1_1
66entry:
67  %v2 = icmp eq i32 0, 0
68  br i1 %v2, label %b1, label %b4
69
70b1:
71  switch i32 %v4, label %b4 [
72    i32 1, label %b3
73    i32 0, label %b2
74  ], !prof !0
75
76b2:
77  br label %b4
78
79b3:
80  %v3 = icmp eq i32 0, 0
81  br i1 %v3, label %b4, label %b2
82
83b4:
84  %v16 = phi i8 [ 1, %b2 ], [ 0, %entry ], [ 0, %b3 ], [ 0, %b1 ]
85  ret i8 %v16
86}
87
88!0 = !{!"branch_weights", i32 5, i32 5, i32 100}
89