1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s 3 4define <8 x i8> @v_orrimm(ptr %A) nounwind { 5; CHECK-LABEL: v_orrimm: 6; CHECK: // %bb.0: 7; CHECK-NEXT: ldr d0, [x0] 8; CHECK-NEXT: orr.2s v0, #1, lsl #24 9; CHECK-NEXT: ret 10 %tmp1 = load <8 x i8>, ptr %A 11 %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> 12 ret <8 x i8> %tmp3 13} 14 15define <16 x i8> @v_orrimmQ(ptr %A) nounwind { 16; CHECK-LABEL: v_orrimmQ: 17; CHECK: // %bb.0: 18; CHECK-NEXT: ldr q0, [x0] 19; CHECK-NEXT: orr.4s v0, #1, lsl #24 20; CHECK-NEXT: ret 21 %tmp1 = load <16 x i8>, ptr %A 22 %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> 23 ret <16 x i8> %tmp3 24} 25 26define <8 x i8> @v_bicimm(ptr %A) nounwind { 27; CHECK-LABEL: v_bicimm: 28; CHECK: // %bb.0: 29; CHECK-NEXT: ldr d0, [x0] 30; CHECK-NEXT: bic.2s v0, #255, lsl #24 31; CHECK-NEXT: ret 32 %tmp1 = load <8 x i8>, ptr %A 33 %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > 34 ret <8 x i8> %tmp3 35} 36 37define <16 x i8> @v_bicimmQ(ptr %A) nounwind { 38; CHECK-LABEL: v_bicimmQ: 39; CHECK: // %bb.0: 40; CHECK-NEXT: ldr q0, [x0] 41; CHECK-NEXT: bic.4s v0, #255, lsl #24 42; CHECK-NEXT: ret 43 %tmp1 = load <16 x i8>, ptr %A 44 %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > 45 ret <16 x i8> %tmp3 46} 47 48define <2 x double> @foo(<2 x double> %bar) nounwind { 49; CHECK-LABEL: foo: 50; CHECK: // %bb.0: 51; CHECK-NEXT: fmov.2d v1, #1.00000000 52; CHECK-NEXT: fadd.2d v0, v0, v1 53; CHECK-NEXT: ret 54 %add = fadd <2 x double> %bar, <double 1.0, double 1.0> 55 ret <2 x double> %add 56} 57 58define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp { 59; CHECK-LABEL: movi_4s_imm_t1: 60; CHECK: // %bb.0: // %entry 61; CHECK-NEXT: movi.4s v0, #75 62; CHECK-NEXT: ret 63entry: 64 ret <4 x i32> <i32 75, i32 75, i32 75, i32 75> 65} 66 67define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp { 68; CHECK-LABEL: movi_4s_imm_t2: 69; CHECK: // %bb.0: // %entry 70; CHECK-NEXT: movi.4s v0, #75, lsl #8 71; CHECK-NEXT: ret 72entry: 73 ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200> 74} 75 76define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp { 77; CHECK-LABEL: movi_4s_imm_t3: 78; CHECK: // %bb.0: // %entry 79; CHECK-NEXT: movi.4s v0, #75, lsl #16 80; CHECK-NEXT: ret 81entry: 82 ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200> 83} 84 85define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp { 86; CHECK-LABEL: movi_4s_imm_t4: 87; CHECK: // %bb.0: // %entry 88; CHECK-NEXT: movi.4s v0, #75, lsl #24 89; CHECK-NEXT: ret 90entry: 91 ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> 92} 93 94define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp { 95; CHECK-LABEL: movi_8h_imm_t5: 96; CHECK: // %bb.0: // %entry 97; CHECK-NEXT: movi.8h v0, #75 98; CHECK-NEXT: ret 99entry: 100 ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75> 101} 102 103; rdar://11989841 104define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp { 105; CHECK-LABEL: movi_8h_imm_t6: 106; CHECK: // %bb.0: // %entry 107; CHECK-NEXT: movi.8h v0, #75, lsl #8 108; CHECK-NEXT: ret 109entry: 110 ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200> 111} 112 113define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp { 114; CHECK-LABEL: movi_4s_imm_t7: 115; CHECK: // %bb.0: // %entry 116; CHECK-NEXT: movi.4s v0, #75, msl #8 117; CHECK-NEXT: ret 118entry: 119 ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455> 120} 121 122define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp { 123; CHECK-LABEL: movi_4s_imm_t8: 124; CHECK: // %bb.0: // %entry 125; CHECK-NEXT: movi.4s v0, #75, msl #16 126; CHECK-NEXT: ret 127entry: 128 ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735> 129} 130 131define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp { 132; CHECK-LABEL: movi_16b_imm_t9: 133; CHECK: // %bb.0: // %entry 134; CHECK-NEXT: movi.16b v0, #75 135; CHECK-NEXT: ret 136entry: 137 ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75> 138} 139 140define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp { 141; CHECK-LABEL: movi_2d_imm_t10: 142; CHECK: // %bb.0: // %entry 143; CHECK-NEXT: movi.2d v0, #0xff00ff00ff00ff 144; CHECK-NEXT: ret 145entry: 146 ret <2 x i64> <i64 71777214294589695, i64 71777214294589695> 147} 148 149define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp { 150; CHECK-LABEL: movi_4s_imm_t11: 151; CHECK: // %bb.0: // %entry 152; CHECK-NEXT: fmov.4s v0, #-0.32812500 153; CHECK-NEXT: ret 154entry: 155 ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088> 156} 157 158define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp { 159; CHECK-LABEL: movi_2d_imm_t12: 160; CHECK: // %bb.0: // %entry 161; CHECK-NEXT: fmov.2d v0, #-0.17187500 162; CHECK-NEXT: ret 163entry: 164 ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664> 165} 166