1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3 4; Check that DAGCombiner is not asserting with mis-matched vector element count, "Vector element counts must match in SIGN_EXTEND_INREG". 5; Also no warning message of "warning: Possible incorrect use of EVT::getVectorNumElements() for scalable vector.". 6 7define <vscale x 4 x i32> @sext_inreg(<vscale x 4 x i32> %a) { 8; CHECK-LABEL: sext_inreg: 9; CHECK: // %bb.0: 10; CHECK-NEXT: ptrue p0.s 11; CHECK-NEXT: sxth z0.s, p0/m, z0.s 12; CHECK-NEXT: ret 13 %sext = shl <vscale x 4 x i32> %a, splat(i32 16) 14 %conv = ashr <vscale x 4 x i32> %sext, splat(i32 16) 15 ret <vscale x 4 x i32> %conv 16} 17 18define <vscale x 4 x i32> @ashr_shl(<vscale x 4 x i32> %a) { 19; CHECK-LABEL: ashr_shl: 20; CHECK: // %bb.0: 21; CHECK-NEXT: lsl z0.s, z0.s, #8 22; CHECK-NEXT: asr z0.s, z0.s, #16 23; CHECK-NEXT: ret 24 %shl = shl <vscale x 4 x i32> %a, splat(i32 8) 25 %r = ashr <vscale x 4 x i32> %shl, splat(i32 16) 26 ret <vscale x 4 x i32> %r 27} 28 29define <vscale x 4 x i32> @ashr_shl_illegal_trunc_vec_ty(<vscale x 4 x i32> %a) { 30; CHECK-LABEL: ashr_shl_illegal_trunc_vec_ty: 31; CHECK: // %bb.0: 32; CHECK-NEXT: lsl z0.s, z0.s, #8 33; CHECK-NEXT: asr z0.s, z0.s, #11 34; CHECK-NEXT: ret 35 %shl = shl <vscale x 4 x i32> %a, splat(i32 8) 36 %r = ashr <vscale x 4 x i32> %shl, splat(i32 11) 37 ret <vscale x 4 x i32> %r 38} 39 40define <vscale x 4 x i32> @ashr_add_shl_nxv4i8(<vscale x 4 x i32> %a) { 41; CHECK-LABEL: ashr_add_shl_nxv4i8: 42; CHECK: // %bb.0: 43; CHECK-NEXT: mov z1.s, #0x1000000 44; CHECK-NEXT: lsl z0.s, z0.s, #24 45; CHECK-NEXT: add z0.s, z0.s, z1.s 46; CHECK-NEXT: asr z0.s, z0.s, #24 47; CHECK-NEXT: ret 48 %conv = shl <vscale x 4 x i32> %a, splat(i32 24) 49 %sext = add <vscale x 4 x i32> %conv, splat(i32 16777216) 50 %conv1 = ashr <vscale x 4 x i32> %sext, splat(i32 24) 51 ret <vscale x 4 x i32> %conv1 52} 53