133d24fe3SLuke Lau; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 2 233d24fe3SLuke Lau; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v | FileCheck %s -check-prefixes=CHECK,RV32 333d24fe3SLuke Lau; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v | FileCheck %s -check-prefixes=CHECK,RV64 4475890cdSShih-Po Hung; RUN: opt < %s -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=riscv32 -mattr=+v | FileCheck %s -check-prefixes=CHECK-SIZE,RV32-SIZE 5475890cdSShih-Po Hung; RUN: opt < %s -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=riscv64 -mattr=+v | FileCheck %s -check-prefixes=CHECK-SIZE,RV64-SIZE 633d24fe3SLuke Lau 733d24fe3SLuke Laudefine <8 x i8> @select_start_v8i8(<8 x i8> %v, <8 x i8> %w) { 833d24fe3SLuke Lau; CHECK-LABEL: 'select_start_v8i8' 9f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 100a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 1133d24fe3SLuke Lau; 12475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'select_start_v8i8' 13475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 14475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 15475890cdSShih-Po Hung; 1633d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 1733d24fe3SLuke Lau ret <8 x i8> %res 1833d24fe3SLuke Lau} 1933d24fe3SLuke Lau 2033d24fe3SLuke Laudefine <8 x i8> @select_non_contiguous_v8i8(<8 x i8> %v, <8 x i8> %w) { 2133d24fe3SLuke Lau; CHECK-LABEL: 'select_non_contiguous_v8i8' 22f23ea4cbSLuke Lau; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 4, i32 13, i32 6, i32 15> 230a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %res 2433d24fe3SLuke Lau; 25475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'select_non_contiguous_v8i8' 26475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 4, i32 13, i32 6, i32 15> 27475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %res 28475890cdSShih-Po Hung; 2933d24fe3SLuke Lau %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 4, i32 13, i32 6, i32 15> 3033d24fe3SLuke Lau ret <8 x i8> %res 3133d24fe3SLuke Lau} 3233d24fe3SLuke Lau 3333d24fe3SLuke Laudefine <8 x i64> @select_start_v8i64(<8 x i64> %v, <8 x i64> %w) { 34f23ea4cbSLuke Lau; CHECK-LABEL: 'select_start_v8i64' 35*2663d2cbSPhilip Reames; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 360a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %res 3733d24fe3SLuke Lau; 38475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'select_start_v8i64' 39*2663d2cbSPhilip Reames; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 40475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i64> %res 41475890cdSShih-Po Hung; 4233d24fe3SLuke Lau %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 4333d24fe3SLuke Lau ret <8 x i64> %res 4433d24fe3SLuke Lau} 4533d24fe3SLuke Lau 4633d24fe3SLuke Laudefine <8 x i64> @select_non_contiguous_v8i64(<8 x i64> %v, <8 x i64> %w) { 47f23ea4cbSLuke Lau; CHECK-LABEL: 'select_non_contiguous_v8i64' 48*2663d2cbSPhilip Reames; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 4, i32 13, i32 6, i32 15> 490a5d52a7SSergey Kachkov; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %res 5033d24fe3SLuke Lau; 51475890cdSShih-Po Hung; CHECK-SIZE-LABEL: 'select_non_contiguous_v8i64' 52*2663d2cbSPhilip Reames; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 4, i32 13, i32 6, i32 15> 53475890cdSShih-Po Hung; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i64> %res 54475890cdSShih-Po Hung; 5533d24fe3SLuke Lau %res = shufflevector <8 x i64> %v, <8 x i64> %w, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 4, i32 13, i32 6, i32 15> 5633d24fe3SLuke Lau ret <8 x i64> %res 5733d24fe3SLuke Lau} 58f23ea4cbSLuke Lau;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 59f23ea4cbSLuke Lau; RV32: {{.*}} 60475890cdSShih-Po Hung; RV32-SIZE: {{.*}} 61f23ea4cbSLuke Lau; RV64: {{.*}} 62475890cdSShih-Po Hung; RV64-SIZE: {{.*}} 63