History log of /llvm-project/llvm/test/Analysis/CostModel/RISCV/shuffle-select.ll (Results 1 – 7 of 7)
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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init
# 2663d2cb 18-Jan-2024 Philip Reames <preames@rivosinc.com>

[RISCV] Adjust select shuffle cost to reflect mask creation cost (#77963)

This is inspired by
https://github.com/llvm/llvm-project/pull/77342#pullrequestreview-1814673242,
and is split off of same

[RISCV] Adjust select shuffle cost to reflect mask creation cost (#77963)

This is inspired by
https://github.com/llvm/llvm-project/pull/77342#pullrequestreview-1814673242,
and is split off of same with some differences in style.

A select is a vmerge.vv with the additional cost of materializing the
bitmask vector in a vreg. All masks fit within a single vector register
(e8 + m8 is the worst case), and thus our worst case cost should be
roughly 3 (2 scalar to produce the address, one vector load op). Given
most shuffles are small, and the mask will be instead produced by
LUI/ADDI + vmv.s.x or ADDI + vmv.s.x, using 2 as the default seems quite
reasonable. At worst, we're not going to be off by much.

The prior lowering scaled the cost of the bitmask with LMUL, which I
don't understand. At m1 it did use the same base cost of 2. (@lukel97
You wrote the original code here, anything I'm missing here?)

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# 475890cd 04-Jan-2024 Shih-Po Hung <shihpo.hung@sifive.com>

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.

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# 9c39d9bb 28-Dec-2023 Vitaly Buka <vitalybuka@google.com>

Revert "[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)" (#76536)

Fails on bots https://lab.llvm.org/buildbot/#/builders/5/builds/39629

Issue #76535

This reverts com

Revert "[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)" (#76536)

Fails on bots https://lab.llvm.org/buildbot/#/builders/5/builds/39629

Issue #76535

This reverts commit 3e75dece919511e4a2edada82d783304cc14a9cd.

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# 3e75dece 28-Dec-2023 Shih-Po Hung <shihpo.hung@sifive.com>

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)

…Kind

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of Cos

[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for Cost… (#73651)

…Kind

Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.

show more ...


Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2
# 0a5d52a7 25-Sep-2023 Sergey Kachkov <109674256+skachkov-sc@users.noreply.github.com>

[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)

This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and

[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)

This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.

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Revision tags: llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1
# f23ea4cb 23-Mar-2023 Luke Lau <luke@igalia.com>

[RISCV] Model select and insertsubvector shuffle kinds

Selects get lowered to a vmerge with a mask, and insertsubvectors get
lowered to a vslideup.

Differential Revision: https://reviews.llvm.org/D

[RISCV] Model select and insertsubvector shuffle kinds

Selects get lowered to a vmerge with a mask, and insertsubvectors get
lowered to a vslideup.

Differential Revision: https://reviews.llvm.org/D146747

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# 33d24fe3 24-Mar-2023 Luke Lau <luke@igalia.com>

[RISCV] Add test cases for modeling more shuffle kinds

These map to SK_InsertSubvector and SK_Select shuffle kinds