1 //===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "XCoreTargetMachine.h" 13 #include "TargetInfo/XCoreTargetInfo.h" 14 #include "XCore.h" 15 #include "XCoreMachineFunctionInfo.h" 16 #include "XCoreTargetObjectFile.h" 17 #include "XCoreTargetTransformInfo.h" 18 #include "llvm/Analysis/TargetTransformInfo.h" 19 #include "llvm/CodeGen/Passes.h" 20 #include "llvm/CodeGen/TargetPassConfig.h" 21 #include "llvm/MC/TargetRegistry.h" 22 #include "llvm/Support/CodeGen.h" 23 #include <optional> 24 25 using namespace llvm; 26 27 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { 28 return RM.value_or(Reloc::Static); 29 } 30 31 static CodeModel::Model 32 getEffectiveXCoreCodeModel(std::optional<CodeModel::Model> CM) { 33 if (CM) { 34 if (*CM != CodeModel::Small && *CM != CodeModel::Large) 35 report_fatal_error("Target only supports CodeModel Small or Large"); 36 return *CM; 37 } 38 return CodeModel::Small; 39 } 40 41 /// Create an ILP32 architecture model 42 /// 43 XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, 44 StringRef CPU, StringRef FS, 45 const TargetOptions &Options, 46 std::optional<Reloc::Model> RM, 47 std::optional<CodeModel::Model> CM, 48 CodeGenOptLevel OL, bool JIT) 49 : CodeGenTargetMachineImpl( 50 T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", 51 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 52 getEffectiveXCoreCodeModel(CM), OL), 53 TLOF(std::make_unique<XCoreTargetObjectFile>()), 54 Subtarget(TT, std::string(CPU), std::string(FS), *this) { 55 initAsmInfo(); 56 } 57 58 XCoreTargetMachine::~XCoreTargetMachine() = default; 59 60 namespace { 61 62 /// XCore Code Generator Pass Configuration Options. 63 class XCorePassConfig : public TargetPassConfig { 64 public: 65 XCorePassConfig(XCoreTargetMachine &TM, PassManagerBase &PM) 66 : TargetPassConfig(TM, PM) {} 67 68 XCoreTargetMachine &getXCoreTargetMachine() const { 69 return getTM<XCoreTargetMachine>(); 70 } 71 72 void addIRPasses() override; 73 bool addPreISel() override; 74 bool addInstSelector() override; 75 void addPreEmitPass() override; 76 }; 77 78 } // end anonymous namespace 79 80 TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) { 81 return new XCorePassConfig(*this, PM); 82 } 83 84 void XCorePassConfig::addIRPasses() { 85 addPass(createAtomicExpandLegacyPass()); 86 87 TargetPassConfig::addIRPasses(); 88 } 89 90 bool XCorePassConfig::addPreISel() { 91 addPass(createXCoreLowerThreadLocalPass()); 92 return false; 93 } 94 95 bool XCorePassConfig::addInstSelector() { 96 addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel())); 97 return false; 98 } 99 100 void XCorePassConfig::addPreEmitPass() { 101 addPass(createXCoreFrameToArgsOffsetEliminationPass()); 102 } 103 104 // Force static initialization. 105 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() { 106 RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget()); 107 PassRegistry &PR = *PassRegistry::getPassRegistry(); 108 initializeXCoreDAGToDAGISelLegacyPass(PR); 109 } 110 111 TargetTransformInfo 112 XCoreTargetMachine::getTargetTransformInfo(const Function &F) const { 113 return TargetTransformInfo(XCoreTTIImpl(this, F)); 114 } 115 116 MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo( 117 BumpPtrAllocator &Allocator, const Function &F, 118 const TargetSubtargetInfo *STI) const { 119 return XCoreFunctionInfo::create<XCoreFunctionInfo>(Allocator, F, STI); 120 } 121