1//=- X86SchedSapphireRapids.td - X86 SapphireRapids Scheduling *- tablegen -*=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for SapphireRapids to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SapphireRapidsModel : SchedMachineModel { 15 // SapphireRapids can allocate 6 uops per cycle. 16 let IssueWidth = 6; // Based on allocator width. 17 let MicroOpBufferSize = 512; // Based on the reorder buffer. 18 let LoadLatency = 5; 19 let MispredictPenalty = 14; 20 21 // Latency for microcoded instructions or instructions without latency info. 22 int MaxLatency = 100; 23 24 // Based on the LSD (loop-stream detector) queue size (ST). 25 let LoopMicroOpBufferSize = 72; 26 27 // This flag is set to allow the scheduler to assign a default model to 28 // unrecognized opcodes. 29 let CompleteModel = 0; 30} 31 32let SchedModel = SapphireRapidsModel in { 33 34// SapphireRapids can issue micro-ops to 12 different ports in one cycle. 35def SPRPort00 : ProcResource<1>; 36def SPRPort01 : ProcResource<1>; 37def SPRPort02 : ProcResource<1>; 38def SPRPort03 : ProcResource<1>; 39def SPRPort04 : ProcResource<1>; 40def SPRPort05 : ProcResource<1>; 41def SPRPort06 : ProcResource<1>; 42def SPRPort07 : ProcResource<1>; 43def SPRPort08 : ProcResource<1>; 44def SPRPort09 : ProcResource<1>; 45def SPRPort10 : ProcResource<1>; 46def SPRPort11 : ProcResource<1>; 47 48// Workaround to represent invalid ports. WriteRes shouldn't use this resource. 49def SPRPortInvalid :ProcResource<1>; 50 51// Many micro-ops are capable of issuing on multiple ports. 52def SPRPort00_01 : ProcResGroup<[SPRPort00, SPRPort01]>; 53def SPRPort00_01_05 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05]>; 54def SPRPort00_01_05_06 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05, SPRPort06]>; 55def SPRPort00_05 : ProcResGroup<[SPRPort00, SPRPort05]>; 56def SPRPort00_05_06 : ProcResGroup<[SPRPort00, SPRPort05, SPRPort06]>; 57def SPRPort00_06 : ProcResGroup<[SPRPort00, SPRPort06]>; 58def SPRPort01_05 : ProcResGroup<[SPRPort01, SPRPort05]>; 59def SPRPort01_05_11 : ProcResGroup<[SPRPort01, SPRPort05, SPRPort11]>; 60def SPRPort02_03 : ProcResGroup<[SPRPort02, SPRPort03]>; 61def SPRPort02_03_10 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort10]>; 62def SPRPort05_11 : ProcResGroup<[SPRPort05, SPRPort11]>; 63def SPRPort07_08 : ProcResGroup<[SPRPort07, SPRPort08]>; 64 65// EU has 112 reservation stations. 66def SPRPort00_01_05_06_11 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05, 67 SPRPort06, SPRPort11]> { 68 let BufferSize = 112; 69} 70 71// STD has 48 reservation stations. 72def SPRPort04_09 : ProcResGroup<[SPRPort04, SPRPort09]> { 73 let BufferSize = 48; 74} 75 76// MEM has 72 reservation stations. 77def SPRPort02_03_07_08_10 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort07, 78 SPRPort08, SPRPort10]> { 79 let BufferSize = 72; 80} 81 82def SPRPortAny : ProcResGroup<[SPRPort00, SPRPort01, SPRPort02, SPRPort03, 83 SPRPort04, SPRPort05, SPRPort06, SPRPort07, 84 SPRPort08, SPRPort09, SPRPort10, SPRPort11]>; 85 86// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available 87// until 5 cycles after the memory operand. 88def : ReadAdvance<ReadAfterLd, 5>; 89 90// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available 91// until 6 cycles after the memory operand. 92def : ReadAdvance<ReadAfterVecLd, 6>; 93def : ReadAdvance<ReadAfterVecXLd, 6>; 94def : ReadAdvance<ReadAfterVecYLd, 6>; 95 96def : ReadAdvance<ReadInt2Fpu, 0>; 97 98// Many SchedWrites are defined in pairs with and without a folded load. 99// Instructions with folded loads are usually micro-fused, so they only appear 100// as two micro-ops when queued in the reservation station. 101// This multiclass defines the resource usage for variants with and without 102// folded loads. 103multiclass SPRWriteResPair<X86FoldableSchedWrite SchedRW, 104 list<ProcResourceKind> ExePorts, 105 int Lat, list<int> Res = [1], int UOps = 1, 106 int LoadLat = 5, int LoadUOps = 1> { 107 // Register variant is using a single cycle on ExePort. 108 def : WriteRes<SchedRW, ExePorts> { 109 let Latency = Lat; 110 let ReleaseAtCycles = Res; 111 let NumMicroOps = UOps; 112 } 113 114 // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to 115 // the latency (default = 5). 116 def : WriteRes<SchedRW.Folded, !listconcat([SPRPort02_03_10], ExePorts)> { 117 let Latency = !add(Lat, LoadLat); 118 let ReleaseAtCycles = !listconcat([1], Res); 119 let NumMicroOps = !add(UOps, LoadUOps); 120 } 121} 122 123//===----------------------------------------------------------------------===// 124// The following definitons are infered by smg. 125//===----------------------------------------------------------------------===// 126 127// Infered SchedWrite definition. 128def : WriteRes<WriteADC, [SPRPort00_06]>; 129defm : X86WriteRes<WriteADCLd, [SPRPort00_01_05_06_11, SPRPort00_06], 11, [1, 1], 2>; 130defm : SPRWriteResPair<WriteAESDecEnc, [SPRPort00_01], 5, [1], 1, 7>; 131defm : SPRWriteResPair<WriteAESIMC, [SPRPort00_01], 8, [2], 2, 7>; 132defm : X86WriteRes<WriteAESKeyGen, [SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort05], 7, [4, 1, 1, 2, 3, 3], 14>; 133defm : X86WriteRes<WriteAESKeyGenLd, [SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort02_03_10, SPRPort05], 12, [4, 1, 2, 3, 1, 3], 14>; 134def : WriteRes<WriteALU, [SPRPort00_01_05_06_11]>; 135def : WriteRes<WriteALULd, [SPRPort00_01_05_06_11]> { 136 let Latency = 11; 137} 138defm : SPRWriteResPair<WriteBEXTR, [SPRPort00_06, SPRPort01], 6, [1, 1], 2>; 139defm : SPRWriteResPair<WriteBLS, [SPRPort01_05_11], 2, [1]>; 140defm : SPRWriteResPair<WriteBSF, [SPRPort01], 3, [1]>; 141defm : SPRWriteResPair<WriteBSR, [SPRPort01], 3, [1]>; 142def : WriteRes<WriteBSWAP32, [SPRPort01]>; 143defm : X86WriteRes<WriteBSWAP64, [SPRPort00_06, SPRPort01], 2, [1, 1], 2>; 144defm : SPRWriteResPair<WriteBZHI, [SPRPort01], 3, [1]>; 145def : WriteRes<WriteBitTest, [SPRPort01]>; 146defm : X86WriteRes<WriteBitTestImmLd, [SPRPort01, SPRPort02_03_10], 6, [1, 1], 2>; 147defm : X86WriteRes<WriteBitTestRegLd, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10], 11, [4, 2, 1, 2, 1], 10>; 148def : WriteRes<WriteBitTestSet, [SPRPort01]>; 149def : WriteRes<WriteBitTestSetImmLd, [SPRPort01]> { 150 let Latency = 11; 151} 152defm : X86WriteRes<WriteBitTestSetRegLd, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11], 17, [3, 2, 1, 2], 8>; 153defm : SPRWriteResPair<WriteBlend, [SPRPort01_05], 1, [1], 1, 7>; 154defm : SPRWriteResPair<WriteBlendY, [SPRPort00_01_05], 1, [1], 1, 8>; 155defm : SPRWriteResPair<WriteCLMul, [SPRPort05], 3, [1], 1, 7>; 156defm : SPRWriteResPair<WriteCMOV, [SPRPort00_06], 1, [1], 1, 6>; 157defm : X86WriteRes<WriteCMPXCHG, [SPRPort00_01_05_06_11, SPRPort00_06], 3, [3, 2], 5>; 158defm : X86WriteRes<WriteCMPXCHGRMW, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 12, [1, 2, 1, 1, 1], 6>; 159defm : SPRWriteResPair<WriteCRC32, [SPRPort01], 3, [1]>; 160defm : X86WriteRes<WriteCvtI2PD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>; 161defm : X86WriteRes<WriteCvtI2PDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>; 162defm : X86WriteRes<WriteCvtI2PDY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>; 163defm : X86WriteRes<WriteCvtI2PDYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>; 164defm : SPRWriteResPair<WriteCvtI2PDZ, [SPRPort00], 4, [1], 1, 8>; 165defm : SPRWriteResPair<WriteCvtI2PS, [SPRPort00_01], 4, [1], 1, 7>; 166defm : SPRWriteResPair<WriteCvtI2PSY, [SPRPort00_01], 4, [1], 1, 8>; 167defm : SPRWriteResPair<WriteCvtI2PSZ, [SPRPort00], 4, [1], 1, 8>; 168defm : X86WriteRes<WriteCvtI2SD, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>; 169defm : X86WriteRes<WriteCvtI2SDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>; 170defm : X86WriteRes<WriteCvtI2SS, [SPRPort00_01, SPRPort00_01_05, SPRPort05], 9, [1, 1, 1], 3>; 171defm : X86WriteRes<WriteCvtI2SSLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>; 172defm : X86WriteRes<WriteCvtPD2I, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>; 173defm : X86WriteRes<WriteCvtPD2ILd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>; 174defm : X86WriteRes<WriteCvtPD2IY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>; 175defm : X86WriteRes<WriteCvtPD2IYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>; 176defm : X86WriteRes<WriteCvtPD2IZ, [SPRPort00, SPRPort05], 7, [1, 1], 2>; 177defm : X86WriteRes<WriteCvtPD2IZLd, [SPRPort00, SPRPort02_03_10], 12, [1, 1], 2>; 178defm : SPRWriteResPair<WriteCvtPD2PS, [SPRPort00_01, SPRPort05], 5, [1, 1], 2, 7>; 179defm : SPRWriteResPair<WriteCvtPD2PSY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2, 8>; 180defm : SPRWriteResPair<WriteCvtPD2PSZ, [SPRPort00, SPRPort05], 7, [1, 1], 2, 8>; 181defm : X86WriteRes<WriteCvtPH2PS, [SPRPort00_01, SPRPort05], 6, [1, 1], 2>; 182defm : X86WriteRes<WriteCvtPH2PSLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>; 183defm : X86WriteRes<WriteCvtPH2PSY, [SPRPort00_01, SPRPort05], 8, [1, 1], 2>; 184defm : X86WriteRes<WriteCvtPH2PSYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>; 185defm : SPRWriteResPair<WriteCvtPH2PSZ, [SPRPort00, SPRPort05], 11, [1, 1], 2>; 186defm : SPRWriteResPair<WriteCvtPS2I, [SPRPort00_01], 4, [1], 1, 7>; 187defm : SPRWriteResPair<WriteCvtPS2IY, [SPRPort00_01], 4, [1], 1, 8>; 188defm : X86WriteRes<WriteCvtPS2IZ, [SPRPort00, SPRPort00_05, SPRPort05], 10, [1, 2, 1], 4>; 189defm : X86WriteRes<WriteCvtPS2IZLd, [SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05], 18, [1, 2, 1, 1, 1], 6>; 190defm : X86WriteRes<WriteCvtPS2PD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>; 191defm : X86WriteRes<WriteCvtPS2PDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>; 192defm : X86WriteRes<WriteCvtPS2PDY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>; 193defm : X86WriteRes<WriteCvtPS2PDYLd, [SPRPort00_01, SPRPort02_03_10], 12, [1, 1], 2>; 194defm : SPRWriteResPair<WriteCvtPS2PDZ, [SPRPort00, SPRPort05], 7, [1, 1], 2, 6>; 195defm : X86WriteRes<WriteCvtPS2PH, [SPRPort00_01, SPRPort05], 6, [1, 1], 2>; 196defm : X86WriteRes<WriteCvtPS2PHSt, [SPRPort00_01, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>; 197defm : X86WriteRes<WriteCvtPS2PHY, [SPRPort00_01, SPRPort05], 8, [1, 1], 2>; 198defm : X86WriteRes<WriteCvtPS2PHYSt, [SPRPort00_01, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>; 199defm : X86WriteRes<WriteCvtPS2PHZ, [SPRPort00, SPRPort05], 11, [1, 1], 2>; 200defm : X86WriteRes<WriteCvtPS2PHZSt, [SPRPort00, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>; 201defm : SPRWriteResPair<WriteCvtSD2I, [SPRPort00, SPRPort00_01], 7, [1, 1], 2>; 202defm : SPRWriteResPair<WriteCvtSD2SS, [SPRPort00_01, SPRPort05], 5, [1, 1], 2, 7>; 203defm : SPRWriteResPair<WriteCvtSS2I, [SPRPort00, SPRPort00_01], 7, [1, 1], 2>; 204defm : X86WriteRes<WriteCvtSS2SD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>; 205defm : X86WriteRes<WriteCvtSS2SDLd, [SPRPort00_01, SPRPort02_03_10], 11, [1, 1], 2>; 206defm : SPRWriteResPair<WriteDPPD, [SPRPort00_01, SPRPort01_05], 9, [2, 1], 3, 7>; 207defm : SPRWriteResPair<WriteDPPS, [SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort05], 14, [2, 1, 2, 1], 6, 7>; 208defm : SPRWriteResPair<WriteDPPSY, [SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort05], 14, [2, 1, 2, 1], 6, 8>; 209defm : SPRWriteResPair<WriteDiv16, [SPRPort00_01_05_06_11, SPRPort01], 16, [1, 3], 4, 4>; 210defm : SPRWriteResPair<WriteDiv32, [SPRPort00_01_05_06_11, SPRPort01], 15, [1, 3], 4, 4>; 211defm : SPRWriteResPair<WriteDiv64, [SPRPort01], 18, [3], 3>; 212defm : X86WriteRes<WriteDiv8, [SPRPort01], 17, [3], 3>; 213defm : X86WriteRes<WriteDiv8Ld, [SPRPort01], 22, [3], 3>; 214defm : X86WriteRes<WriteEMMS, [SPRPort00, SPRPort00_05, SPRPort00_06], 10, [1, 8, 1], 10>; 215defm : SPRWriteResPair<WriteFAdd, [SPRPort01_05], 3, [1], 1, 7>; 216defm : SPRWriteResPair<WriteFAdd64, [SPRPort01_05], 3, [1], 1, 7>; 217defm : SPRWriteResPair<WriteFAdd64X, [SPRPort01_05], 3, [1], 1, 7>; 218defm : SPRWriteResPair<WriteFAdd64Y, [SPRPort01_05], 3, [1], 1, 8>; 219defm : SPRWriteResPair<WriteFAdd64Z, [SPRPort00_05], 4, [1], 1, 7>; 220defm : SPRWriteResPair<WriteFAddX, [SPRPort00_01], 4, [1], 1, 7>; 221defm : SPRWriteResPair<WriteFAddY, [SPRPort00_01], 4, [1], 1, 8>; 222defm : SPRWriteResPair<WriteFAddZ, [SPRPort00], 4, [1], 1, 8>; 223defm : SPRWriteResPair<WriteFBlend, [SPRPort00_01_05], 1, [1], 1, 7>; 224defm : SPRWriteResPair<WriteFBlendY, [SPRPort00_01_05], 1, [1], 1, 8>; 225def : WriteRes<WriteFCMOV, [SPRPort01]> { 226 let Latency = 3; 227} 228defm : SPRWriteResPair<WriteFCmp, [SPRPort00_01], 4, [1], 1, 7>; 229defm : SPRWriteResPair<WriteFCmp64, [SPRPort00_01], 4, [1], 1, 7>; 230defm : SPRWriteResPair<WriteFCmp64X, [SPRPort00_01], 4, [1], 1, 7>; 231defm : SPRWriteResPair<WriteFCmp64Y, [SPRPort00_01], 4, [1], 1, 8>; 232defm : SPRWriteResPair<WriteFCmp64Z, [SPRPort00], 4, [1], 1, 8>; 233defm : SPRWriteResPair<WriteFCmpX, [SPRPort00_01], 4, [1], 1, 7>; 234defm : SPRWriteResPair<WriteFCmpY, [SPRPort00_01], 4, [1], 1, 8>; 235def : WriteRes<WriteFCmpZ, [SPRPort05]> { 236 let Latency = 3; 237} 238defm : X86WriteRes<WriteFCmpZLd, [SPRPort00, SPRPort02_03_10], 12, [1, 1], 2>; 239defm : SPRWriteResPair<WriteFCom, [SPRPort05], 1, [1], 1, 7>; 240defm : SPRWriteResPair<WriteFComX, [SPRPort00], 3, [1]>; 241defm : SPRWriteResPair<WriteFDiv, [SPRPort00], 11, [1], 1, 7>; 242defm : SPRWriteResPair<WriteFDiv64, [SPRPort00], 14, [1], 1, 6>; 243defm : SPRWriteResPair<WriteFDiv64X, [SPRPort00], 14, [1], 1, 6>; 244defm : SPRWriteResPair<WriteFDiv64Y, [SPRPort00], 14, [1], 1, 7>; 245defm : SPRWriteResPair<WriteFDiv64Z, [SPRPort00, SPRPort00_05], 23, [2, 1], 3, 7>; 246defm : SPRWriteResPair<WriteFDivX, [SPRPort00], 11, [1], 1, 7>; 247defm : SPRWriteResPair<WriteFDivY, [SPRPort00], 11, [1], 1, 8>; 248defm : SPRWriteResPair<WriteFDivZ, [SPRPort00, SPRPort00_05], 18, [2, 1], 3, 7>; 249defm : SPRWriteResPair<WriteFHAdd, [SPRPort01_05, SPRPort05], 6, [1, 2], 3, 6>; 250defm : SPRWriteResPair<WriteFHAddY, [SPRPort01_05, SPRPort05], 5, [1, 2], 3, 8>; 251def : WriteRes<WriteFLD0, [SPRPort00_05]>; 252defm : X86WriteRes<WriteFLD1, [SPRPort00_05], 1, [2], 2>; 253defm : X86WriteRes<WriteFLDC, [SPRPort00_05], 1, [2], 2>; 254def : WriteRes<WriteFLoad, [SPRPort02_03_10]> { 255 let Latency = 7; 256} 257def : WriteRes<WriteFLoadX, [SPRPort02_03_10]> { 258 let Latency = 7; 259} 260def : WriteRes<WriteFLoadY, [SPRPort02_03_10]> { 261 let Latency = 8; 262} 263defm : SPRWriteResPair<WriteFLogic, [SPRPort00_01_05], 1, [1], 1, 7>; 264defm : SPRWriteResPair<WriteFLogicY, [SPRPort00_01_05], 1, [1], 1, 8>; 265defm : SPRWriteResPair<WriteFLogicZ, [SPRPort00_05], 1, [1], 1, 8>; 266defm : SPRWriteResPair<WriteFMA, [SPRPort00_01], 4, [1], 1, 7>; 267defm : SPRWriteResPair<WriteFMAX, [SPRPort00_01], 4, [1], 1, 7>; 268defm : SPRWriteResPair<WriteFMAY, [SPRPort00_01], 4, [1], 1, 8>; 269defm : SPRWriteResPair<WriteFMAZ, [SPRPort00], 4, [1], 1, 8>; 270def : WriteRes<WriteFMOVMSK, [SPRPort00]> { 271 let Latency = 3; 272} 273defm : X86WriteRes<WriteFMaskedLoad, [SPRPort00_01_05, SPRPort02_03_10], 8, [1, 1], 2>; 274defm : X86WriteRes<WriteFMaskedLoadY, [SPRPort00_01_05, SPRPort02_03_10], 9, [1, 1], 2>; 275defm : X86WriteRes<WriteFMaskedStore32, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 276defm : X86WriteRes<WriteFMaskedStore32Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 277defm : X86WriteRes<WriteFMaskedStore64, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 278defm : X86WriteRes<WriteFMaskedStore64Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 279defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>; 280defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>; 281def : WriteRes<WriteFMoveZ, [SPRPort00_05]>; 282defm : SPRWriteResPair<WriteFMul, [SPRPort00_01], 4, [1], 1, 7>; 283defm : SPRWriteResPair<WriteFMul64, [SPRPort00_01], 4, [1], 1, 7>; 284defm : SPRWriteResPair<WriteFMul64X, [SPRPort00_01], 4, [1], 1, 7>; 285defm : SPRWriteResPair<WriteFMul64Y, [SPRPort00_01], 4, [1], 1, 8>; 286defm : SPRWriteResPair<WriteFMul64Z, [SPRPort00], 4, [1], 1, 8>; 287defm : SPRWriteResPair<WriteFMulX, [SPRPort00_01], 4, [1], 1, 7>; 288defm : SPRWriteResPair<WriteFMulY, [SPRPort00_01], 4, [1], 1, 8>; 289defm : SPRWriteResPair<WriteFMulZ, [SPRPort00], 4, [1], 1, 8>; 290defm : SPRWriteResPair<WriteFRcp, [SPRPort00], 4, [1], 1, 7>; 291defm : SPRWriteResPair<WriteFRcpX, [SPRPort00], 4, [1], 1, 7>; 292defm : SPRWriteResPair<WriteFRcpY, [SPRPort00], 4, [1], 1, 8>; 293defm : SPRWriteResPair<WriteFRcpZ, [SPRPort00, SPRPort00_05], 7, [2, 1], 3, 7>; 294defm : SPRWriteResPair<WriteFRnd, [SPRPort00_01], 4, [1], 1, 7>; 295defm : SPRWriteResPair<WriteFRndY, [SPRPort00_01], 4, [1], 1, 8>; 296defm : SPRWriteResPair<WriteFRndZ, [SPRPort00], 4, [1], 1, 8>; 297defm : SPRWriteResPair<WriteFRsqrt, [SPRPort00], 4, [1], 1, 7>; 298defm : SPRWriteResPair<WriteFRsqrtX, [SPRPort00], 4, [1], 1, 7>; 299defm : SPRWriteResPair<WriteFRsqrtY, [SPRPort00], 4, [1], 1, 8>; 300defm : SPRWriteResPair<WriteFRsqrtZ, [SPRPort00, SPRPort00_05], 9, [2, 1], 3>; 301defm : SPRWriteResPair<WriteFShuffle, [SPRPort05], 1, [1], 1, 7>; 302defm : SPRWriteResPair<WriteFShuffle256, [SPRPort05], 3, [1], 1, 8>; 303defm : SPRWriteResPair<WriteFShuffleY, [SPRPort05], 1, [1], 1, 8>; 304defm : SPRWriteResPair<WriteFShuffleZ, [SPRPort05], 1, [1], 1, 8>; 305def : WriteRes<WriteFSign, [SPRPort00]>; 306defm : SPRWriteResPair<WriteFSqrt, [SPRPort00], 12, [1], 1, 7>; 307defm : SPRWriteResPair<WriteFSqrt64, [SPRPort00], 18, [1]>; 308defm : SPRWriteResPair<WriteFSqrt64X, [SPRPort00], 18, [1], 1, 6>; 309defm : SPRWriteResPair<WriteFSqrt64Y, [SPRPort00], 18, [1], 1, 3>; 310// Warning: negtive load latency. 311defm : SPRWriteResPair<WriteFSqrt64Z, [SPRPort00, SPRPort00_05], 32, [2, 1], 3, -1>; 312def : WriteRes<WriteFSqrt80, [SPRPortInvalid, SPRPort00]> { 313 let ReleaseAtCycles = [7, 1]; 314 let Latency = 21; 315} 316defm : SPRWriteResPair<WriteFSqrtX, [SPRPort00], 12, [1], 1, 7>; 317defm : SPRWriteResPair<WriteFSqrtY, [SPRPort00], 12, [1], 1, 8>; 318defm : SPRWriteResPair<WriteFSqrtZ, [SPRPort00, SPRPort00_05], 20, [2, 1], 3, 7>; 319defm : X86WriteRes<WriteFStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 320defm : X86WriteResUnsupported<WriteFStoreNT>; 321defm : X86WriteRes<WriteFStoreNTX, [SPRPort04_09, SPRPort07_08], 518, [1, 1], 2>; 322defm : X86WriteRes<WriteFStoreNTY, [SPRPort04_09, SPRPort07_08], 542, [1, 1], 2>; 323defm : X86WriteRes<WriteFStoreX, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 324defm : X86WriteRes<WriteFStoreY, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 325defm : SPRWriteResPair<WriteFTest, [SPRPort00], 3, [1]>; 326defm : SPRWriteResPair<WriteFTestY, [SPRPort00], 5, [1], 1, 6>; 327defm : SPRWriteResPair<WriteFVarBlend, [SPRPort00_01_05], 1, [1], 1, 7>; 328defm : SPRWriteResPair<WriteFVarBlendY, [SPRPort00_01_05], 1, [1], 1, 8>; 329defm : SPRWriteResPair<WriteFVarBlendZ, [SPRPort00_05], 1, [1], 1, 8>; 330defm : SPRWriteResPair<WriteFVarShuffle, [SPRPort05], 1, [1], 1, 7>; 331defm : SPRWriteResPair<WriteFVarShuffle256, [SPRPort05], 3, [1], 1, 8>; 332defm : SPRWriteResPair<WriteFVarShuffleY, [SPRPort05], 1, [1], 1, 8>; 333defm : SPRWriteResPair<WriteFVarShuffleZ, [SPRPort05], 1, [1], 1, 8>; 334def : WriteRes<WriteFence, [SPRPort00_06]> { 335 let Latency = 2; 336} 337defm : SPRWriteResPair<WriteIDiv16, [SPRPort00_01_05_06_11, SPRPort01], 16, [1, 3], 4, 4>; 338defm : SPRWriteResPair<WriteIDiv32, [SPRPort00_01_05_06_11, SPRPort01], 15, [1, 3], 4, 4>; 339defm : SPRWriteResPair<WriteIDiv64, [SPRPort01], 18, [3], 3>; 340defm : X86WriteRes<WriteIDiv8, [SPRPort01], 17, [3], 3>; 341defm : X86WriteRes<WriteIDiv8Ld, [SPRPort01], 22, [3], 3>; 342defm : SPRWriteResPair<WriteIMul16, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 5, [2, 1, 1], 4>; 343defm : SPRWriteResPair<WriteIMul16Imm, [SPRPort00_01_05_06_11, SPRPort01], 4, [1, 1], 2>; 344defm : SPRWriteResPair<WriteIMul16Reg, [SPRPort01], 3, [1]>; 345defm : SPRWriteResPair<WriteIMul32, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 4, [1, 1, 1], 3>; 346defm : SPRWriteResPair<WriteIMul32Imm, [SPRPort01], 3, [1]>; 347defm : SPRWriteResPair<WriteIMul32Reg, [SPRPort01], 3, [1]>; 348defm : SPRWriteResPair<WriteIMul64, [SPRPort01, SPRPort05], 4, [1, 1], 2>; 349defm : SPRWriteResPair<WriteIMul64Imm, [SPRPort01], 3, [1]>; 350defm : SPRWriteResPair<WriteIMul64Reg, [SPRPort01], 3, [1]>; 351defm : SPRWriteResPair<WriteIMul8, [SPRPort01], 3, [1]>; 352def : WriteRes<WriteIMulH, []> { 353 let Latency = 3; 354} 355def : WriteRes<WriteIMulHLd, []> { 356 let Latency = 3; 357} 358defm : SPRWriteResPair<WriteJump, [SPRPort00_06], 1, [1]>; 359def : WriteRes<WriteLAHFSAHF, [SPRPort00_06]> { 360 let Latency = 3; 361} 362defm : X86WriteRes<WriteLDMXCSR, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10], 7, [1, 1, 1, 1], 4>; 363def : WriteRes<WriteLEA, [SPRPort01]>; 364defm : SPRWriteResPair<WriteLZCNT, [SPRPort01], 3, [1]>; 365def : WriteRes<WriteLoad, [SPRPort02_03_10]> { 366 let Latency = 5; 367} 368def : WriteRes<WriteMMXMOVMSK, [SPRPort00]> { 369 let Latency = 3; 370} 371defm : SPRWriteResPair<WriteMPSAD, [SPRPort01_05, SPRPort05], 4, [1, 1], 2, 7>; 372defm : SPRWriteResPair<WriteMPSADY, [SPRPort01_05, SPRPort05], 4, [1, 1], 2, 8>; 373defm : SPRWriteResPair<WriteMULX32, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 4, [1, 1, 1], 2>; 374defm : SPRWriteResPair<WriteMULX64, [SPRPort01, SPRPort05], 4, [1, 1]>; 375def : WriteRes<WriteMicrocoded, [SPRPort00_01_05_06]> { 376 let Latency = SapphireRapidsModel.MaxLatency; 377} 378def : WriteRes<WriteMove, [SPRPort00]> { 379 let Latency = 3; 380} 381defm : X86WriteRes<WriteNop, [], 1, [], 0>; 382defm : X86WriteRes<WritePCmpEStrI, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort05], 16, [3, 2, 1, 1, 1], 8>; 383defm : X86WriteRes<WritePCmpEStrILd, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05], 31, [3, 1, 1, 1, 1, 1], 8>; 384defm : X86WriteRes<WritePCmpEStrM, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort05], 16, [3, 3, 1, 1, 1], 9>; 385defm : X86WriteRes<WritePCmpEStrMLd, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05], 17, [3, 2, 1, 1, 1, 1], 9>; 386defm : SPRWriteResPair<WritePCmpIStrI, [SPRPort00], 11, [3], 3, 20>; 387defm : SPRWriteResPair<WritePCmpIStrM, [SPRPort00], 11, [3], 3>; 388defm : SPRWriteResPair<WritePHAdd, [SPRPort00_05, SPRPort05], 3, [1, 2], 3, 8>; 389defm : SPRWriteResPair<WritePHAddX, [SPRPort00_01_05, SPRPort01_05], 2, [1, 2], 3, 7>; 390defm : SPRWriteResPair<WritePHAddY, [SPRPort00_01_05, SPRPort01_05], 2, [1, 2], 3, 8>; 391defm : SPRWriteResPair<WritePHMINPOS, [SPRPort00], 4, [1], 1, 7>; 392defm : SPRWriteResPair<WritePMULLD, [SPRPort00_01], 10, [2], 2, 8>; 393defm : SPRWriteResPair<WritePMULLDY, [SPRPort00_01], 10, [2], 2, 8>; 394defm : SPRWriteResPair<WritePMULLDZ, [SPRPort00], 10, [2], 2, 8>; 395defm : SPRWriteResPair<WritePOPCNT, [SPRPort01], 3, [1]>; 396defm : SPRWriteResPair<WritePSADBW, [SPRPort05], 3, [1], 1, 8>; 397defm : SPRWriteResPair<WritePSADBWX, [SPRPort05], 3, [1], 1, 7>; 398defm : SPRWriteResPair<WritePSADBWY, [SPRPort05], 3, [1], 1, 8>; 399defm : SPRWriteResPair<WritePSADBWZ, [SPRPort05], 3, [1], 1, 8>; 400defm : X86WriteRes<WriteRMW, [SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 1, [1, 1, 1], 3>; 401defm : X86WriteRes<WriteRotate, [SPRPort00_01_05_06_11, SPRPort00_06], 2, [1, 2], 3>; 402defm : X86WriteRes<WriteRotateLd, [SPRPort00_01_05_06_11, SPRPort00_06], 12, [1, 2], 3>; 403defm : X86WriteRes<WriteRotateCL, [SPRPort00_06], 2, [2], 2>; 404defm : X86WriteRes<WriteRotateCLLd, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 19, [2, 3, 2], 7>; 405defm : X86WriteRes<WriteSETCC, [SPRPort00_06], 2, [2], 2>; 406defm : X86WriteRes<WriteSETCCStore, [SPRPort00_06, SPRPort04_09, SPRPort07_08], 13, [2, 1, 1], 4>; 407defm : X86WriteRes<WriteSHDmrcl, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1, 1, 1], 6>; 408defm : X86WriteRes<WriteSHDmri, [SPRPort00_01_05_06_11, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1, 1], 5>; 409defm : X86WriteRes<WriteSHDrrcl, [SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01], 5, [1, 1, 1], 3>; 410def : WriteRes<WriteSHDrri, [SPRPort01]> { 411 let Latency = 3; 412} 413defm : X86WriteRes<WriteSTMXCSR, [SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1], 4>; 414def : WriteRes<WriteShift, [SPRPort00_06]>; 415def : WriteRes<WriteShiftLd, [SPRPort00_06]> { 416 let Latency = 12; 417} 418defm : X86WriteRes<WriteShiftCL, [SPRPort00_06], 2, [2], 2>; 419defm : X86WriteRes<WriteShiftCLLd, [SPRPort00_06], 12, [2], 2>; 420defm : SPRWriteResPair<WriteShuffle, [SPRPort05], 1, [1], 1, 8>; 421defm : SPRWriteResPair<WriteShuffle256, [SPRPort05], 3, [1], 1, 8>; 422defm : SPRWriteResPair<WriteShuffleX, [SPRPort01_05], 1, [1], 1, 7>; 423defm : SPRWriteResPair<WriteShuffleY, [SPRPort01_05], 1, [1], 1, 8>; 424defm : SPRWriteResPair<WriteShuffleZ, [SPRPort05], 3, [1], 1, 6>; 425defm : X86WriteRes<WriteStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 426defm : X86WriteRes<WriteStoreNT, [SPRPort04_09, SPRPort07_08], 512, [1, 1], 2>; 427def : WriteRes<WriteSystem, [SPRPort00_01_05_06]> { 428 let Latency = SapphireRapidsModel.MaxLatency; 429} 430defm : SPRWriteResPair<WriteTZCNT, [SPRPort01], 3, [1]>; 431defm : SPRWriteResPair<WriteVPMOV256, [SPRPort05], 3, [1], 1, 8>; 432defm : SPRWriteResPair<WriteVarBlend, [SPRPort00_01_05], 1, [1], 1, 7>; 433defm : SPRWriteResPair<WriteVarBlendY, [SPRPort00_01_05], 1, [1], 1, 8>; 434defm : SPRWriteResPair<WriteVarBlendZ, [SPRPort00_05], 1, [1], 1, 8>; 435defm : SPRWriteResPair<WriteVarShuffle, [SPRPort00, SPRPort05], 3, [1, 1], 2, 8>; 436defm : X86WriteRes<WriteVarShuffle256, [SPRPort05], 6, [2], 2>; 437defm : X86WriteRes<WriteVarShuffle256Ld, [SPRPort02_03_10, SPRPort05], 11, [1, 1], 2>; 438defm : SPRWriteResPair<WriteVarShuffleX, [SPRPort01_05], 1, [1], 1, 7>; 439defm : SPRWriteResPair<WriteVarShuffleY, [SPRPort01_05], 1, [1], 1, 8>; 440defm : SPRWriteResPair<WriteVarShuffleZ, [SPRPort05], 3, [1], 1, 8>; 441defm : SPRWriteResPair<WriteVarVecShift, [SPRPort00_01], 1, [1], 1, 7>; 442defm : SPRWriteResPair<WriteVarVecShiftY, [SPRPort00_01], 1, [1], 1, 8>; 443defm : SPRWriteResPair<WriteVarVecShiftZ, [SPRPort00], 1, [1], 1, 8>; 444defm : SPRWriteResPair<WriteVecALU, [SPRPort00], 1, [1], 1, 8>; 445defm : SPRWriteResPair<WriteVecALUX, [SPRPort00_01], 1, [1], 1, 7>; 446defm : SPRWriteResPair<WriteVecALUY, [SPRPort00_01], 1, [1], 1, 8>; 447def : WriteRes<WriteVecALUZ, [SPRPort05]> { 448 let Latency = 3; 449} 450defm : X86WriteRes<WriteVecALUZLd, [SPRPort00, SPRPort02_03_10], 9, [1, 1], 2>; 451defm : X86WriteRes<WriteVecExtract, [SPRPort00, SPRPort01_05], 4, [1, 1], 2>; 452defm : X86WriteRes<WriteVecExtractSt, [SPRPort01_05, SPRPort04_09, SPRPort07_08], 19, [1, 1, 1], 3>; 453defm : SPRWriteResPair<WriteVecIMul, [SPRPort00], 5, [1], 1, 8>; 454defm : SPRWriteResPair<WriteVecIMulX, [SPRPort00_01], 5, [1], 1, 8>; 455defm : SPRWriteResPair<WriteVecIMulY, [SPRPort00_01], 5, [1], 1, 8>; 456defm : SPRWriteResPair<WriteVecIMulZ, [SPRPort00], 5, [1], 1, 8>; 457defm : X86WriteRes<WriteVecInsert, [SPRPort01_05, SPRPort05], 4, [1, 1], 2>; 458defm : X86WriteRes<WriteVecInsertLd, [SPRPort01_05, SPRPort02_03_10], 8, [1, 1], 2>; 459def : WriteRes<WriteVecLoad, [SPRPort02_03_10]> { 460 let Latency = 7; 461} 462def : WriteRes<WriteVecLoadNT, [SPRPort02_03_10]> { 463 let Latency = 7; 464} 465def : WriteRes<WriteVecLoadNTY, [SPRPort02_03_10]> { 466 let Latency = 8; 467} 468def : WriteRes<WriteVecLoadX, [SPRPort02_03_10]> { 469 let Latency = 7; 470} 471def : WriteRes<WriteVecLoadY, [SPRPort02_03_10]> { 472 let Latency = 8; 473} 474defm : SPRWriteResPair<WriteVecLogic, [SPRPort00_05], 1, [1], 1, 8>; 475defm : SPRWriteResPair<WriteVecLogicX, [SPRPort00_01_05], 1, [1], 1, 7>; 476defm : SPRWriteResPair<WriteVecLogicY, [SPRPort00_01_05], 1, [1], 1, 8>; 477defm : SPRWriteResPair<WriteVecLogicZ, [SPRPort00_05], 1, [1], 1, 8>; 478def : WriteRes<WriteVecMOVMSK, [SPRPort00]> { 479 let Latency = 3; 480} 481def : WriteRes<WriteVecMOVMSKY, [SPRPort00]> { 482 let Latency = 4; 483} 484defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 485defm : X86WriteRes<WriteVecMaskedLoad, [SPRPort00_01_05, SPRPort02_03_10], 8, [1, 1], 2>; 486defm : X86WriteRes<WriteVecMaskedLoadY, [SPRPort00_01_05, SPRPort02_03_10], 9, [1, 1], 2>; 487defm : X86WriteRes<WriteVecMaskedStore32, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 488defm : X86WriteRes<WriteVecMaskedStore32Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 489defm : X86WriteRes<WriteVecMaskedStore64, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 490defm : X86WriteRes<WriteVecMaskedStore64Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>; 491def : WriteRes<WriteVecMove, [SPRPort00_05]>; 492def : WriteRes<WriteVecMoveFromGpr, [SPRPort05]> { 493 let Latency = 3; 494} 495def : WriteRes<WriteVecMoveToGpr, [SPRPort00]> { 496 let Latency = 3; 497} 498defm : X86WriteRes<WriteVecMoveX, [], 1, [], 0>; 499def : WriteRes<WriteVecMoveY, [SPRPort00_01_05]>; 500def : WriteRes<WriteVecMoveZ, [SPRPort00_05]>; 501defm : SPRWriteResPair<WriteVecShift, [SPRPort00], 1, [1], 1, 8>; 502def : WriteRes<WriteVecShiftImm, [SPRPort00]>; 503defm : SPRWriteResPair<WriteVecShiftImmX, [SPRPort00_01], 1, [1], 1, 7>; 504defm : SPRWriteResPair<WriteVecShiftImmY, [SPRPort00_01], 1, [1], 1, 8>; 505defm : SPRWriteResPair<WriteVecShiftImmZ, [SPRPort00], 1, [1], 1, 8>; 506defm : X86WriteRes<WriteVecShiftX, [SPRPort00_01, SPRPort01_05], 2, [1, 1], 2>; 507defm : X86WriteRes<WriteVecShiftXLd, [SPRPort00_01, SPRPort02_03_10], 8, [1, 1], 2>; 508defm : X86WriteRes<WriteVecShiftY, [SPRPort00_01, SPRPort05], 4, [1, 1], 2>; 509defm : X86WriteRes<WriteVecShiftYLd, [SPRPort00_01, SPRPort02_03_10], 9, [1, 1], 2>; 510defm : X86WriteRes<WriteVecShiftZ, [SPRPort00, SPRPort05], 4, [1, 1], 2>; 511defm : X86WriteRes<WriteVecShiftZLd, [SPRPort00, SPRPort02_03_10], 9, [1, 1], 2>; 512defm : X86WriteRes<WriteVecStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 513defm : X86WriteRes<WriteVecStoreNT, [SPRPort04_09, SPRPort07_08], 511, [1, 1], 2>; 514defm : X86WriteRes<WriteVecStoreNTY, [SPRPort04_09, SPRPort07_08], 507, [1, 1], 2>; 515defm : X86WriteRes<WriteVecStoreX, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 516defm : X86WriteRes<WriteVecStoreY, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>; 517defm : SPRWriteResPair<WriteVecTest, [SPRPort00, SPRPort05], 4, [1, 1], 2>; 518defm : SPRWriteResPair<WriteVecTestY, [SPRPort00, SPRPort05], 6, [1, 1], 2, 6>; 519defm : X86WriteRes<WriteXCHG, [SPRPort00_01_05_06_11], 2, [3], 3>; 520def : WriteRes<WriteZero, []>; 521 522// Infered SchedWriteRes and InstRW definition. 523 524def SPRWriteResGroup0 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_10, SPRPort04, SPRPort04_09]> { 525 let Latency = 7; 526 let NumMicroOps = 3; 527} 528def : InstRW<[SPRWriteResGroup0], (instregex "^AA(D|N)D64mr$", 529 "^A(X?)OR64mr$")>; 530 531def SPRWriteResGroup1 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 532 let ReleaseAtCycles = [2, 1, 1, 1, 1]; 533 let Latency = 12; 534 let NumMicroOps = 6; 535} 536def : InstRW<[SPRWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>; 537 538def SPRWriteResGroup2 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> { 539 let Latency = 6; 540 let NumMicroOps = 2; 541} 542def : InstRW<[SPRWriteResGroup2], (instregex "^RORX(32|64)mi$")>; 543def : InstRW<[SPRWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$", 544 "^AD(C|O)X(32|64)rm$")>; 545 546def SPRWriteResGroup3 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 547 let Latency = 13; 548 let NumMicroOps = 5; 549} 550def : InstRW<[SPRWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>; 551 552def SPRWriteResGroup4 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 553 let ReleaseAtCycles = [2, 1, 1, 1, 1]; 554 let Latency = 13; 555 let NumMicroOps = 6; 556} 557def : InstRW<[SPRWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>; 558 559def SPRWriteResGroup5 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 560 let Latency = 6; 561 let NumMicroOps = 2; 562} 563def : InstRW<[SPRWriteResGroup5], (instregex "^CMP(8|16|32)mi$", 564 "^CMP(8|16|32|64)mi8$", 565 "^MOV(8|16)rm$", 566 "^POP(16|32)r((mr)?)$")>; 567def : InstRW<[SPRWriteResGroup5], (instrs CMP64mi32, 568 MOV8rm_NOREX, 569 MOVZX16rm8)>; 570def : InstRW<[SPRWriteResGroup5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$", 571 "^AND(8|16|32)rm$", 572 "^(X?)OR(8|16|32)rm$")>; 573def : InstRW<[SPRWriteResGroup5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>; 574 575def SPRWriteResGroup6 : SchedWriteRes<[]> { 576 let NumMicroOps = 0; 577} 578def : InstRW<[SPRWriteResGroup6], (instregex "^(ADD|SUB)64ri8$", 579 "^(DE|IN)C64r$", 580 "^MOV64rr((_REV)?)$", 581 "^VMOV(A|U)P(D|S)Zrr((_REV)?)$", 582 "^VMOVDQA(32|64)Z((256)?)rr((_REV)?)$", 583 "^VMOVDQ(A|U)Yrr((_REV)?)$", 584 "^VMOVDQU(8|16|32|64)Z((256)?)rr((_REV)?)$")>; 585def : InstRW<[SPRWriteResGroup6], (instrs CLC, 586 JMP_2)>; 587 588def SPRWriteResGroup7 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 589 let Latency = 13; 590 let NumMicroOps = 4; 591} 592def : InstRW<[SPRWriteResGroup7], (instregex "^A(D|N)D8mi(8?)$", 593 "^(DE|IN)C8m$", 594 "^N(EG|OT)8m$", 595 "^(X?)OR8mi(8?)$", 596 "^SUB8mi(8?)$")>; 597def : InstRW<[SPRWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$", 598 "^(X?)OR8mr$")>; 599def : InstRW<[SPRWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>; 600 601def SPRWriteResGroup8 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> { 602 let Latency = 10; 603 let NumMicroOps = 2; 604} 605def : InstRW<[SPRWriteResGroup8, ReadAfterVecXLd], (instregex "^(V?)(ADD|SUB)PSrm$", 606 "^(V?)ADDSUBPSrm$", 607 "^V(ADD|SUB)PSZ128rm((b|k|bk|kz)?)$", 608 "^V(ADD|SUB)PSZ128rmbkz$")>; 609 610def SPRWriteResGroup9 : SchedWriteRes<[SPRPort01_05]> { 611 let Latency = 3; 612} 613def : InstRW<[SPRWriteResGroup9], (instregex "^(V?)(ADD|SUB)PSrr$", 614 "^(V?)ADDSUBPSrr$", 615 "^V(ADD|SUB)PSYrr$", 616 "^V(ADD|SUB)PSZ(128|256)rr(k?)$", 617 "^VPMOV(S|Z)XBWZ128rrk(z?)$", 618 "^VPSHUFBZ(128|256)rrk(z?)$", 619 "^VPSHUF(H|L)WZ(128|256)rik(z?)$", 620 "^VPUNPCK(H|L)(BW|WD)Z(128|256)rrk(z?)$")>; 621def : InstRW<[SPRWriteResGroup9], (instrs VADDSUBPSYrr)>; 622 623def SPRWriteResGroup10 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 624 let Latency = 10; 625 let NumMicroOps = 2; 626} 627def : InstRW<[SPRWriteResGroup10], (instregex "^ADD_F(32|64)m$", 628 "^ILD_F(16|32|64)m$", 629 "^SUB(R?)_F(32|64)m$", 630 "^VPOPCNT(B|D|Q|W)Z128rm$", 631 "^VPOPCNT(D|Q)Z128rm(b|k|kz)$", 632 "^VPOPCNT(D|Q)Z128rmbk(z?)$")>; 633def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$", 634 "^(V?)PCMPGTQrm$", 635 "^VFPCLASSP(D|H|S)Z128mbi$", 636 "^VPACK(S|U)S(DW|WB)Z128rm$", 637 "^VPACK(S|U)SDWZ128rmb$", 638 "^VPM(AX|IN)(S|U)QZ128rm((b|k|bk|kz)?)$", 639 "^VPM(AX|IN)(S|U)QZ128rmbkz$", 640 "^VPMULTISHIFTQBZ128rm(b?)$")>; 641def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128mi)>; 642def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)mi$", 643 "^VPERM(I|T)2(D|Q|PS)Z128rm((b|k|bk|kz)?)$", 644 "^VPERM(I|T)2(D|Q|PS)Z128rmbkz$", 645 "^VPERM(I|T)2PDZ128rm((b|k|bk|kz)?)$", 646 "^VPERM(I|T)2PDZ128rmbkz$")>; 647def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instrs VPERMBZ128rm)>; 648 649def SPRWriteResGroup11 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 650 let ReleaseAtCycles = [1, 2]; 651 let Latency = 13; 652 let NumMicroOps = 3; 653} 654def : InstRW<[SPRWriteResGroup11], (instregex "^ADD_FI(16|32)m$", 655 "^SUB(R?)_FI(16|32)m$")>; 656def : InstRW<[SPRWriteResGroup11, ReadAfterVecXLd], (instrs SHA256MSG2rm)>; 657def : InstRW<[SPRWriteResGroup11, ReadAfterVecYLd], (instregex "^VPEXPAND(B|W)Z(128|256)rmk(z?)$", 658 "^VPEXPAND(B|W)Zrmk(z?)$")>; 659 660def SPRWriteResGroup12 : SchedWriteRes<[SPRPort05]> { 661 let Latency = 3; 662} 663def : InstRW<[SPRWriteResGroup12], (instregex "^ADD_F(P?)rST0$", 664 "^KMOV(B|D|W)kr$", 665 "^(V?)PACK(S|U)S(DW|WB)rr$", 666 "^(V?)PCMPGTQrr$", 667 "^SUB(R?)_F(P?)rST0$", 668 "^SUB(R?)_FST0r$", 669 "^VALIGN(D|Q)Z256rri((k|kz)?)$", 670 "^VCMPP(D|H|S)Z(128|256)rri(k?)$", 671 "^VCMPS(D|H|S)Zrri$", 672 "^VCMPS(D|H|S)Zrr(b?)i(k?)_Int$", 673 "^VFPCLASSP(D|H|S)Z(128|256)ri(k?)$", 674 "^VFPCLASSS(D|H|S)Zri(k?)$", 675 "^VPACK(S|U)S(DW|WB)Yrr$", 676 "^VPACK(S|U)S(DW|WB)Z(128|256)rr$", 677 "^VPALIGNRZ(128|256)rrik(z?)$", 678 "^VPBROADCAST(B|W)Z128rrk(z?)$", 679 "^VPCMP(B|D|Q|W|UD|UQ|UW)Z(128|256)rri(k?)$", 680 "^VPCMP(EQ|GT)(B|D|Q|W)Z(128|256)rr(k?)$", 681 "^VPCMPUBZ(128|256)rri(k?)$", 682 "^VPERMBZ(128|256)rr$", 683 "^VPERM(B|D|Q)Zrr$", 684 "^VPERM(D|Q)Z256rr((k|kz)?)$", 685 "^VPERM(D|Q)Zrrk(z?)$", 686 "^VPERM(I|T)2(D|Q)Z(128|256)rr((k|kz)?)$", 687 "^VPERM(I|T)2(D|Q)Zrr((k|kz)?)$", 688 "^VPM(AX|IN)(S|U)QZ(128|256)rr((k|kz)?)$", 689 "^VPMULTISHIFTQBZ(128|256)rr$", 690 "^VPOPCNT(B|D|Q|W)Z(128|256)rr$", 691 "^VPOPCNT(D|Q)Z(128|256)rrk(z?)$", 692 "^VPTEST(N?)M(B|D|Q|W)Z(128|256)rr(k?)$", 693 "^VPTEST(N?)M(B|D|Q|W)Zrr(k?)$")>; 694def : InstRW<[SPRWriteResGroup12], (instrs ADD_FST0r, 695 VPCMPGTQYrr, 696 VPERMDYrr)>; 697 698def SPRWriteResGroup13 : SchedWriteRes<[SPRPort00_01_05_06_11]> { 699 let Latency = 2; 700} 701def : InstRW<[SPRWriteResGroup13], (instregex "^AND(8|16|32|64)r(r|i8)$", 702 "^AND(8|16|32|64)rr_REV$", 703 "^(AND|TEST)(32|64)i32$", 704 "^(AND|TEST)(8|32)ri$", 705 "^(AND|TEST)64ri32$", 706 "^(AND|TEST)8i8$", 707 "^(X?)OR(8|16|32|64)r(r|i8)$", 708 "^(X?)OR(8|16|32|64)rr_REV$", 709 "^(X?)OR(32|64)i32$", 710 "^(X?)OR(8|32)ri$", 711 "^(X?)OR64ri32$", 712 "^(X?)OR8i8$", 713 "^TEST(8|16|32|64)rr$")>; 714def : InstRW<[SPRWriteResGroup13], (instrs XOR8rr_NOREX)>; 715 716def SPRWriteResGroup14 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 717 let Latency = 7; 718 let NumMicroOps = 2; 719} 720def : InstRW<[SPRWriteResGroup14], (instregex "^TEST(8|16|32)mi$")>; 721def : InstRW<[SPRWriteResGroup14], (instrs TEST64mi32)>; 722def : InstRW<[SPRWriteResGroup14, ReadAfterLd], (instregex "^(X?)OR64rm$")>; 723def : InstRW<[SPRWriteResGroup14, ReadAfterLd], (instrs AND64rm)>; 724def : InstRW<[SPRWriteResGroup14, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>; 725 726def SPRWriteResGroup15 : SchedWriteRes<[SPRPort01_05_11, SPRPort02_03_10]> { 727 let Latency = 7; 728 let NumMicroOps = 2; 729} 730def : InstRW<[SPRWriteResGroup15, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>; 731 732def SPRWriteResGroup16 : SchedWriteRes<[SPRPort01_05_11]> { 733 let Latency = 2; 734} 735def : InstRW<[SPRWriteResGroup16], (instregex "^ANDN(32|64)rr$")>; 736 737def SPRWriteResGroup17 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10]> { 738 let ReleaseAtCycles = [5, 2, 1, 1]; 739 let Latency = 10; 740 let NumMicroOps = 9; 741} 742def : InstRW<[SPRWriteResGroup17], (instrs BT64mr)>; 743 744def SPRWriteResGroup18 : SchedWriteRes<[SPRPort01]> { 745 let Latency = 3; 746} 747def : InstRW<[SPRWriteResGroup18], (instregex "^BT((C|R|S)?)64rr$", 748 "^P(DEP|EXT)(32|64)rr$")>; 749 750def SPRWriteResGroup19 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 751 let ReleaseAtCycles = [4, 2, 1, 1, 1, 1]; 752 let Latency = 17; 753 let NumMicroOps = 10; 754} 755def : InstRW<[SPRWriteResGroup19], (instregex "^BT(C|R|S)64mr$")>; 756 757def SPRWriteResGroup20 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 758 let Latency = 7; 759 let NumMicroOps = 5; 760} 761def : InstRW<[SPRWriteResGroup20], (instregex "^CALL(16|32|64)m((_NT)?)$")>; 762 763def SPRWriteResGroup21 : SchedWriteRes<[SPRPort00_06, SPRPort04_09, SPRPort07_08]> { 764 let Latency = 3; 765 let NumMicroOps = 3; 766} 767def : InstRW<[SPRWriteResGroup21], (instregex "^CALL(16|32|64)r((_NT)?)$")>; 768 769def SPRWriteResGroup22 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 770 let Latency = 3; 771 let NumMicroOps = 2; 772} 773def : InstRW<[SPRWriteResGroup22], (instrs CALL64pcrel32, 774 MFENCE)>; 775 776def SPRWriteResGroup23 : SchedWriteRes<[SPRPort01_05]>; 777def : InstRW<[SPRWriteResGroup23], (instregex "^C(DQ|WD)E$", 778 "^(V?)MOVS(H|L)DUPrr$", 779 "^(V?)SHUFP(D|S)rri$", 780 "^VMOVS(H|L)DUPYrr$", 781 "^VMOVS(H|L)DUPZ(128|256)rr((k|kz)?)$", 782 "^VPMOVQDZ128rr((k|kz)?)$", 783 "^VSHUFP(D|S)Yrri$", 784 "^VSHUFP(D|S)Z(128|256)rri((k|kz)?)$")>; 785def : InstRW<[SPRWriteResGroup23], (instrs CBW, 786 VPBLENDWYrri)>; 787 788def SPRWriteResGroup24 : SchedWriteRes<[SPRPort00_06]>; 789def : InstRW<[SPRWriteResGroup24], (instregex "^C(DQ|QO)$", 790 "^(CL|ST)AC$")>; 791 792def SPRWriteResGroup25 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 793 let Latency = 3; 794 let NumMicroOps = 2; 795} 796def : InstRW<[SPRWriteResGroup25], (instrs CLD)>; 797 798def SPRWriteResGroup26 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 799 let Latency = 3; 800 let NumMicroOps = 3; 801} 802def : InstRW<[SPRWriteResGroup26], (instrs CLDEMOTE)>; 803 804def SPRWriteResGroup27 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort04_09, SPRPort07_08]> { 805 let Latency = 2; 806 let NumMicroOps = 4; 807} 808def : InstRW<[SPRWriteResGroup27], (instrs CLFLUSH)>; 809 810def SPRWriteResGroup28 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 811 let Latency = 2; 812 let NumMicroOps = 3; 813} 814def : InstRW<[SPRWriteResGroup28], (instrs CLFLUSHOPT)>; 815 816def SPRWriteResGroup29 : SchedWriteRes<[SPRPort00_06, SPRPort01]> { 817 let ReleaseAtCycles = [2, 1]; 818 let Latency = SapphireRapidsModel.MaxLatency; 819 let NumMicroOps = 3; 820} 821def : InstRW<[SPRWriteResGroup29], (instrs CLI)>; 822 823def SPRWriteResGroup30 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort05]> { 824 let ReleaseAtCycles = [6, 1, 3]; 825 let Latency = SapphireRapidsModel.MaxLatency; 826 let NumMicroOps = 10; 827} 828def : InstRW<[SPRWriteResGroup30], (instrs CLTS)>; 829 830def SPRWriteResGroup31 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 831 let Latency = 5; 832 let NumMicroOps = 3; 833} 834def : InstRW<[SPRWriteResGroup31], (instregex "^MOV16o(16|32|64)a$")>; 835def : InstRW<[SPRWriteResGroup31], (instrs CLWB)>; 836 837def SPRWriteResGroup32 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 838 let ReleaseAtCycles = [5, 2]; 839 let Latency = 6; 840 let NumMicroOps = 7; 841} 842def : InstRW<[SPRWriteResGroup32], (instregex "^CMPS(B|L|Q|W)$")>; 843 844def SPRWriteResGroup33 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 845 let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1]; 846 let Latency = 32; 847 let NumMicroOps = 22; 848} 849def : InstRW<[SPRWriteResGroup33], (instrs CMPXCHG16B)>; 850 851def SPRWriteResGroup34 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 852 let ReleaseAtCycles = [4, 7, 2, 1, 1, 1]; 853 let Latency = 25; 854 let NumMicroOps = 16; 855} 856def : InstRW<[SPRWriteResGroup34], (instrs CMPXCHG8B)>; 857 858def SPRWriteResGroup35 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 859 let ReleaseAtCycles = [1, 2, 1, 1, 1]; 860 let Latency = 13; 861 let NumMicroOps = 6; 862} 863def : InstRW<[SPRWriteResGroup35], (instrs CMPXCHG8rm)>; 864 865def SPRWriteResGroup36 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> { 866 let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1]; 867 let Latency = 18; 868 let NumMicroOps = 26; 869} 870def : InstRW<[SPRWriteResGroup36], (instrs CPUID)>; 871 872def SPRWriteResGroup37 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 873 let Latency = 12; 874 let NumMicroOps = 3; 875} 876def : InstRW<[SPRWriteResGroup37], (instregex "^(V?)CVT(T?)PD2DQrm$", 877 "^VCVT(T?)PD2(U?)DQZ128rm((b|k|bk|kz)?)$", 878 "^VCVT(T?)PD2(U?)DQZ128rmbkz$", 879 "^VCVTPH2PSXZ128rm(b?)$", 880 "^VCVT(U?)QQ2PSZ128rm((b|k|bk|kz)?)$", 881 "^VCVT(U?)QQ2PSZ128rmbkz$")>; 882def : InstRW<[SPRWriteResGroup37], (instrs CVTSI642SSrm)>; 883def : InstRW<[SPRWriteResGroup37, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$", 884 "^VCVT(U?)SI642SSZrm((_Int)?)$")>; 885def : InstRW<[SPRWriteResGroup37, ReadAfterVecLd], (instrs VCVTSI642SSrm)>; 886 887def SPRWriteResGroup38 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_10]> { 888 let Latency = 26; 889 let NumMicroOps = 3; 890} 891def : InstRW<[SPRWriteResGroup38], (instregex "^(V?)CVT(T?)SD2SIrm((_Int)?)$")>; 892def : InstRW<[SPRWriteResGroup38, ReadAfterVecLd], (instregex "^VCVT(T?)SD2SIZrm$", 893 "^VCVT(T?)SD2(U?)SIZrm_Int$")>; 894def : InstRW<[SPRWriteResGroup38, ReadAfterVecLd], (instrs VCVTTSD2USIZrm)>; 895 896def SPRWriteResGroup39 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 897 let Latency = 7; 898 let NumMicroOps = 2; 899} 900def : InstRW<[SPRWriteResGroup39], (instregex "^VCVT(T?)PS2(U?)QQZ256rr((k|kz)?)$", 901 "^VCVT(U?)QQ2PSZ256rr((k|kz)?)$")>; 902def : InstRW<[SPRWriteResGroup39, ReadInt2Fpu], (instrs CVTSI2SSrr)>; 903def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI2SSrr_Int$", 904 "^VCVT(U?)SI2SSZrr$", 905 "^VCVT(U?)SI2SSZrr(b?)_Int$")>; 906def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instrs VCVTSI2SSrr)>; 907 908def SPRWriteResGroup40 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 909 let ReleaseAtCycles = [1, 2]; 910 let Latency = 8; 911 let NumMicroOps = 3; 912} 913def : InstRW<[SPRWriteResGroup40, ReadInt2Fpu], (instrs CVTSI642SSrr)>; 914def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$", 915 "^VCVT(U?)SI642SSZrr$", 916 "^VCVT(U?)SI642SSZrr(b?)_Int$")>; 917def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>; 918 919def SPRWriteResGroup41 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort05]> { 920 let Latency = 8; 921 let NumMicroOps = 3; 922} 923def : InstRW<[SPRWriteResGroup41], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$", 924 "^VCVT(T?)SS2SI64Zrr$", 925 "^VCVT(T?)SS2(U?)SI64Zrr(b?)_Int$")>; 926def : InstRW<[SPRWriteResGroup41], (instrs VCVTTSS2USI64Zrr)>; 927def : InstRW<[SPRWriteResGroup41, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>; 928 929def SPRWriteResGroup42 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 930 let Latency = 2; 931 let NumMicroOps = 2; 932} 933def : InstRW<[SPRWriteResGroup42], (instregex "^J(E|R)CXZ$")>; 934def : InstRW<[SPRWriteResGroup42], (instrs CWD)>; 935 936def SPRWriteResGroup43 : SchedWriteRes<[SPRPort00_01_05_06]>; 937def : InstRW<[SPRWriteResGroup43], (instregex "^(LD|ST)_Frr$", 938 "^MOV16s(m|r)$", 939 "^MOV(32|64)sr$")>; 940def : InstRW<[SPRWriteResGroup43], (instrs DEC16r_alt, 941 SALC, 942 ST_FPrr, 943 SYSCALL)>; 944 945def SPRWriteResGroup44 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 946 let Latency = 7; 947} 948def : InstRW<[SPRWriteResGroup44], (instrs DEC32r_alt)>; 949 950def SPRWriteResGroup45 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 951 let Latency = 27; 952 let NumMicroOps = 2; 953} 954def : InstRW<[SPRWriteResGroup45], (instregex "^DIVR_F(32|64)m$")>; 955 956def SPRWriteResGroup46 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 957 let Latency = 30; 958 let NumMicroOps = 3; 959} 960def : InstRW<[SPRWriteResGroup46], (instregex "^DIVR_FI(16|32)m$")>; 961 962def SPRWriteResGroup47 : SchedWriteRes<[SPRPort00]> { 963 let Latency = 15; 964} 965def : InstRW<[SPRWriteResGroup47], (instregex "^DIVR_F(P?)rST0$")>; 966def : InstRW<[SPRWriteResGroup47], (instrs DIVR_FST0r)>; 967 968def SPRWriteResGroup48 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 969 let Latency = 19; 970 let NumMicroOps = 2; 971} 972def : InstRW<[SPRWriteResGroup48, ReadAfterVecLd], (instregex "^(V?)DIVSDrm$")>; 973def : InstRW<[SPRWriteResGroup48, ReadAfterVecLd], (instrs VDIVSDZrm)>; 974 975def SPRWriteResGroup49 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 976 let Latency = 22; 977 let NumMicroOps = 2; 978} 979def : InstRW<[SPRWriteResGroup49], (instregex "^DIV_F(32|64)m$")>; 980def : InstRW<[SPRWriteResGroup49, ReadAfterVecLd], (instregex "^VSQRTSHZm((k|kz)?)_Int$")>; 981def : InstRW<[SPRWriteResGroup49, ReadAfterVecLd], (instrs VSQRTSHZm)>; 982 983def SPRWriteResGroup50 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 984 let Latency = 25; 985 let NumMicroOps = 3; 986} 987def : InstRW<[SPRWriteResGroup50], (instregex "^DIV_FI(16|32)m$")>; 988 989def SPRWriteResGroup51 : SchedWriteRes<[SPRPort00]> { 990 let Latency = 20; 991} 992def : InstRW<[SPRWriteResGroup51], (instregex "^DIV_F(P?)rST0$")>; 993def : InstRW<[SPRWriteResGroup51], (instrs DIV_FST0r)>; 994 995def SPRWriteResGroup52 : SchedWriteRes<[SPRPort04, SPRPort04_09]>; 996def : InstRW<[SPRWriteResGroup52], (instregex "^ENQCMD(S?)(16|32|64)$", 997 "^PUSHA(16|32)$", 998 "^ST_F(32|64)m$")>; 999def : InstRW<[SPRWriteResGroup52], (instrs PUSHF32)>; 1000 1001def SPRWriteResGroup53 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1002 let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5]; 1003 let Latency = 126; 1004 let NumMicroOps = 57; 1005} 1006def : InstRW<[SPRWriteResGroup53], (instrs ENTER)>; 1007 1008def SPRWriteResGroup54 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> { 1009 let Latency = 12; 1010 let NumMicroOps = 3; 1011} 1012def : InstRW<[SPRWriteResGroup54], (instregex "^(V?)EXTRACTPSmri$", 1013 "^VPMOVQDZ((256)?)mr$")>; 1014def : InstRW<[SPRWriteResGroup54], (instrs SMSW16m, 1015 VEXTRACTPSZmri)>; 1016 1017def SPRWriteResGroup55 : SchedWriteRes<[SPRPort00, SPRPort05]> { 1018 let Latency = 4; 1019 let NumMicroOps = 2; 1020} 1021def : InstRW<[SPRWriteResGroup55], (instregex "^(V?)EXTRACTPSrri$")>; 1022def : InstRW<[SPRWriteResGroup55], (instrs MMX_PEXTRWrri, 1023 VEXTRACTPSZrri, 1024 VPERMWZrr)>; 1025 1026def SPRWriteResGroup56 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_10, SPRPort04, SPRPort04_09, SPRPort06]> { 1027 let Latency = 7; 1028 let NumMicroOps = 5; 1029} 1030def : InstRW<[SPRWriteResGroup56], (instrs FARCALL64m)>; 1031 1032def SPRWriteResGroup57 : SchedWriteRes<[SPRPort02_03_10, SPRPort06]> { 1033 let Latency = 6; 1034 let NumMicroOps = 2; 1035} 1036def : InstRW<[SPRWriteResGroup57], (instrs FARJMP64m, 1037 JMP64m_REX)>; 1038 1039def SPRWriteResGroup58 : SchedWriteRes<[SPRPort04, SPRPort04_09]> { 1040 let NumMicroOps = 2; 1041} 1042def : InstRW<[SPRWriteResGroup58], (instregex "^(V?)MASKMOVDQU((64)?)$", 1043 "^ST_FP(32|64|80)m$")>; 1044def : InstRW<[SPRWriteResGroup58], (instrs FBSTPm, 1045 VMPTRSTm)>; 1046 1047def SPRWriteResGroup59 : SchedWriteRes<[SPRPort00_05]> { 1048 let ReleaseAtCycles = [2]; 1049 let Latency = 2; 1050 let NumMicroOps = 2; 1051} 1052def : InstRW<[SPRWriteResGroup59], (instrs FDECSTP)>; 1053 1054def SPRWriteResGroup60 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 1055 let ReleaseAtCycles = [1, 2]; 1056 let Latency = 11; 1057 let NumMicroOps = 3; 1058} 1059def : InstRW<[SPRWriteResGroup60], (instregex "^FICOM(P?)(16|32)m$")>; 1060def : InstRW<[SPRWriteResGroup60, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z((256)?)rm((k|kz)?)$", 1061 "^VPEXPAND(B|D|Q|W)Z((256)?)rm$", 1062 "^VPEXPAND(D|Q)Z((256)?)rmk(z?)$")>; 1063 1064def SPRWriteResGroup61 : SchedWriteRes<[SPRPort00_05]>; 1065def : InstRW<[SPRWriteResGroup61], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$", 1066 "^VP(ADD|SUB)(B|D|Q|W)Zrr$", 1067 "^VP(ADD|SUB)(D|Q)Zrrk(z?)$", 1068 "^VPTERNLOG(D|Q)Zrri((k|kz)?)$")>; 1069def : InstRW<[SPRWriteResGroup61], (instrs FINCSTP, 1070 FNOP)>; 1071 1072def SPRWriteResGroup62 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> { 1073 let Latency = 7; 1074 let NumMicroOps = 3; 1075} 1076def : InstRW<[SPRWriteResGroup62], (instrs FLDCW16m)>; 1077 1078def SPRWriteResGroup63 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03, SPRPort02_03_10]> { 1079 let ReleaseAtCycles = [2, 5, 10, 39, 8]; 1080 let Latency = 62; 1081 let NumMicroOps = 64; 1082} 1083def : InstRW<[SPRWriteResGroup63], (instrs FLDENVm)>; 1084 1085def SPRWriteResGroup64 : SchedWriteRes<[SPRPort00_01_05_06]> { 1086 let ReleaseAtCycles = [4]; 1087 let Latency = 4; 1088 let NumMicroOps = 4; 1089} 1090def : InstRW<[SPRWriteResGroup64], (instrs FNCLEX)>; 1091 1092def SPRWriteResGroup65 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_05, SPRPort05]> { 1093 let ReleaseAtCycles = [6, 3, 6]; 1094 let Latency = 75; 1095 let NumMicroOps = 15; 1096} 1097def : InstRW<[SPRWriteResGroup65], (instrs FNINIT)>; 1098 1099def SPRWriteResGroup66 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort06]> { 1100 let Latency = 2; 1101 let NumMicroOps = 3; 1102} 1103def : InstRW<[SPRWriteResGroup66], (instrs FNSTCW16m)>; 1104 1105def SPRWriteResGroup67 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06]> { 1106 let Latency = 3; 1107 let NumMicroOps = 2; 1108} 1109def : InstRW<[SPRWriteResGroup67], (instrs FNSTSW16r)>; 1110 1111def SPRWriteResGroup68 : SchedWriteRes<[SPRPort00, SPRPort04, SPRPort04_09]> { 1112 let Latency = 3; 1113 let NumMicroOps = 3; 1114} 1115def : InstRW<[SPRWriteResGroup68], (instrs FNSTSWm)>; 1116 1117def SPRWriteResGroup69 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_06, SPRPort01, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> { 1118 let ReleaseAtCycles = [9, 11, 21, 1, 30, 11, 16, 1]; 1119 let Latency = 106; 1120 let NumMicroOps = 100; 1121} 1122def : InstRW<[SPRWriteResGroup69], (instrs FSTENVm)>; 1123 1124def SPRWriteResGroup70 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_10, SPRPort06]> { 1125 let ReleaseAtCycles = [4, 1, 2, 1, 47, 33, 2]; 1126 let Latency = 63; 1127 let NumMicroOps = 90; 1128} 1129def : InstRW<[SPRWriteResGroup70], (instrs FXRSTOR)>; 1130 1131def SPRWriteResGroup71 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_10, SPRPort06]> { 1132 let ReleaseAtCycles = [4, 1, 2, 1, 45, 31, 4]; 1133 let Latency = 63; 1134 let NumMicroOps = 88; 1135} 1136def : InstRW<[SPRWriteResGroup71], (instrs FXRSTOR64)>; 1137 1138def SPRWriteResGroup72 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1139 let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38]; 1140 let Latency = SapphireRapidsModel.MaxLatency; 1141 let NumMicroOps = 110; 1142} 1143def : InstRW<[SPRWriteResGroup72], (instregex "^FXSAVE((64)?)$")>; 1144 1145def SPRWriteResGroup73 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 1146 let Latency = 12; 1147 let NumMicroOps = 2; 1148} 1149def : InstRW<[SPRWriteResGroup73], (instregex "^VPLZCNT(D|Q)Z256rm((b|k|bk|kz)?)$", 1150 "^VPLZCNT(D|Q)Z256rmbkz$")>; 1151def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$", 1152 "^(V?)GF2P8MULBrm$", 1153 "^V(ADD|SUB)PHZ128rm((b|k|bk|kz)?)$", 1154 "^V(ADD|SUB)PHZ128rmbkz$", 1155 "^VGETEXPPHZ128m((b|k|bk|kz)?)$", 1156 "^VGETEXPSHZm((k|kz)?)$", 1157 "^VGETMANTPHZ128rm(bi|ik)$", 1158 "^VGETMANTPHZ128rmbik(z?)$", 1159 "^VGETMANTPHZ128rmi((kz)?)$", 1160 "^VGETMANTSHZrmi((k|kz)?)$", 1161 "^VGF2P8AFFINE((INV)?)QBZ128rm(b?)i$", 1162 "^VM(AX|IN)CPHZ128rm((b|k|bk|kz)?)$", 1163 "^VM(AX|IN)CPHZ128rmbkz$", 1164 "^VM(AX|IN|UL)PHZ128rm((b|k|bk|kz)?)$", 1165 "^VM(AX|IN|UL)PHZ128rmbkz$")>; 1166def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd], (instrs VGETEXPPHZ128mbkz, 1167 VGF2P8MULBZ128rm)>; 1168def : InstRW<[SPRWriteResGroup73, ReadAfterVecLd], (instregex "^V(ADD|SUB)SHZrm$", 1169 "^V(ADD|SUB)SHZrm((k|kz)?)_Int$", 1170 "^VCVTSH2SSZrm((_Int)?)$", 1171 "^VM(AX|IN)CSHZrm$", 1172 "^VM(AX|IN|UL)SHZrm$", 1173 "^VM(AX|IN|UL)SHZrm((k|kz)?)_Int$")>; 1174def : InstRW<[SPRWriteResGroup73, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$", 1175 "^VGF2P8AFFINE((INV)?)QBZ256rm(b?)i$", 1176 "^VGF2P8MULB(Y|Z256)rm$")>; 1177def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd, ReadAfterVecXLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)PHZ128m((b|k|bk|kz)?)$", 1178 "^VF(N?)M(ADD|SUB)(132|213|231)PHZ128mbkz$", 1179 "^VFMADDSUB(132|213|231)PHZ128m((b|k|bk|kz)?)$", 1180 "^VFMADDSUB(132|213|231)PHZ128mbkz$", 1181 "^VFMSUBADD(132|213|231)PHZ128m((b|k|bk|kz)?)$", 1182 "^VFMSUBADD(132|213|231)PHZ128mbkz$")>; 1183def : InstRW<[SPRWriteResGroup73, ReadAfterVecLd, ReadAfterVecLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)SHZm$", 1184 "^VF(N?)M(ADD|SUB)(132|213|231)SHZm((k|kz)?)_Int$")>; 1185def : InstRW<[SPRWriteResGroup73, ReadAfterVecYLd, ReadAfterVecYLd], (instregex "^VPMADD52(H|L)UQZ256m((b|k|bk|kz)?)$", 1186 "^VPMADD52(H|L)UQZ256mbkz$")>; 1187 1188def SPRWriteResGroup74 : SchedWriteRes<[SPRPort00_01]> { 1189 let Latency = 5; 1190} 1191def : InstRW<[SPRWriteResGroup74], (instregex "^(V?)GF2P8MULBrr$", 1192 "^V(ADD|SUB)PHZ(128|256)rr$", 1193 "^V(ADD|SUB)SHZrr$", 1194 "^V(ADD|SUB)SHZrr(b?)_Int$", 1195 "^VCVT(T?)PH2(U?)WZ(128|256)rr$", 1196 "^VCVTSH2SSZrr(b?)_Int$", 1197 "^VCVT(U?)W2PHZ(128|256)rr$", 1198 "^VF(N?)M(ADD|SUB)(132|213|231)PHZ(128|256)r$", 1199 "^VF(N?)M(ADD|SUB)(132|213|231)SHZr(b?)((_Int)?)$", 1200 "^VFMADDSUB(132|213|231)PHZ(128|256)r$", 1201 "^VFMSUBADD(132|213|231)PHZ(128|256)r$", 1202 "^VGETEXPPHZ(128|256)r$", 1203 "^VGETEXPSHZr(b?)$", 1204 "^VGETMANTPHZ(128|256)rri$", 1205 "^VGETMANTSHZrri(b?)$", 1206 "^VGF2P8MULBZ(128|256)rr$", 1207 "^VM(AX|IN)CPHZ(128|256)rr$", 1208 "^VM(AX|IN)CSHZrr$", 1209 "^VM(AX|IN|UL)PHZ(128|256)rr$", 1210 "^VM(AX|IN|UL)SHZrr$", 1211 "^VM(AX|IN|UL)SHZrr(b?)_Int$")>; 1212def : InstRW<[SPRWriteResGroup74], (instrs VCVTSH2SSZrr, 1213 VGF2P8MULBYrr)>; 1214 1215def SPRWriteResGroup75 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> { 1216 let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21]; 1217 let Latency = 35; 1218 let NumMicroOps = 87; 1219} 1220def : InstRW<[SPRWriteResGroup75], (instrs IN16ri)>; 1221 1222def SPRWriteResGroup76 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> { 1223 let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20]; 1224 let Latency = 35; 1225 let NumMicroOps = 87; 1226} 1227def : InstRW<[SPRWriteResGroup76], (instrs IN16rr)>; 1228 1229def SPRWriteResGroup77 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> { 1230 let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20]; 1231 let Latency = 35; 1232 let NumMicroOps = 94; 1233} 1234def : InstRW<[SPRWriteResGroup77], (instrs IN32ri)>; 1235 1236def SPRWriteResGroup78 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> { 1237 let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21]; 1238 let NumMicroOps = 99; 1239} 1240def : InstRW<[SPRWriteResGroup78], (instrs IN32rr)>; 1241 1242def SPRWriteResGroup79 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> { 1243 let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20]; 1244 let Latency = 35; 1245 let NumMicroOps = 87; 1246} 1247def : InstRW<[SPRWriteResGroup79], (instrs IN8ri)>; 1248 1249def SPRWriteResGroup80 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort05]> { 1250 let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20]; 1251 let Latency = 35; 1252 let NumMicroOps = 86; 1253} 1254def : InstRW<[SPRWriteResGroup80], (instrs IN8rr)>; 1255 1256def SPRWriteResGroup81 : SchedWriteRes<[SPRPort00_06]> { 1257 let NumMicroOps = 4; 1258} 1259def : InstRW<[SPRWriteResGroup81], (instrs INC16r_alt)>; 1260 1261def SPRWriteResGroup82 : SchedWriteRes<[SPRPort02_03_10]> { 1262 let Latency = 7; 1263} 1264def : InstRW<[SPRWriteResGroup82], (instregex "^LD_F(32|64|80)m$", 1265 "^(V?)MOV(D|SH|SL)DUPrm$", 1266 "^VBROADCASTSS((Z128)?)rm$", 1267 "^VMOV(D|SH|SL)DUPZ128rm$", 1268 "^VPBROADCAST(D|Q)((Z128)?)rm$")>; 1269def : InstRW<[SPRWriteResGroup82], (instrs INC32r_alt, 1270 VBROADCASTI32X2Z128rm)>; 1271 1272def SPRWriteResGroup83 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1273 let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1]; 1274 let Latency = 20; 1275 let NumMicroOps = 83; 1276} 1277def : InstRW<[SPRWriteResGroup83], (instrs INSB)>; 1278 1279def SPRWriteResGroup84 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1280 let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1]; 1281 let Latency = 20; 1282 let NumMicroOps = 92; 1283} 1284def : InstRW<[SPRWriteResGroup84], (instrs INSL)>; 1285 1286def SPRWriteResGroup85 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1287 let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1]; 1288 let Latency = 20; 1289 let NumMicroOps = 86; 1290} 1291def : InstRW<[SPRWriteResGroup85], (instrs INSW)>; 1292 1293def SPRWriteResGroup86 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1294 let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5]; 1295 let Latency = SapphireRapidsModel.MaxLatency; 1296 let NumMicroOps = 42; 1297} 1298def : InstRW<[SPRWriteResGroup86], (instrs INVLPG)>; 1299 1300def SPRWriteResGroup87 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort05]> { 1301 let Latency = 4; 1302 let NumMicroOps = 3; 1303} 1304def : InstRW<[SPRWriteResGroup87], (instregex "^IST(T?)_FP(16|32|64)m$", 1305 "^IST_F(16|32)m$")>; 1306 1307def SPRWriteResGroup88 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_06]> { 1308 let Latency = 2; 1309 let NumMicroOps = 2; 1310} 1311def : InstRW<[SPRWriteResGroup88], (instrs JCXZ)>; 1312 1313def SPRWriteResGroup89 : SchedWriteRes<[SPRPort06]>; 1314def : InstRW<[SPRWriteResGroup89], (instrs JMP64r_REX)>; 1315 1316def SPRWriteResGroup90 : SchedWriteRes<[]> { 1317 let Latency = 0; 1318 let NumMicroOps = 0; 1319} 1320def : InstRW<[SPRWriteResGroup90], (instregex "^JMP_(1|4)$")>; 1321def : InstRW<[SPRWriteResGroup90], (instrs VZEROUPPER)>; 1322 1323def SPRWriteResGroup91 : SchedWriteRes<[SPRPort05]> { 1324 let Latency = 4; 1325} 1326def : InstRW<[SPRWriteResGroup91], (instregex "^KADD(B|D|Q|W)kk", 1327 "^KSHIFT(LB|RD|RQ|RW)ki$", 1328 "^KSHIFT(LD|RB)ki$", 1329 "^KSHIFTL(Q|W)ki$", 1330 "^KUNPCK(BW|DQ|WD)kk$")>; 1331 1332def SPRWriteResGroup92 : SchedWriteRes<[SPRPort00]>; 1333def : InstRW<[SPRWriteResGroup92], (instregex "^KAND(B|D|Q|W|ND|NQ|NW)kk$", 1334 "^KMOV(B|D|Q|W)kk$", 1335 "^KNOT(B|D|Q|W)kk$", 1336 "^K((X|XN)?)OR(B|D|Q|W)kk$", 1337 "^VP(A|SU)BSBZrr$", 1338 "^VPABS(D|Q|W)Zrr$", 1339 "^VPABS(D|Q)Zrrk(z?)$", 1340 "^VPADD(U?)S(B|W)Zrr$", 1341 "^VPAVG(B|W)Zrr$", 1342 "^VPM(AX|IN)(SB|UD|UW)Zrr$", 1343 "^VPM(AX|IN)(SD|UB)Zrr$", 1344 "^VPM(AX|IN)(S|U)DZrrk(z?)$", 1345 "^VPM(AX|IN)SWZrr$", 1346 "^VPSH(L|R)D(D|Q|W)Zrri$", 1347 "^VPSH(L|R)DV(D|Q|W)Zr$", 1348 "^VPSH(L|R)DV(D|Q)Zrk(z?)$", 1349 "^VPSUB(U?)SWZrr$")>; 1350def : InstRW<[SPRWriteResGroup92], (instrs KANDNBkk, 1351 VPSUBUSBZrr)>; 1352 1353def SPRWriteResGroup93 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 1354 let Latency = 7; 1355 let NumMicroOps = 2; 1356} 1357def : InstRW<[SPRWriteResGroup93], (instregex "^KMOV(B|D|Q|W)km$")>; 1358 1359def SPRWriteResGroup94 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1360 let Latency = 13; 1361 let NumMicroOps = 2; 1362} 1363def : InstRW<[SPRWriteResGroup94], (instregex "^MOV8m(i|r)$")>; 1364def : InstRW<[SPRWriteResGroup94], (instrs KMOVBmk, 1365 MOV8mr_NOREX)>; 1366 1367def SPRWriteResGroup95 : SchedWriteRes<[SPRPort05]>; 1368def : InstRW<[SPRWriteResGroup95], (instregex "^(V?)PALIGNRrri$", 1369 "^VALIGN(D|Q)Z128rri((k|kz)?)$", 1370 "^VBROADCASTSSZ128rr((k|kz)?)$", 1371 "^VPALIGNR(Y|Z)rri$", 1372 "^VPALIGNRZ(128|256)rri$", 1373 "^VPBROADCAST(B|D|Q|W)rr$", 1374 "^VPSHUF(D|HW|LW)Zri$", 1375 "^VPSHUFDZrik(z?)$", 1376 "^VPS(L|R)LDQZri$", 1377 "^VPUNPCK(H|L)(BW|WD)Zrr$", 1378 "^VPUNPCK(H|L|LQ)DQZrr((k|kz)?)$", 1379 "^VPUNPCKHQDQZrr((k|kz)?)$")>; 1380def : InstRW<[SPRWriteResGroup95], (instrs KMOVQkr, 1381 VPSHUFBZrr)>; 1382 1383def SPRWriteResGroup96 : SchedWriteRes<[SPRPort00]> { 1384 let Latency = 3; 1385} 1386def : InstRW<[SPRWriteResGroup96], (instregex "^K((OR)?)TEST(B|D|Q|W)kk$", 1387 "^VP(A|SU)BS(B|W)Zrrk(z?)$", 1388 "^VPADD(U?)S(B|W)Zrrk(z?)$", 1389 "^VPAVG(B|W)Zrrk(z?)$", 1390 "^VPM(AX|IN)(SB|UW)Zrrk(z?)$", 1391 "^VPM(AX|IN)(SW|UB)Zrrk(z?)$", 1392 "^VPSH(L|R)DVWZrk(z?)$", 1393 "^VPS(L|R)LVWZrrk(z?)$", 1394 "^VPS(L|R)LWZrik(z?)$", 1395 "^VPSRAVWZrrk(z?)$", 1396 "^VPSRAWZrik(z?)$", 1397 "^VPSUBUS(B|W)Zrrk(z?)$")>; 1398def : InstRW<[SPRWriteResGroup96], (instrs VMOVSDto64Zrr)>; 1399 1400def SPRWriteResGroup97 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 1401 let ReleaseAtCycles = [8, 2, 14, 3, 1]; 1402 let Latency = 198; 1403 let NumMicroOps = 81; 1404} 1405def : InstRW<[SPRWriteResGroup97], (instrs LAR16rm)>; 1406 1407def SPRWriteResGroup98 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 1408 let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1]; 1409 let Latency = 66; 1410 let NumMicroOps = 22; 1411} 1412def : InstRW<[SPRWriteResGroup98], (instrs LAR16rr)>; 1413 1414def SPRWriteResGroup99 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 1415 let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1]; 1416 let Latency = 71; 1417 let NumMicroOps = 85; 1418} 1419def : InstRW<[SPRWriteResGroup99], (instrs LAR32rm)>; 1420 1421def SPRWriteResGroup100 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 1422 let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1]; 1423 let Latency = 65; 1424 let NumMicroOps = 22; 1425} 1426def : InstRW<[SPRWriteResGroup100], (instregex "^LAR(32|64)rr$")>; 1427 1428def SPRWriteResGroup101 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 1429 let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1]; 1430 let Latency = 71; 1431 let NumMicroOps = 87; 1432} 1433def : InstRW<[SPRWriteResGroup101], (instrs LAR64rm)>; 1434 1435def SPRWriteResGroup102 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> { 1436 let Latency = 2; 1437 let NumMicroOps = 2; 1438} 1439def : InstRW<[SPRWriteResGroup102], (instrs LEA16r)>; 1440 1441def SPRWriteResGroup103 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 1442 let ReleaseAtCycles = [3, 1]; 1443 let Latency = 6; 1444 let NumMicroOps = 4; 1445} 1446def : InstRW<[SPRWriteResGroup103], (instregex "^LODS(B|W)$", 1447 "^SCAS(B|L|Q|W)$")>; 1448def : InstRW<[SPRWriteResGroup103], (instrs LEAVE)>; 1449 1450def SPRWriteResGroup104 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 1451 let ReleaseAtCycles = [2, 1]; 1452 let Latency = 6; 1453 let NumMicroOps = 3; 1454} 1455def : InstRW<[SPRWriteResGroup104], (instrs LEAVE64)>; 1456 1457def SPRWriteResGroup105 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1458 let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1]; 1459 let Latency = SapphireRapidsModel.MaxLatency; 1460 let NumMicroOps = 14; 1461} 1462def : InstRW<[SPRWriteResGroup105], (instrs LGDT64m)>; 1463 1464def SPRWriteResGroup106 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1465 let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1]; 1466 let Latency = SapphireRapidsModel.MaxLatency; 1467 let NumMicroOps = 14; 1468} 1469def : InstRW<[SPRWriteResGroup106], (instrs LIDT64m)>; 1470 1471def SPRWriteResGroup107 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1472 let ReleaseAtCycles = [5, 3, 2, 1, 1]; 1473 let Latency = SapphireRapidsModel.MaxLatency; 1474 let NumMicroOps = 12; 1475} 1476def : InstRW<[SPRWriteResGroup107], (instrs LLDT16m)>; 1477 1478def SPRWriteResGroup108 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1479 let ReleaseAtCycles = [1, 4, 3, 1, 1, 1]; 1480 let Latency = SapphireRapidsModel.MaxLatency; 1481 let NumMicroOps = 11; 1482} 1483def : InstRW<[SPRWriteResGroup108], (instrs LLDT16r)>; 1484 1485def SPRWriteResGroup109 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1486 let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2]; 1487 let Latency = SapphireRapidsModel.MaxLatency; 1488 let NumMicroOps = 27; 1489} 1490def : InstRW<[SPRWriteResGroup109], (instrs LMSW16m)>; 1491 1492def SPRWriteResGroup110 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1493 let ReleaseAtCycles = [5, 7, 1, 2, 5, 2]; 1494 let Latency = SapphireRapidsModel.MaxLatency; 1495 let NumMicroOps = 22; 1496} 1497def : InstRW<[SPRWriteResGroup110], (instrs LMSW16r)>; 1498 1499def SPRWriteResGroup111 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 1500 let ReleaseAtCycles = [2, 1]; 1501 let Latency = 5; 1502 let NumMicroOps = 3; 1503} 1504def : InstRW<[SPRWriteResGroup111], (instregex "^LODS(L|Q)$")>; 1505 1506def SPRWriteResGroup112 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 1507 let ReleaseAtCycles = [2, 4, 1]; 1508 let Latency = 3; 1509 let NumMicroOps = 7; 1510} 1511def : InstRW<[SPRWriteResGroup112], (instrs LOOP)>; 1512 1513def SPRWriteResGroup113 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 1514 let ReleaseAtCycles = [4, 6, 1]; 1515 let Latency = 3; 1516 let NumMicroOps = 11; 1517} 1518def : InstRW<[SPRWriteResGroup113], (instrs LOOPE)>; 1519 1520def SPRWriteResGroup114 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 1521 let ReleaseAtCycles = [4, 6, 1]; 1522 let Latency = 2; 1523 let NumMicroOps = 11; 1524} 1525def : InstRW<[SPRWriteResGroup114], (instrs LOOPNE)>; 1526 1527def SPRWriteResGroup115 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_10, SPRPort06]> { 1528 let Latency = 7; 1529 let NumMicroOps = 3; 1530} 1531def : InstRW<[SPRWriteResGroup115], (instrs LRET64)>; 1532 1533def SPRWriteResGroup116 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 1534 let ReleaseAtCycles = [1, 5, 3, 3, 1]; 1535 let Latency = 70; 1536 let NumMicroOps = 13; 1537} 1538def : InstRW<[SPRWriteResGroup116], (instregex "^LSL(16|32|64)rm$")>; 1539 1540def SPRWriteResGroup117 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 1541 let ReleaseAtCycles = [1, 4, 4, 3, 2, 1]; 1542 let Latency = 63; 1543 let NumMicroOps = 15; 1544} 1545def : InstRW<[SPRWriteResGroup117], (instregex "^LSL(16|32|64)rr$")>; 1546 1547def SPRWriteResGroup118 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 1548 let Latency = 24; 1549 let NumMicroOps = 3; 1550} 1551def : InstRW<[SPRWriteResGroup118], (instregex "^MMX_CVT(T?)PD2PIrm$")>; 1552 1553def SPRWriteResGroup119 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 1554 let Latency = 8; 1555 let NumMicroOps = 2; 1556} 1557def : InstRW<[SPRWriteResGroup119], (instregex "^MMX_CVT(T?)PD2PIrr$", 1558 "^VCVT(T?)PH2(U?)DQZ(128|256)rr$", 1559 "^VCVTP(H2PS|S2PH)XZ256rr$")>; 1560 1561def SPRWriteResGroup120 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 1562 let Latency = 6; 1563 let NumMicroOps = 2; 1564} 1565def : InstRW<[SPRWriteResGroup120], (instregex "^VCVTP(H2PS|S2PH)XZ128rr$", 1566 "^VPERMWZ(128|256)rrk(z?)$", 1567 "^VPS(L|R)LWZ256rrk(z?)$", 1568 "^VPSRAWZ256rrk(z?)$")>; 1569def : InstRW<[SPRWriteResGroup120], (instrs MMX_CVTPI2PDrr)>; 1570 1571def SPRWriteResGroup121 : SchedWriteRes<[SPRPort00, SPRPort00_01]> { 1572 let Latency = 7; 1573 let NumMicroOps = 2; 1574} 1575def : InstRW<[SPRWriteResGroup121], (instrs MMX_CVTPI2PSrr)>; 1576 1577def SPRWriteResGroup122 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 1578 let Latency = 13; 1579 let NumMicroOps = 2; 1580} 1581def : InstRW<[SPRWriteResGroup122], (instregex "^MMX_CVT(T?)PS2PIrm$")>; 1582 1583def SPRWriteResGroup123 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 1584 let Latency = 9; 1585 let NumMicroOps = 2; 1586} 1587def : InstRW<[SPRWriteResGroup123], (instregex "^MMX_CVT(T?)PS2PIrr$")>; 1588 1589def SPRWriteResGroup124 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> { 1590 let ReleaseAtCycles = [2, 1, 1]; 1591 let Latency = 12; 1592 let NumMicroOps = 4; 1593} 1594def : InstRW<[SPRWriteResGroup124], (instregex "^MMX_MASKMOVQ((64)?)$")>; 1595 1596def SPRWriteResGroup125 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1597 let Latency = 18; 1598 let NumMicroOps = 2; 1599} 1600def : InstRW<[SPRWriteResGroup125], (instregex "^VMOV(W|SHZ)mr$")>; 1601def : InstRW<[SPRWriteResGroup125], (instrs MMX_MOVD64mr)>; 1602 1603def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_10]> { 1604 let Latency = 8; 1605} 1606def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$", 1607 "^VBROADCAST(F|I)128rm$", 1608 "^VBROADCAST(F|I)32X(2|4)Z256rm$", 1609 "^VBROADCAST(F|I)32X(8|2)Zrm$", 1610 "^VBROADCAST(F|I)(32|64)X4Zrm$", 1611 "^VBROADCAST(F|I)64X2(Z|Z256)rm$", 1612 "^VBROADCASTS(DY|SZ)rm$", 1613 "^VBROADCASTS(D|S)Z256rm$", 1614 "^VBROADCASTS(DZ|SY)rm$", 1615 "^VMOV(D|SH|SL)DUP(Y|Z)rm$", 1616 "^VMOV(D|SH|SL)DUPZ256rm$", 1617 "^VPBROADCAST(DY|QZ)rm$", 1618 "^VPBROADCAST(D|Q)Z256rm$", 1619 "^VPBROADCAST(DZ|QY)rm$")>; 1620def : InstRW<[SPRWriteResGroup126], (instrs MMX_MOVD64to64rm)>; 1621 1622def SPRWriteResGroup127 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_05]> { 1623 let Latency = 3; 1624 let NumMicroOps = 2; 1625} 1626def : InstRW<[SPRWriteResGroup127], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>; 1627 1628def SPRWriteResGroup128 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 1629 let Latency = 3; 1630 let NumMicroOps = 2; 1631} 1632def : InstRW<[SPRWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>; 1633 1634def SPRWriteResGroup129 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 1635 let ReleaseAtCycles = [1, 2]; 1636 let Latency = 12; 1637 let NumMicroOps = 3; 1638} 1639def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>; 1640def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>; 1641 1642def SPRWriteResGroup130 : SchedWriteRes<[SPRPort05]> { 1643 let ReleaseAtCycles = [2]; 1644 let Latency = 4; 1645 let NumMicroOps = 2; 1646} 1647def : InstRW<[SPRWriteResGroup130], (instregex "^MMX_PACKSS(DW|WB)rr$", 1648 "^VPMOV(D|Q|W|SQ|SW)BZrr$", 1649 "^VPMOV((S|US)?)(D|Q)WZrr$", 1650 "^VPMOV(U?)S(DB|QD)Zrr$", 1651 "^VPMOV(U?)SQDZrrk(z?)$", 1652 "^VPMOVUS(Q|W)BZrr$")>; 1653def : InstRW<[SPRWriteResGroup130], (instrs MMX_PACKUSWBrr)>; 1654def : InstRW<[SPRWriteResGroup130, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrri)>; 1655 1656def SPRWriteResGroup131 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10]> { 1657 let Latency = 9; 1658 let NumMicroOps = 2; 1659} 1660def : InstRW<[SPRWriteResGroup131], (instregex "^VBROADCAST(F|I)32X(8|2)Zrmk(z?)$", 1661 "^VBROADCAST(F|I)(32|64)X4Zrmk(z?)$", 1662 "^VBROADCAST(F|I)64X2Zrmk(z?)$", 1663 "^VBROADCASTS(D|S)Zrmk(z?)$", 1664 "^VMOV(A|U)P(D|S)Zrmk(z?)$", 1665 "^VMOV(D|SH|SL)DUPZrmk(z?)$", 1666 "^VMOVDQ(A|U)(32|64)Zrmk(z?)$", 1667 "^VPBROADCAST(D|Q)Zrmk(z?)$")>; 1668def : InstRW<[SPRWriteResGroup131, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>; 1669def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(32|64)X4Zrmi((k|kz)?)$", 1670 "^VINSERT(F|I)(32X8|64X2)Zrmi((k|kz)?)$", 1671 "^VP(ADD|SUB)(B|D|Q|W)Zrm$", 1672 "^VP(ADD|SUB)(D|Q)Zrm(b|k|kz)$", 1673 "^VP(ADD|SUB)(D|Q)Zrmbk(z?)$", 1674 "^VPTERNLOG(D|Q)Zrm(bi|ik)$", 1675 "^VPTERNLOG(D|Q)Zrmbik(z?)$", 1676 "^VPTERNLOG(D|Q)Zrmi((kz)?)$")>; 1677 1678def SPRWriteResGroup132 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 1679 let ReleaseAtCycles = [1, 1, 2]; 1680 let Latency = 11; 1681 let NumMicroOps = 4; 1682} 1683def : InstRW<[SPRWriteResGroup132, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>; 1684 1685def SPRWriteResGroup133 : SchedWriteRes<[SPRPort00, SPRPort05]> { 1686 let ReleaseAtCycles = [1, 2]; 1687 let Latency = 3; 1688 let NumMicroOps = 3; 1689} 1690def : InstRW<[SPRWriteResGroup133], (instregex "^MMX_PH(ADD|SUB)SWrr$")>; 1691 1692def SPRWriteResGroup134 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 1693 let Latency = 9; 1694 let NumMicroOps = 2; 1695} 1696def : InstRW<[SPRWriteResGroup134], (instregex "^VPBROADCAST(BY|WZ)rm$", 1697 "^VPBROADCAST(B|W)Z256rm$", 1698 "^VPBROADCAST(BZ|WY)rm$")>; 1699def : InstRW<[SPRWriteResGroup134, ReadAfterLd], (instrs MMX_PINSRWrmi)>; 1700def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128mi$")>; 1701def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zmi$")>; 1702def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instregex "^VPALIGNR(Y|Z256)rmi$")>; 1703def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instrs VPSHUFBZrm)>; 1704 1705def SPRWriteResGroup135 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 1706 let Latency = 5; 1707 let NumMicroOps = 2; 1708} 1709def : InstRW<[SPRWriteResGroup135], (instregex "^MOV16ao(16|32|64)$")>; 1710 1711def SPRWriteResGroup136 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> { 1712 let Latency = 12; 1713 let NumMicroOps = 3; 1714} 1715def : InstRW<[SPRWriteResGroup136], (instregex "^PUSH(F|G)S(16|32)$")>; 1716def : InstRW<[SPRWriteResGroup136], (instrs MOV16ms, 1717 MOVBE32mr)>; 1718 1719def SPRWriteResGroup137 : SchedWriteRes<[SPRPort00_01_05_06_11]>; 1720def : InstRW<[SPRWriteResGroup137], (instregex "^MOV(8|16|32|64)ri$", 1721 "^MOV(8|16|32)ri_alt$", 1722 "^MOV(8|16)rr((_REV)?)$")>; 1723def : InstRW<[SPRWriteResGroup137], (instrs MOV64ri32, 1724 MOV8rr_NOREX)>; 1725 1726def SPRWriteResGroup138 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> { 1727 let NumMicroOps = 2; 1728} 1729def : InstRW<[SPRWriteResGroup138], (instregex "^MOV(16|32|64)rs$", 1730 "^S(TR|LDT)16r$")>; 1731 1732def SPRWriteResGroup139 : SchedWriteRes<[SPRPort02_03_10]>; 1733def : InstRW<[SPRWriteResGroup139], (instregex "^MOV32ao(16|32|64)$")>; 1734def : InstRW<[SPRWriteResGroup139], (instrs MOV64ao64)>; 1735 1736def SPRWriteResGroup140 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 1737 let NumMicroOps = 3; 1738} 1739def : InstRW<[SPRWriteResGroup140], (instregex "^MOV(8|32)o(16|32)a$", 1740 "^MOV(8|32|64)o64a$")>; 1741 1742def SPRWriteResGroup141 : SchedWriteRes<[SPRPort00_01_05_06_11]> { 1743 let Latency = 0; 1744} 1745def : InstRW<[SPRWriteResGroup141], (instregex "^MOV32rr((_REV)?)$", 1746 "^MOVZX(32|64)rr8$")>; 1747def : InstRW<[SPRWriteResGroup141], (instrs MOVZX32rr8_NOREX)>; 1748 1749def SPRWriteResGroup142 : SchedWriteRes<[SPRPort02_03_10]> { 1750 let Latency = 5; 1751} 1752def : InstRW<[SPRWriteResGroup142], (instrs MOV64ao32)>; 1753 1754def SPRWriteResGroup143 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1755 let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2]; 1756 let Latency = 217; 1757 let NumMicroOps = 48; 1758} 1759def : InstRW<[SPRWriteResGroup143], (instrs MOV64dr)>; 1760 1761def SPRWriteResGroup144 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1762 let Latency = 12; 1763 let NumMicroOps = 2; 1764} 1765def : InstRW<[SPRWriteResGroup144], (instrs MOV64o32a)>; 1766 1767def SPRWriteResGroup145 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort05]> { 1768 let Latency = SapphireRapidsModel.MaxLatency; 1769 let NumMicroOps = 3; 1770} 1771def : InstRW<[SPRWriteResGroup145], (instrs MOV64rc)>; 1772 1773def SPRWriteResGroup146 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort05]> { 1774 let ReleaseAtCycles = [3, 4, 8, 4, 2, 3]; 1775 let Latency = 181; 1776 let NumMicroOps = 24; 1777} 1778def : InstRW<[SPRWriteResGroup146], (instrs MOV64rd)>; 1779 1780def SPRWriteResGroup147 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 1781 let NumMicroOps = 2; 1782} 1783def : InstRW<[SPRWriteResGroup147], (instregex "^MOV8ao(16|32|64)$")>; 1784 1785def SPRWriteResGroup148 : SchedWriteRes<[SPRPort00_06, SPRPort04_09, SPRPort07_08]> { 1786 let Latency = 12; 1787 let NumMicroOps = 3; 1788} 1789def : InstRW<[SPRWriteResGroup148], (instrs MOVBE16mr)>; 1790 1791def SPRWriteResGroup149 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort02_03_10]> { 1792 let Latency = 7; 1793 let NumMicroOps = 3; 1794} 1795def : InstRW<[SPRWriteResGroup149], (instrs MOVBE16rm)>; 1796 1797def SPRWriteResGroup150 : SchedWriteRes<[SPRPort01, SPRPort02_03_10]> { 1798 let Latency = 6; 1799 let NumMicroOps = 2; 1800} 1801def : InstRW<[SPRWriteResGroup150], (instrs MOVBE32rm)>; 1802 1803def SPRWriteResGroup151 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> { 1804 let Latency = 12; 1805 let NumMicroOps = 4; 1806} 1807def : InstRW<[SPRWriteResGroup151], (instrs MOVBE64mr, 1808 PUSHF16, 1809 SLDT16m, 1810 STRm)>; 1811 1812def SPRWriteResGroup152 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_10]> { 1813 let Latency = 7; 1814 let NumMicroOps = 3; 1815} 1816def : InstRW<[SPRWriteResGroup152], (instrs MOVBE64rm)>; 1817 1818def SPRWriteResGroup153 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1819 let NumMicroOps = 4; 1820} 1821def : InstRW<[SPRWriteResGroup153], (instregex "^MOVDIR64B(16|32|64)$")>; 1822 1823def SPRWriteResGroup154 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1824 let Latency = 511; 1825 let NumMicroOps = 2; 1826} 1827def : InstRW<[SPRWriteResGroup154], (instrs MOVDIRI32)>; 1828 1829def SPRWriteResGroup155 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1830 let Latency = 514; 1831 let NumMicroOps = 2; 1832} 1833def : InstRW<[SPRWriteResGroup155], (instrs MOVDIRI64)>; 1834 1835def SPRWriteResGroup156 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> { 1836 let Latency = 8; 1837 let NumMicroOps = 2; 1838} 1839def : InstRW<[SPRWriteResGroup156, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$", 1840 "^(V?)SHUFP(D|S)rmi$", 1841 "^VMOVLP(D|S)Z128rm$", 1842 "^VSHUFP(D|S)Z128rm(bi|ik)$", 1843 "^VSHUFP(D|S)Z128rmbik(z?)$", 1844 "^VSHUFP(D|S)Z128rmi((kz)?)$")>; 1845 1846def SPRWriteResGroup157 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1847 let Latency = 512; 1848 let NumMicroOps = 2; 1849} 1850def : InstRW<[SPRWriteResGroup157], (instrs MOVNTDQmr)>; 1851 1852def SPRWriteResGroup158 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 1853 let Latency = 518; 1854 let NumMicroOps = 2; 1855} 1856def : InstRW<[SPRWriteResGroup158], (instrs MOVNTImr)>; 1857 1858def SPRWriteResGroup159 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1859 let ReleaseAtCycles = [4, 1, 1, 1]; 1860 let Latency = 8; 1861 let NumMicroOps = 7; 1862} 1863def : InstRW<[SPRWriteResGroup159], (instrs MOVSB)>; 1864 1865def SPRWriteResGroup160 : SchedWriteRes<[SPRPort00_01_05]>; 1866def : InstRW<[SPRWriteResGroup160], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$", 1867 "^(V?)P(ADD|SUB)(B|D|Q|W)rr$", 1868 "^VMOV(A|U)P(D|S)Z(128|256)rrk(z?)((_REV)?)$", 1869 "^VMOVDQ(A|U)(32|64)Z128rrk(z?)((_REV)?)$", 1870 "^VMOVS(D|H|S)Zrr((_REV)?)$", 1871 "^VMOVS(D|S)Zrrk(z?)((_REV)?)$", 1872 "^VP(ADD|SUB)(B|D|Q|W)Yrr$", 1873 "^VP(ADD|SUB)(B|D|Q|W)Z(128|256)rr$", 1874 "^VP(ADD|SUB)(D|Q)Z(128|256)rrk(z?)$", 1875 "^VPMOVM2(D|Q)Z128rk$", 1876 "^VPTERNLOG(D|Q)Z(128|256)rri((k|kz)?)$")>; 1877def : InstRW<[SPRWriteResGroup160], (instrs VPBLENDDrri)>; 1878 1879def SPRWriteResGroup161 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 1880 let ReleaseAtCycles = [4, 1, 1, 1]; 1881 let Latency = 7; 1882 let NumMicroOps = 7; 1883} 1884def : InstRW<[SPRWriteResGroup161], (instregex "^MOVS(L|Q|W)$")>; 1885 1886def SPRWriteResGroup162 : SchedWriteRes<[SPRPort02_03_10]> { 1887 let Latency = 6; 1888} 1889def : InstRW<[SPRWriteResGroup162], (instregex "^MOVSX(16|32|64)rm(16|32)$", 1890 "^MOVSX(32|64)rm8$")>; 1891def : InstRW<[SPRWriteResGroup162], (instrs MOVSX32rm8_NOREX)>; 1892 1893def SPRWriteResGroup163 : SchedWriteRes<[SPRPort01_05_11, SPRPort02_03_10]> { 1894 let Latency = 6; 1895 let NumMicroOps = 2; 1896} 1897def : InstRW<[SPRWriteResGroup163], (instrs MOVSX16rm8)>; 1898 1899def SPRWriteResGroup164 : SchedWriteRes<[SPRPort01_05_11]>; 1900def : InstRW<[SPRWriteResGroup164], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>; 1901def : InstRW<[SPRWriteResGroup164], (instrs MOVSX32rr8_NOREX)>; 1902 1903def SPRWriteResGroup165 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 1904 let Latency = 11; 1905 let NumMicroOps = 2; 1906} 1907def : InstRW<[SPRWriteResGroup165], (instregex "^MUL_F(32|64)m$", 1908 "^VPABS(B|W)Zrmk(z?)$", 1909 "^VPS(L|R)LWZmik(z?)$", 1910 "^VPSRAWZmik(z?)$")>; 1911def : InstRW<[SPRWriteResGroup165, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Zrmk(z?)$", 1912 "^VPAVG(B|W)Zrmk(z?)$", 1913 "^VPM(AX|IN)(SB|UW)Zrmk(z?)$", 1914 "^VPM(AX|IN)(SW|UB)Zrmk(z?)$", 1915 "^VPSH(L|R)DVWZmk(z?)$", 1916 "^VPS(L|R)L(V?)WZrmk(z?)$", 1917 "^VPSRA(V?)WZrmk(z?)$")>; 1918 1919def SPRWriteResGroup166 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 1920 let Latency = 14; 1921 let NumMicroOps = 3; 1922} 1923def : InstRW<[SPRWriteResGroup166], (instregex "^MUL_FI(16|32)m$")>; 1924 1925def SPRWriteResGroup167 : SchedWriteRes<[SPRPort00]> { 1926 let Latency = 4; 1927} 1928def : InstRW<[SPRWriteResGroup167], (instregex "^MUL_F(P?)rST0$", 1929 "^V(U?)COMISHZrr(b?)$", 1930 "^V(U?)COMISHZrr_Int$", 1931 "^VCVT(T?)PD2(U?)QQZrr((b|k|bk|kz)?)$", 1932 "^VCVT(T?)PD2(U?)QQZrrbkz$", 1933 "^VCVT(T?)PS2(U?)DQZrr((b|k|bk|kz)?)$", 1934 "^VCVT(T?)PS2(U?)DQZrrbkz$", 1935 "^VM(AX|IN)(C?)PSZrr((k|kz)?)$", 1936 "^VM(AX|IN)PSZrrb((k|kz)?)$", 1937 "^VPLZCNT(D|Q)Zrr((k|kz)?)$", 1938 "^VPMADD52(H|L)UQZr((k|kz)?)$")>; 1939def : InstRW<[SPRWriteResGroup167], (instrs MUL_FST0r)>; 1940 1941def SPRWriteResGroup168 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort05, SPRPort06]> { 1942 let ReleaseAtCycles = [7, 1, 2]; 1943 let Latency = 20; 1944 let NumMicroOps = 10; 1945} 1946def : InstRW<[SPRWriteResGroup168], (instrs MWAITrr)>; 1947 1948def SPRWriteResGroup169 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1949 let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1]; 1950 let Latency = 35; 1951 let NumMicroOps = 79; 1952} 1953def : InstRW<[SPRWriteResGroup169], (instrs OUT16ir)>; 1954 1955def SPRWriteResGroup170 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1956 let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1]; 1957 let Latency = 35; 1958 let NumMicroOps = 79; 1959} 1960def : InstRW<[SPRWriteResGroup170], (instrs OUT16rr)>; 1961 1962def SPRWriteResGroup171 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1963 let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1]; 1964 let Latency = 35; 1965 let NumMicroOps = 85; 1966} 1967def : InstRW<[SPRWriteResGroup171], (instrs OUT32ir)>; 1968 1969def SPRWriteResGroup172 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1970 let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1]; 1971 let Latency = 35; 1972 let NumMicroOps = 85; 1973} 1974def : InstRW<[SPRWriteResGroup172], (instrs OUT32rr)>; 1975 1976def SPRWriteResGroup173 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1977 let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1]; 1978 let Latency = 35; 1979 let NumMicroOps = 73; 1980} 1981def : InstRW<[SPRWriteResGroup173], (instrs OUT8ir)>; 1982 1983def SPRWriteResGroup174 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1984 let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1]; 1985 let Latency = 35; 1986 let NumMicroOps = 73; 1987} 1988def : InstRW<[SPRWriteResGroup174], (instrs OUT8rr)>; 1989 1990def SPRWriteResGroup175 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1991 let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1]; 1992 let Latency = SapphireRapidsModel.MaxLatency; 1993 let NumMicroOps = 80; 1994} 1995def : InstRW<[SPRWriteResGroup175], (instrs OUTSB)>; 1996 1997def SPRWriteResGroup176 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 1998 let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1]; 1999 let Latency = SapphireRapidsModel.MaxLatency; 2000 let NumMicroOps = 89; 2001} 2002def : InstRW<[SPRWriteResGroup176], (instrs OUTSL)>; 2003 2004def SPRWriteResGroup177 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 2005 let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1]; 2006 let Latency = SapphireRapidsModel.MaxLatency; 2007 let NumMicroOps = 83; 2008} 2009def : InstRW<[SPRWriteResGroup177], (instrs OUTSW)>; 2010 2011def SPRWriteResGroup178 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> { 2012 let Latency = 8; 2013 let NumMicroOps = 2; 2014} 2015def : InstRW<[SPRWriteResGroup178], (instregex "^VBROADCASTI32X2Z128rmk(z?)$", 2016 "^VBROADCASTSSZ128rmk(z?)$", 2017 "^VMOV(A|U)P(D|S)Z128rmk(z?)$", 2018 "^VMOV(D|SH|SL)DUPZ128rmk(z?)$", 2019 "^VMOVDQ(A|U)(32|64)Z128rmk(z?)$", 2020 "^VMOVS(D|S)Zrmk(z?)$", 2021 "^VPBROADCAST(D|Q)Z128rmk(z?)$")>; 2022def : InstRW<[SPRWriteResGroup178, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$", 2023 "^VP(ADD|SUB)(B|D|Q|W)Z128rm$", 2024 "^VP(ADD|SUB)(D|Q)Z128rm(b|k|kz)$", 2025 "^VP(ADD|SUB)(D|Q)Z128rmbk(z?)$", 2026 "^VPTERNLOG(D|Q)Z128rm(bi|ik)$", 2027 "^VPTERNLOG(D|Q)Z128rmbik(z?)$", 2028 "^VPTERNLOG(D|Q)Z128rmi((kz)?)$")>; 2029def : InstRW<[SPRWriteResGroup178, ReadAfterVecXLd], (instrs VPBLENDDrmi)>; 2030 2031def SPRWriteResGroup179 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 2032 let Latency = 8; 2033 let NumMicroOps = 2; 2034} 2035def : InstRW<[SPRWriteResGroup179], (instregex "^VPBROADCAST(B|W)((Z128)?)rm$")>; 2036def : InstRW<[SPRWriteResGroup179, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$", 2037 "^VALIGN(D|Q)Z128rm(bi|ik)$", 2038 "^VALIGN(D|Q)Z128rmbik(z?)$", 2039 "^VALIGN(D|Q)Z128rmi((kz)?)$")>; 2040def : InstRW<[SPRWriteResGroup179, ReadAfterVecXLd], (instrs VPALIGNRZ128rmi)>; 2041 2042def SPRWriteResGroup180 : SchedWriteRes<[SPRPort00_06, SPRPort05]> { 2043 let Latency = 140; 2044 let NumMicroOps = 2; 2045} 2046def : InstRW<[SPRWriteResGroup180], (instrs PAUSE)>; 2047 2048def SPRWriteResGroup181 : SchedWriteRes<[SPRPort01, SPRPort02_03_10]> { 2049 let Latency = 8; 2050 let NumMicroOps = 2; 2051} 2052def : InstRW<[SPRWriteResGroup181, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>; 2053 2054def SPRWriteResGroup182 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort07_08]> { 2055 let Latency = 12; 2056 let NumMicroOps = 3; 2057} 2058def : InstRW<[SPRWriteResGroup182], (instregex "^(V?)PEXTR(D|Q)mri$", 2059 "^VPEXTR(D|Q)Zmri$", 2060 "^VPMOVQDZ128mr(k?)$")>; 2061 2062def SPRWriteResGroup183 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10]> { 2063 let ReleaseAtCycles = [1, 2, 1]; 2064 let Latency = 9; 2065 let NumMicroOps = 4; 2066} 2067def : InstRW<[SPRWriteResGroup183, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>; 2068 2069def SPRWriteResGroup184 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> { 2070 let ReleaseAtCycles = [1, 2]; 2071 let Latency = 2; 2072 let NumMicroOps = 3; 2073} 2074def : InstRW<[SPRWriteResGroup184], (instregex "^(V?)PH(ADD|SUB)SWrr$", 2075 "^VPH(ADD|SUB)SWYrr$")>; 2076 2077def SPRWriteResGroup185 : SchedWriteRes<[SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 2078 let Latency = 12; 2079 let NumMicroOps = 3; 2080} 2081def : InstRW<[SPRWriteResGroup185], (instregex "^POP(16|32|64)rmm$", 2082 "^PUSH(16|32)rmm$")>; 2083 2084def SPRWriteResGroup186 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort02_03_10]> { 2085 let ReleaseAtCycles = [6, 2, 1, 1]; 2086 let Latency = 5; 2087 let NumMicroOps = 10; 2088} 2089def : InstRW<[SPRWriteResGroup186], (instrs POPF16)>; 2090 2091def SPRWriteResGroup187 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_10]> { 2092 let ReleaseAtCycles = [2, 1, 1]; 2093 let Latency = 5; 2094 let NumMicroOps = 7; 2095} 2096def : InstRW<[SPRWriteResGroup187], (instrs POPF64)>; 2097 2098def SPRWriteResGroup188 : SchedWriteRes<[SPRPort02_03_10]> { 2099 let Latency = 0; 2100} 2101def : InstRW<[SPRWriteResGroup188], (instregex "^PREFETCHT(0|1|2)$")>; 2102def : InstRW<[SPRWriteResGroup188], (instrs PREFETCHNTA)>; 2103 2104def SPRWriteResGroup189 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10, SPRPort06]> { 2105 let ReleaseAtCycles = [1, 1, 2]; 2106 let Latency = SapphireRapidsModel.MaxLatency; 2107 let NumMicroOps = 4; 2108} 2109def : InstRW<[SPRWriteResGroup189], (instregex "^PTWRITE((64)?)m$")>; 2110 2111def SPRWriteResGroup190 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort06]> { 2112 let ReleaseAtCycles = [1, 2]; 2113 let Latency = SapphireRapidsModel.MaxLatency; 2114 let NumMicroOps = 3; 2115} 2116def : InstRW<[SPRWriteResGroup190], (instrs PTWRITE64r)>; 2117 2118def SPRWriteResGroup191 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort06]> { 2119 let ReleaseAtCycles = [2, 2]; 2120 let Latency = SapphireRapidsModel.MaxLatency; 2121 let NumMicroOps = 4; 2122} 2123def : InstRW<[SPRWriteResGroup191], (instrs PTWRITEr)>; 2124 2125def SPRWriteResGroup192 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 2126 let NumMicroOps = 2; 2127} 2128def : InstRW<[SPRWriteResGroup192], (instregex "^PUSH64r((mr)?)$")>; 2129 2130def SPRWriteResGroup193 : SchedWriteRes<[SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 2131 let NumMicroOps = 3; 2132} 2133def : InstRW<[SPRWriteResGroup193], (instrs PUSH64rmm)>; 2134 2135def SPRWriteResGroup194 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> { 2136 let Latency = 4; 2137 let NumMicroOps = 4; 2138} 2139def : InstRW<[SPRWriteResGroup194], (instrs PUSHF64)>; 2140 2141def SPRWriteResGroup195 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> { 2142 let NumMicroOps = 3; 2143} 2144def : InstRW<[SPRWriteResGroup195], (instregex "^PUSH(F|G)S64$")>; 2145 2146def SPRWriteResGroup196 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2147 let ReleaseAtCycles = [2, 3, 2]; 2148 let Latency = 8; 2149 let NumMicroOps = 7; 2150} 2151def : InstRW<[SPRWriteResGroup196], (instregex "^RC(L|R)(16|32|64)rCL$")>; 2152 2153def SPRWriteResGroup197 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 2154 let ReleaseAtCycles = [1, 2]; 2155 let Latency = 13; 2156 let NumMicroOps = 3; 2157} 2158def : InstRW<[SPRWriteResGroup197, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>; 2159 2160def SPRWriteResGroup198 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2161 let ReleaseAtCycles = [1, 5, 2]; 2162 let Latency = 20; 2163 let NumMicroOps = 8; 2164} 2165def : InstRW<[SPRWriteResGroup198, WriteRMW], (instrs RCL8mCL)>; 2166 2167def SPRWriteResGroup199 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2168 let ReleaseAtCycles = [2, 5, 2]; 2169 let Latency = 7; 2170 let NumMicroOps = 9; 2171} 2172def : InstRW<[SPRWriteResGroup199], (instrs RCL8rCL)>; 2173 2174def SPRWriteResGroup200 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2175 let ReleaseAtCycles = [2, 4, 3]; 2176 let Latency = 20; 2177 let NumMicroOps = 9; 2178} 2179def : InstRW<[SPRWriteResGroup200, WriteRMW], (instrs RCR8mCL)>; 2180 2181def SPRWriteResGroup201 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2182 let ReleaseAtCycles = [3, 4, 3]; 2183 let Latency = 9; 2184 let NumMicroOps = 10; 2185} 2186def : InstRW<[SPRWriteResGroup201], (instrs RCR8rCL)>; 2187 2188def SPRWriteResGroup202 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort01_05_11, SPRPort05]> { 2189 let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2]; 2190 let Latency = SapphireRapidsModel.MaxLatency; 2191 let NumMicroOps = 54; 2192} 2193def : InstRW<[SPRWriteResGroup202], (instrs RDMSR)>; 2194 2195def SPRWriteResGroup203 : SchedWriteRes<[SPRPort01]> { 2196 let Latency = SapphireRapidsModel.MaxLatency; 2197} 2198def : InstRW<[SPRWriteResGroup203], (instrs RDPID64)>; 2199 2200def SPRWriteResGroup204 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2201 let Latency = SapphireRapidsModel.MaxLatency; 2202 let NumMicroOps = 3; 2203} 2204def : InstRW<[SPRWriteResGroup204], (instrs RDPKRUr)>; 2205 2206def SPRWriteResGroup205 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort05]> { 2207 let ReleaseAtCycles = [9, 6, 2, 1]; 2208 let Latency = SapphireRapidsModel.MaxLatency; 2209 let NumMicroOps = 18; 2210} 2211def : InstRW<[SPRWriteResGroup205], (instrs RDPMC)>; 2212 2213def SPRWriteResGroup206 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2214 let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2]; 2215 let Latency = 1386; 2216 let NumMicroOps = 25; 2217} 2218def : InstRW<[SPRWriteResGroup206], (instrs RDRAND16r)>; 2219 2220def SPRWriteResGroup207 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2221 let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2]; 2222 let Latency = SapphireRapidsModel.MaxLatency; 2223 let NumMicroOps = 25; 2224} 2225def : InstRW<[SPRWriteResGroup207], (instregex "^RDRAND(32|64)r$")>; 2226 2227def SPRWriteResGroup208 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 2228 let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4]; 2229 let Latency = 1381; 2230 let NumMicroOps = 25; 2231} 2232def : InstRW<[SPRWriteResGroup208], (instrs RDSEED16r)>; 2233 2234def SPRWriteResGroup209 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort05]> { 2235 let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4]; 2236 let Latency = SapphireRapidsModel.MaxLatency; 2237 let NumMicroOps = 25; 2238} 2239def : InstRW<[SPRWriteResGroup209], (instregex "^RDSEED(32|64)r$")>; 2240 2241def SPRWriteResGroup210 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort05]> { 2242 let ReleaseAtCycles = [5, 6, 3, 1]; 2243 let Latency = 18; 2244 let NumMicroOps = 15; 2245} 2246def : InstRW<[SPRWriteResGroup210], (instrs RDTSC)>; 2247 2248def SPRWriteResGroup211 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort05]> { 2249 let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3]; 2250 let Latency = 42; 2251 let NumMicroOps = 21; 2252} 2253def : InstRW<[SPRWriteResGroup211], (instrs RDTSCP)>; 2254 2255def SPRWriteResGroup212 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> { 2256 let Latency = 7; 2257 let NumMicroOps = 2; 2258} 2259def : InstRW<[SPRWriteResGroup212], (instrs RET64)>; 2260 2261def SPRWriteResGroup213 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> { 2262 let ReleaseAtCycles = [2, 1]; 2263 let Latency = 6; 2264 let NumMicroOps = 3; 2265} 2266def : InstRW<[SPRWriteResGroup213], (instregex "^RETI(16|32|64)$")>; 2267 2268def SPRWriteResGroup214 : SchedWriteRes<[]>; 2269def : InstRW<[SPRWriteResGroup214], (instrs REX64_PREFIX)>; 2270 2271def SPRWriteResGroup215 : SchedWriteRes<[SPRPort00_06]> { 2272 let ReleaseAtCycles = [2]; 2273 let Latency = 12; 2274 let NumMicroOps = 2; 2275} 2276def : InstRW<[SPRWriteResGroup215, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>; 2277 2278def SPRWriteResGroup216 : SchedWriteRes<[SPRPort00_06]> { 2279 let ReleaseAtCycles = [2]; 2280 let NumMicroOps = 2; 2281} 2282def : InstRW<[SPRWriteResGroup216], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>; 2283 2284def SPRWriteResGroup217 : SchedWriteRes<[SPRPort00_06]> { 2285 let ReleaseAtCycles = [2]; 2286 let Latency = 13; 2287 let NumMicroOps = 2; 2288} 2289def : InstRW<[SPRWriteResGroup217, WriteRMW], (instregex "^RO(L|R)8m(1|i)$", 2290 "^(RO|SH)L8mCL$", 2291 "^(RO|SA|SH)R8mCL$")>; 2292 2293def SPRWriteResGroup218 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 2294 let ReleaseAtCycles = [2, 1]; 2295 let Latency = 15; 2296 let NumMicroOps = 3; 2297} 2298def : InstRW<[SPRWriteResGroup218], (instregex "^(V?)ROUNDP(D|S)mi$")>; 2299def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S)mi((_Int)?)$", 2300 "^VRNDSCALEP(D|S)Z128rm(bi|ik)$", 2301 "^VRNDSCALEP(D|S)Z128rmbik(z?)$", 2302 "^VRNDSCALEP(D|S)Z128rmi((kz)?)$", 2303 "^VRNDSCALES(D|S)Zrmi$", 2304 "^VRNDSCALES(D|S)Zrmi((k|kz)?)_Int$")>; 2305 2306def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> { 2307 let ReleaseAtCycles = [2]; 2308 let Latency = 8; 2309 let NumMicroOps = 2; 2310} 2311def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)ri$", 2312 "^(V?)ROUND(PS|SD)ri$", 2313 "^(V?)ROUNDS(D|S)ri_Int$", 2314 "^VRNDSCALEP(D|S)Z(128|256)rri((k|kz)?)$", 2315 "^VRNDSCALES(D|S)Zrri$", 2316 "^VRNDSCALES(D|S)Zrri(b?)((k|kz)?)_Int$", 2317 "^VROUNDP(D|S)Yri$")>; 2318 2319def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> { 2320 let ReleaseAtCycles = [2]; 2321 let Latency = 4; 2322 let NumMicroOps = 2; 2323} 2324def : InstRW<[SPRWriteResGroup220], (instrs SAHF)>; 2325 2326def SPRWriteResGroup221 : SchedWriteRes<[SPRPort00_06]> { 2327 let Latency = 13; 2328} 2329def : InstRW<[SPRWriteResGroup221, WriteRMW], (instregex "^S(A|H)R8m(1|i)$", 2330 "^SHL8m(1|i)$")>; 2331 2332def SPRWriteResGroup222 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_10]> { 2333 let Latency = 8; 2334 let NumMicroOps = 2; 2335} 2336def : InstRW<[SPRWriteResGroup222, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$", 2337 "^SHLX(32|64)rm$")>; 2338 2339def SPRWriteResGroup223 : SchedWriteRes<[SPRPort00_06]> { 2340 let Latency = 3; 2341} 2342def : InstRW<[SPRWriteResGroup223], (instregex "^S(A|H)RX(32|64)rr$", 2343 "^SHLX(32|64)rr$")>; 2344 2345def SPRWriteResGroup224 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> { 2346 let ReleaseAtCycles = [2, 2, 1, 1, 1]; 2347 let Latency = SapphireRapidsModel.MaxLatency; 2348 let NumMicroOps = 7; 2349} 2350def : InstRW<[SPRWriteResGroup224], (instrs SERIALIZE)>; 2351 2352def SPRWriteResGroup225 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 2353 let Latency = 2; 2354 let NumMicroOps = 2; 2355} 2356def : InstRW<[SPRWriteResGroup225], (instrs SFENCE)>; 2357 2358def SPRWriteResGroup226 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01, SPRPort04_09, SPRPort07_08]> { 2359 let ReleaseAtCycles = [1, 2, 2, 2]; 2360 let Latency = 21; 2361 let NumMicroOps = 7; 2362} 2363def : InstRW<[SPRWriteResGroup226], (instregex "^S(G|I)DT64m$")>; 2364 2365def SPRWriteResGroup227 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 2366 let Latency = 9; 2367 let NumMicroOps = 3; 2368} 2369def : InstRW<[SPRWriteResGroup227, ReadAfterVecXLd], (instrs SHA1MSG1rm)>; 2370 2371def SPRWriteResGroup228 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> { 2372 let Latency = 2; 2373 let NumMicroOps = 2; 2374} 2375def : InstRW<[SPRWriteResGroup228], (instrs SHA1MSG1rr)>; 2376 2377def SPRWriteResGroup229 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort02_03_10]> { 2378 let ReleaseAtCycles = [2, 2, 1, 2, 1]; 2379 let Latency = 13; 2380 let NumMicroOps = 8; 2381} 2382def : InstRW<[SPRWriteResGroup229, ReadAfterVecXLd], (instrs SHA1MSG2rm)>; 2383 2384def SPRWriteResGroup230 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05]> { 2385 let ReleaseAtCycles = [2, 2, 1, 2]; 2386 let Latency = 6; 2387 let NumMicroOps = 7; 2388} 2389def : InstRW<[SPRWriteResGroup230], (instrs SHA1MSG2rr)>; 2390 2391def SPRWriteResGroup231 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> { 2392 let Latency = 8; 2393 let NumMicroOps = 4; 2394} 2395def : InstRW<[SPRWriteResGroup231, ReadAfterVecXLd], (instrs SHA1NEXTErm)>; 2396 2397def SPRWriteResGroup232 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05]> { 2398 let Latency = 3; 2399 let NumMicroOps = 3; 2400} 2401def : InstRW<[SPRWriteResGroup232], (instrs SHA1NEXTErr)>; 2402 2403def SPRWriteResGroup233 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 2404 let Latency = 13; 2405 let NumMicroOps = 2; 2406} 2407def : InstRW<[SPRWriteResGroup233], (instregex "^VPMOV(S|Z)XBWZ((256)?)rmk(z?)$", 2408 "^VPOPCNT(B|W)Z(128|256)rmk(z?)$", 2409 "^VPOPCNT(B|W)Zrmk(z?)$")>; 2410def : InstRW<[SPRWriteResGroup233, ReadAfterVecXLd], (instregex "^VDBPSADBWZ128rmik(z?)$", 2411 "^VPACK(S|U)SDWZ128rm(bk|kz)$", 2412 "^VPACK(S|U)SDWZ128rmbkz$", 2413 "^VPACK(S|U)S(DW|WB)Z128rmk$", 2414 "^VPACK(S|U)SWBZ128rmkz$", 2415 "^VPMULTISHIFTQBZ128rm(bk|kz)$", 2416 "^VPMULTISHIFTQBZ128rm(k|bkz)$")>; 2417def : InstRW<[SPRWriteResGroup233, ReadAfterVecXLd], (instrs SHA1RNDS4rmi, 2418 SHA256RNDS2rm)>; 2419def : InstRW<[SPRWriteResGroup233, ReadAfterVecYLd], (instregex "^VDBPSADBWZ((256)?)rmik(z?)$", 2420 "^VPACK(S|U)SDWZ((256)?)rm(bk|kz)$", 2421 "^VPACK(S|U)SDWZ((256)?)rmbkz$", 2422 "^VPACK(S|U)S(DW|WB)Z((256)?)rmk$", 2423 "^VPACK(S|U)SWBZ((256)?)rmkz$", 2424 "^VPERMBZ(128|256)rmk(z?)$", 2425 "^VPERMBZrmk(z?)$", 2426 "^VPMULTISHIFTQBZ((256)?)rm(bk|kz)$", 2427 "^VPMULTISHIFTQBZ((256)?)rm(k|bkz)$")>; 2428 2429def SPRWriteResGroup234 : SchedWriteRes<[SPRPort05]> { 2430 let Latency = 6; 2431} 2432def : InstRW<[SPRWriteResGroup234], (instrs SHA1RNDS4rri, 2433 SHA256RNDS2rr)>; 2434 2435def SPRWriteResGroup235 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 2436 let ReleaseAtCycles = [3, 2, 1, 1, 1]; 2437 let Latency = 12; 2438 let NumMicroOps = 8; 2439} 2440def : InstRW<[SPRWriteResGroup235, ReadAfterVecXLd], (instrs SHA256MSG1rm)>; 2441 2442def SPRWriteResGroup236 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> { 2443 let ReleaseAtCycles = [3, 2, 1, 1]; 2444 let Latency = 5; 2445 let NumMicroOps = 7; 2446} 2447def : InstRW<[SPRWriteResGroup236], (instrs SHA256MSG1rr)>; 2448 2449def SPRWriteResGroup237 : SchedWriteRes<[SPRPort05]> { 2450 let ReleaseAtCycles = [2]; 2451 let Latency = 6; 2452 let NumMicroOps = 2; 2453} 2454def : InstRW<[SPRWriteResGroup237], (instregex "^VPMOV(D|Q|W|SQ|SW)BZrrk(z?)$", 2455 "^VPMOV((S|US)?)(D|Q)WZrrk(z?)$", 2456 "^VPMOV(U?)SDBZrrk(z?)$", 2457 "^VPMOVUS(Q|W)BZrrk(z?)$")>; 2458def : InstRW<[SPRWriteResGroup237], (instrs SHA256MSG2rr)>; 2459 2460def SPRWriteResGroup238 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort07_08]> { 2461 let Latency = 13; 2462 let NumMicroOps = 5; 2463} 2464def : InstRW<[SPRWriteResGroup238], (instrs SHRD16mri8)>; 2465 2466def SPRWriteResGroup239 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> { 2467 let Latency = 6; 2468 let NumMicroOps = 2; 2469} 2470def : InstRW<[SPRWriteResGroup239], (instregex "^SLDT(32|64)r$")>; 2471 2472def SPRWriteResGroup240 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort05]> { 2473 let NumMicroOps = 2; 2474} 2475def : InstRW<[SPRWriteResGroup240], (instrs SMSW16r)>; 2476 2477def SPRWriteResGroup241 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort05]> { 2478 let Latency = SapphireRapidsModel.MaxLatency; 2479 let NumMicroOps = 2; 2480} 2481def : InstRW<[SPRWriteResGroup241], (instregex "^SMSW(32|64)r$")>; 2482 2483def SPRWriteResGroup242 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 2484 let Latency = 24; 2485 let NumMicroOps = 2; 2486} 2487def : InstRW<[SPRWriteResGroup242, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>; 2488def : InstRW<[SPRWriteResGroup242, ReadAfterVecLd], (instrs VSQRTSDZm_Int)>; 2489 2490def SPRWriteResGroup243 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 2491 let Latency = 6; 2492 let NumMicroOps = 2; 2493} 2494def : InstRW<[SPRWriteResGroup243], (instrs STD)>; 2495 2496def SPRWriteResGroup244 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01]> { 2497 let ReleaseAtCycles = [1, 4, 1]; 2498 let Latency = SapphireRapidsModel.MaxLatency; 2499 let NumMicroOps = 6; 2500} 2501def : InstRW<[SPRWriteResGroup244], (instrs STI)>; 2502 2503def SPRWriteResGroup245 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 2504 let ReleaseAtCycles = [2, 1, 1]; 2505 let Latency = 8; 2506 let NumMicroOps = 4; 2507} 2508def : InstRW<[SPRWriteResGroup245], (instrs STOSB)>; 2509 2510def SPRWriteResGroup246 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 2511 let ReleaseAtCycles = [2, 1, 1]; 2512 let Latency = 7; 2513 let NumMicroOps = 4; 2514} 2515def : InstRW<[SPRWriteResGroup246], (instregex "^STOS(L|Q|W)$")>; 2516 2517def SPRWriteResGroup247 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort01]> { 2518 let Latency = 5; 2519 let NumMicroOps = 2; 2520} 2521def : InstRW<[SPRWriteResGroup247], (instregex "^STR(32|64)r$")>; 2522 2523def SPRWriteResGroup248 : SchedWriteRes<[SPRPort00]> { 2524 let Latency = 2; 2525} 2526def : InstRW<[SPRWriteResGroup248], (instregex "^(TST|XAM)_F$")>; 2527def : InstRW<[SPRWriteResGroup248], (instrs UCOM_FPPr)>; 2528 2529def SPRWriteResGroup249 : SchedWriteRes<[SPRPort01_05]> { 2530 let Latency = 4; 2531} 2532def : InstRW<[SPRWriteResGroup249], (instregex "^V(ADD|SUB)P(D|S)Z(128|256)rrkz$", 2533 "^V(ADD|SUB)S(D|S)Zrr(b?)kz_Int$")>; 2534 2535def SPRWriteResGroup250 : SchedWriteRes<[SPRPort00_05]> { 2536 let Latency = 3; 2537} 2538def : InstRW<[SPRWriteResGroup250], (instregex "^V(ADD|SUB)P(D|S)Zrr(b?)$", 2539 "^VMOVDQU(8|16)Zrrk(z?)((_REV)?)$", 2540 "^VP(ADD|SUB)(B|W)Zrrk(z?)$", 2541 "^VPBLENDM(B|W)Zrrk(z?)$", 2542 "^VPMOVM2(B|W)Zrk$")>; 2543 2544def SPRWriteResGroup251 : SchedWriteRes<[SPRPort00_01]> { 2545 let Latency = 6; 2546} 2547def : InstRW<[SPRWriteResGroup251], (instregex "^V(ADD|SUB)PHZ(128|256)rrk(z?)$", 2548 "^V(ADD|SUB)SHZrr(b?)k(z?)_Int$", 2549 "^VCVT(T?)PH2(U?)WZ(128|256)rrk(z?)$", 2550 "^VCVT(U?)W2PHZ(128|256)rrk(z?)$", 2551 "^VF(N?)M(ADD|SUB)(132|213|231)PHZ(128|256)rk(z?)$", 2552 "^VF(N?)M(ADD|SUB)(132|213|231)SHZr(b?)k(z?)_Int$", 2553 "^VFMADDSUB(132|213|231)PHZ(128|256)rk(z?)$", 2554 "^VFMSUBADD(132|213|231)PHZ(128|256)rk(z?)$", 2555 "^VGETEXPPHZ(128|256)rk(z?)$", 2556 "^VGETEXPSHZr(bk|kz)$", 2557 "^VGETEXPSHZr(k|bkz)$", 2558 "^VGETMANTPHZ(128|256)rrik(z?)$", 2559 "^VGETMANTSHZrri(bk|kz)$", 2560 "^VGETMANTSHZrri(k|bkz)$", 2561 "^VM(AX|IN)CPHZ(128|256)rrk(z?)$", 2562 "^VM(AX|IN|UL)PHZ(128|256)rrk(z?)$", 2563 "^VM(AX|IN|UL)SHZrr(b?)k(z?)_Int$")>; 2564 2565def SPRWriteResGroup252 : SchedWriteRes<[SPRPort00]> { 2566 let Latency = 5; 2567} 2568def : InstRW<[SPRWriteResGroup252], (instregex "^V(ADD|SUB)PHZrr(b?)$", 2569 "^VAES(DE|EN)C((LAST)?)Zrr$", 2570 "^VCVT(T?)PH2(U?)WZrr(b?)$", 2571 "^VCVT(U?)W2PHZrr(b?)$", 2572 "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(b?)$", 2573 "^VFMADDSUB(132|213|231)PHZr(b?)$", 2574 "^VFMSUBADD(132|213|231)PHZr(b?)$", 2575 "^VGETEXPPHZr(b?)$", 2576 "^VGETMANTPHZrri(b?)$", 2577 "^VM(AX|IN)CPHZrr$", 2578 "^VM(AX|IN|UL)PHZrr(b?)$", 2579 "^VMOVMSKP(D|S)Yrr$")>; 2580def : InstRW<[SPRWriteResGroup252], (instrs VGF2P8MULBZrr)>; 2581 2582def SPRWriteResGroup253 : SchedWriteRes<[SPRPort00]> { 2583 let Latency = 6; 2584} 2585def : InstRW<[SPRWriteResGroup253], (instregex "^V(ADD|SUB)PHZrr(bk|kz)$", 2586 "^V(ADD|SUB)PHZrr(k|bkz)$", 2587 "^VCVT(T?)PH2(U?)WZrr(bk|kz)$", 2588 "^VCVT(T?)PH2(U?)WZrr(k|bkz)$", 2589 "^VCVT(U?)W2PHZrr(bk|kz)$", 2590 "^VCVT(U?)W2PHZrr(k|bkz)$", 2591 "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(bk|kz)$", 2592 "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(k|bkz)$", 2593 "^VFMADDSUB(132|213|231)PHZr(bk|kz)$", 2594 "^VFMADDSUB(132|213|231)PHZr(k|bkz)$", 2595 "^VFMSUBADD(132|213|231)PHZr(bk|kz)$", 2596 "^VFMSUBADD(132|213|231)PHZr(k|bkz)$", 2597 "^VGETEXPPHZr(bk|kz)$", 2598 "^VGETEXPPHZr(k|bkz)$", 2599 "^VGETMANTPHZrri(bk|kz)$", 2600 "^VGETMANTPHZrri(k|bkz)$", 2601 "^VM(AX|IN)CPHZrrk(z?)$", 2602 "^VM(AX|IN|UL)PHZrr(bk|kz)$", 2603 "^VM(AX|IN|UL)PHZrr(k|bkz)$")>; 2604 2605def SPRWriteResGroup254 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> { 2606 let Latency = 11; 2607 let NumMicroOps = 2; 2608} 2609def : InstRW<[SPRWriteResGroup254], (instregex "^VPMOV(S|Z)XBWZ128rmk(z?)$", 2610 "^VPSHUF(H|L)WZ(128|256)mik(z?)$")>; 2611def : InstRW<[SPRWriteResGroup254, ReadAfterVecYLd], (instregex "^V(ADD|SUB)PSYrm$", 2612 "^V(ADD|SUB)PSZ256rm((b|k|bk|kz)?)$", 2613 "^V(ADD|SUB)PSZ256rmbkz$", 2614 "^VPSHUFBZ256rmk(z?)$", 2615 "^VPUNPCK(H|L)(BW|WD)Z256rmk(z?)$")>; 2616def : InstRW<[SPRWriteResGroup254, ReadAfterVecYLd], (instrs VADDSUBPSYrm)>; 2617def : InstRW<[SPRWriteResGroup254, ReadAfterVecXLd], (instregex "^VPSHUFBZ128rmk(z?)$", 2618 "^VPUNPCK(H|L)(BW|WD)Z128rmk(z?)$")>; 2619 2620def SPRWriteResGroup255 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10]> { 2621 let Latency = 11; 2622 let NumMicroOps = 2; 2623} 2624def : InstRW<[SPRWriteResGroup255], (instregex "^VMOVDQU(8|16)Zrmk(z?)$")>; 2625def : InstRW<[SPRWriteResGroup255, ReadAfterVecYLd], (instregex "^V(ADD|SUB)PSZrm((b|k|bk|kz)?)$", 2626 "^V(ADD|SUB)PSZrmbkz$", 2627 "^VP(ADD|SUB)(B|W)Zrmk(z?)$", 2628 "^VPBLENDM(B|W)Zrmk(z?)$")>; 2629 2630def SPRWriteResGroup256 : SchedWriteRes<[SPRPort00_05]> { 2631 let Latency = 4; 2632} 2633def : InstRW<[SPRWriteResGroup256], (instregex "^V(ADD|SUB)PSZrr(bk|kz)$", 2634 "^V(ADD|SUB)PSZrr(k|bkz)$")>; 2635 2636def SPRWriteResGroup257 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 2637 let Latency = 12; 2638 let NumMicroOps = 2; 2639} 2640def : InstRW<[SPRWriteResGroup257], (instregex "^VCVT(T?)PS2(U?)DQZrm((b|k|bk|kz)?)$", 2641 "^VCVT(T?)PS2(U?)DQZrmbkz$", 2642 "^VPLZCNT(D|Q)Zrm((b|k|bk|kz)?)$", 2643 "^VPLZCNT(D|Q)Zrmbkz$")>; 2644def : InstRW<[SPRWriteResGroup257, ReadAfterVecXLd], (instregex "^VAES(DE|EN)C((LAST)?)Zrm$")>; 2645def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZrm(b?)i$")>; 2646def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd], (instrs VGF2P8MULBZrm)>; 2647def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd, ReadAfterVecYLd], (instregex "^VPMADD52(H|L)UQZm((b|k|bk|kz)?)$", 2648 "^VPMADD52(H|L)UQZmbkz$")>; 2649 2650def SPRWriteResGroup258 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 2651 let Latency = 11; 2652 let NumMicroOps = 2; 2653} 2654def : InstRW<[SPRWriteResGroup258], (instregex "^VPBROADCAST(B|W)Z128rmk(z?)$", 2655 "^VPOPCNT(B|D|Q|W)Z((256)?)rm$", 2656 "^VPOPCNT(D|Q)Z((256)?)rm(b|k|kz)$", 2657 "^VPOPCNT(D|Q)Z((256)?)rmbk(z?)$", 2658 "^VPSHUF(H|L)WZmik(z?)$")>; 2659def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$", 2660 "^VALIGN(D|Q)Z((256)?)rmbik(z?)$", 2661 "^VALIGN(D|Q)Z((256)?)rmi((kz)?)$", 2662 "^VFPCLASSP(D|H|S)Z((256)?)mbi$", 2663 "^VPACK(S|U)S(DW|WB)(Y|Z)rm$", 2664 "^VPACK(S|U)S(DW|WB)Z256rm$", 2665 "^VPACK(S|U)SDWZ((256)?)rmb$", 2666 "^VPALIGNRZ((256)?)rmik(z?)$", 2667 "^VPM(AX|IN)(S|U)QZ((256)?)rm((b|k|bk|kz)?)$", 2668 "^VPM(AX|IN)(S|U)QZ((256)?)rmbkz$", 2669 "^VPMULTISHIFTQBZ((256)?)rm(b?)$", 2670 "^VPUNPCK(H|L)(BW|WD)Zrmk(z?)$")>; 2671def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>; 2672def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rmik(z?)$", 2673 "^VPCLMULQDQ(Y|Z)rmi$")>; 2674def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rmi)>; 2675 2676def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> { 2677 let ReleaseAtCycles = [3, 1]; 2678 let Latency = 10; 2679 let NumMicroOps = 4; 2680} 2681def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)Yrmr$")>; 2682def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrmr)>; 2683 2684def SPRWriteResGroup260 : SchedWriteRes<[SPRPort00_01_05]> { 2685 let ReleaseAtCycles = [3]; 2686 let Latency = 3; 2687 let NumMicroOps = 3; 2688} 2689def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rrr$", 2690 "^VBLENDVP(D|SY)rrr$", 2691 "^VPBLENDVB(Y?)rrr$")>; 2692 2693def SPRWriteResGroup261 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> { 2694 let ReleaseAtCycles = [3, 1]; 2695 let Latency = 9; 2696 let NumMicroOps = 4; 2697} 2698def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>; 2699def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>; 2700 2701def SPRWriteResGroup262 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> { 2702 let Latency = 9; 2703 let NumMicroOps = 2; 2704} 2705def : InstRW<[SPRWriteResGroup262], (instregex "^VBROADCAST(F|I)32X(2|4)Z256rmk(z?)$", 2706 "^VBROADCAST(F|I)64X2Z256rmk(z?)$", 2707 "^VBROADCASTS(D|S)Z256rmk(z?)$", 2708 "^VMOV(A|U)P(D|S)Z256rmk(z?)$", 2709 "^VMOV(D|SH|SL)DUPZ256rmk(z?)$", 2710 "^VMOVDQ(A|U)(32|64)Z256rmk(z?)$", 2711 "^VPBROADCAST(D|Q)Z256rmk(z?)$")>; 2712def : InstRW<[SPRWriteResGroup262, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rmi$", 2713 "^VINSERT(F|I)(32X4|64X2)Z256rmi((k|kz)?)$", 2714 "^VP(ADD|SUB)(B|D|Q|W)(Y|Z256)rm$", 2715 "^VP(ADD|SUB)(D|Q)Z256rm(b|k|kz)$", 2716 "^VP(ADD|SUB)(D|Q)Z256rmbk(z?)$", 2717 "^VPTERNLOG(D|Q)Z256rm(bi|ik)$", 2718 "^VPTERNLOG(D|Q)Z256rmbik(z?)$", 2719 "^VPTERNLOG(D|Q)Z256rmi((kz)?)$")>; 2720 2721def SPRWriteResGroup263 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 2722 let Latency = 3; 2723 let NumMicroOps = 2; 2724} 2725def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z128rm(bi|ik)$", 2726 "^VCMPP(D|H|S)Z128rm(i|bik)$", 2727 "^VFPCLASSP(D|H|S)Z128m(b?)ik$", 2728 "^VPCMP(B|D|Q|W|UD|UQ|UW)Z128rmi(k?)$", 2729 "^VPCMP(D|Q|UQ)Z128rmbi(k?)$", 2730 "^VPCMP(EQ|GT)(B|D|Q|W)Z128rm(k?)$", 2731 "^VPCMP(EQ|GT)(D|Q)Z128rmb(k?)$", 2732 "^VPCMPUBZ128rmi(k?)$", 2733 "^VPCMPUDZ128rmbi(k?)$", 2734 "^VPTEST(N?)M(B|D|Q|W)Z128rm(k?)$", 2735 "^VPTEST(N?)M(D|Q)Z128rmb(k?)$")>; 2736def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z((256)?)rm(bi|ik)$", 2737 "^VCMPP(D|H|S)Z((256)?)rm(i|bik)$", 2738 "^VFPCLASSP(D|H|S)Z((256)?)m(b?)ik$", 2739 "^VPCMP(B|D|Q|W|UD|UQ|UW)Z((256)?)rmi(k?)$", 2740 "^VPCMP(D|Q|UQ)Z((256)?)rmbi(k?)$", 2741 "^VPCMP(EQ|GT)(B|D|Q|W)Z((256)?)rm(k?)$", 2742 "^VPCMP(EQ|GT)(D|Q)Z((256)?)rmb(k?)$", 2743 "^VPCMPUBZ((256)?)rmi(k?)$", 2744 "^VPCMPUDZ((256)?)rmbi(k?)$", 2745 "^VPTEST(N?)M(B|D|Q|W)Z((256)?)rm(k?)$", 2746 "^VPTEST(N?)M(D|Q)Z((256)?)rmb(k?)$")>; 2747def : InstRW<[SPRWriteResGroup263, ReadAfterVecLd], (instregex "^VCMPS(D|H|S)Zrmi$", 2748 "^VCMPS(D|H|S)Zrmi(k?)_Int$", 2749 "^VFPCLASSS(D|H|S)Zmik$")>; 2750 2751def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 2752 let Latency = 10; 2753 let NumMicroOps = 2; 2754} 2755def : InstRW<[SPRWriteResGroup264, ReadAfterVecLd], (instregex "^V(U?)COMISHZrm((_Int)?)$")>; 2756 2757def SPRWriteResGroup265 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> { 2758 let ReleaseAtCycles = [1, 2, 1]; 2759 let Latency = 12; 2760 let NumMicroOps = 4; 2761} 2762def : InstRW<[SPRWriteResGroup265], (instregex "^VCOMPRESSP(D|S)Z(128|256)mr$", 2763 "^VCOMPRESSP(D|S)Zmr$", 2764 "^VPCOMPRESS(D|Q)Z(128|256)mr$", 2765 "^VPCOMPRESS(D|Q)Zmr$", 2766 "^VPMOV(D|Q|W|SQ|SW)BZmr$", 2767 "^VPMOV((S|US)?)(D|Q)WZmr$", 2768 "^VPMOV(U?)S(DB|QD)Zmr$", 2769 "^VPMOVUS(Q|W)BZmr$")>; 2770 2771def SPRWriteResGroup266 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> { 2772 let ReleaseAtCycles = [1, 2, 1]; 2773 let Latency = 15; 2774 let NumMicroOps = 4; 2775} 2776def : InstRW<[SPRWriteResGroup266], (instregex "^VCOMPRESSP(D|S)Z(128|256)mrk$", 2777 "^VCOMPRESSP(D|S)Zmrk$", 2778 "^VPCOMPRESS(D|Q)Z(128|256)mrk$", 2779 "^VPCOMPRESS(D|Q)Zmrk$", 2780 "^VPMOV(D|Q|W|SQ|SW)BZmrk$", 2781 "^VPMOV((S|US)?)(D|Q)WZmrk$", 2782 "^VPMOV(U?)S(DB|QD)Zmrk$", 2783 "^VPMOVUS(Q|W)BZmrk$")>; 2784 2785def SPRWriteResGroup267 : SchedWriteRes<[SPRPort05]> { 2786 let ReleaseAtCycles = [2]; 2787 let Latency = 3; 2788 let NumMicroOps = 2; 2789} 2790def : InstRW<[SPRWriteResGroup267], (instregex "^VCOMPRESSP(D|S)Z(128|256)rr$", 2791 "^VCOMPRESSP(D|S)Zrr$", 2792 "^VEXPANDP(D|S)Z(128|256)rr$", 2793 "^VEXPANDP(D|S)Zrr$", 2794 "^VPCOMPRESS(B|D|Q|W)Z(128|256)rr$", 2795 "^VPCOMPRESS(B|D|Q|W)Zrr$", 2796 "^VPEXPAND(B|D|Q|W)Z(128|256)rr$", 2797 "^VPEXPAND(B|D|Q|W)Zrr$")>; 2798 2799def SPRWriteResGroup268 : SchedWriteRes<[SPRPort00, SPRPort05]> { 2800 let Latency = 7; 2801 let NumMicroOps = 2; 2802} 2803def : InstRW<[SPRWriteResGroup268], (instregex "^VCVT(U?)DQ2PDZrr((k|kz)?)$", 2804 "^VCVT(T?)PS2(U?)QQZrr((b|k|bk|kz)?)$", 2805 "^VCVT(T?)PS2(U?)QQZrrbkz$", 2806 "^VCVT(U?)QQ2PSZrr((b|k|bk|kz)?)$", 2807 "^VCVT(U?)QQ2PSZrrbkz$")>; 2808 2809def SPRWriteResGroup269 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2810 let Latency = 15; 2811 let NumMicroOps = 4; 2812} 2813def : InstRW<[SPRWriteResGroup269], (instregex "^VCVT(U?)DQ2PHZ128rm(b?)$", 2814 "^VCVTNEPS2BF16Z128rm(b?)$")>; 2815 2816def SPRWriteResGroup270 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2817 let Latency = 19; 2818 let NumMicroOps = 4; 2819} 2820def : InstRW<[SPRWriteResGroup270], (instregex "^VCVT(U?)DQ2PHZ128rm(bk|kz)$", 2821 "^VCVT(U?)DQ2PHZ128rm(k|bkz)$")>; 2822 2823def SPRWriteResGroup271 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2824 let Latency = 7; 2825 let NumMicroOps = 3; 2826} 2827def : InstRW<[SPRWriteResGroup271], (instregex "^VCVT(U?)DQ2PHZ128rr$")>; 2828 2829def SPRWriteResGroup272 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2830 let Latency = 12; 2831 let NumMicroOps = 3; 2832} 2833def : InstRW<[SPRWriteResGroup272], (instregex "^VCVT(U?)DQ2PHZ128rrk(z?)$")>; 2834 2835def SPRWriteResGroup273 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2836 let Latency = 17; 2837 let NumMicroOps = 4; 2838} 2839def : InstRW<[SPRWriteResGroup273], (instregex "^VCVT(U?)DQ2PHZ256rm(b?)$", 2840 "^VCVTNEPS2BF16Z128rm(bk|kz)$", 2841 "^VCVTNEPS2BF16Z128rm(k|bkz)$")>; 2842 2843def SPRWriteResGroup274 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2844 let Latency = 21; 2845 let NumMicroOps = 4; 2846} 2847def : InstRW<[SPRWriteResGroup274], (instregex "^VCVT(U?)DQ2PHZ256rm(bk|kz)$", 2848 "^VCVT(U?)DQ2PHZ256rm(k|bkz)$")>; 2849 2850def SPRWriteResGroup275 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2851 let Latency = 9; 2852 let NumMicroOps = 3; 2853} 2854def : InstRW<[SPRWriteResGroup275], (instregex "^VCVT(U?)DQ2PHZ256rr$")>; 2855 2856def SPRWriteResGroup276 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2857 let Latency = 14; 2858 let NumMicroOps = 3; 2859} 2860def : InstRW<[SPRWriteResGroup276], (instregex "^VCVT(U?)DQ2PHZ256rrk(z?)$")>; 2861 2862def SPRWriteResGroup277 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 2863 let ReleaseAtCycles = [1, 1, 2]; 2864 let Latency = 17; 2865 let NumMicroOps = 4; 2866} 2867def : InstRW<[SPRWriteResGroup277], (instregex "^VCVT(U?)DQ2PHZrm(b?)$")>; 2868 2869def SPRWriteResGroup278 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 2870 let ReleaseAtCycles = [1, 1, 2]; 2871 let Latency = 21; 2872 let NumMicroOps = 4; 2873} 2874def : InstRW<[SPRWriteResGroup278], (instregex "^VCVT(U?)DQ2PHZrm(bk|kz)$", 2875 "^VCVT(U?)DQ2PHZrm(k|bkz)$")>; 2876 2877def SPRWriteResGroup279 : SchedWriteRes<[SPRPort00, SPRPort05]> { 2878 let ReleaseAtCycles = [1, 2]; 2879 let Latency = 9; 2880 let NumMicroOps = 3; 2881} 2882def : InstRW<[SPRWriteResGroup279], (instregex "^VCVT(U?)DQ2PHZrr(b?)$")>; 2883 2884def SPRWriteResGroup280 : SchedWriteRes<[SPRPort00, SPRPort05]> { 2885 let ReleaseAtCycles = [1, 2]; 2886 let Latency = 14; 2887 let NumMicroOps = 3; 2888} 2889def : InstRW<[SPRWriteResGroup280], (instregex "^VCVT(U?)DQ2PHZrr(bk|kz)$", 2890 "^VCVT(U?)DQ2PHZrr(k|bkz)$")>; 2891 2892def SPRWriteResGroup281 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2893 let ReleaseAtCycles = [2, 1, 1, 1]; 2894 let Latency = 15; 2895 let NumMicroOps = 5; 2896} 2897def : InstRW<[SPRWriteResGroup281, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(b?)$")>; 2898 2899def SPRWriteResGroup282 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2900 let ReleaseAtCycles = [2, 1, 1, 1]; 2901 let Latency = 17; 2902 let NumMicroOps = 5; 2903} 2904def : InstRW<[SPRWriteResGroup282, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(bk|kz)$", 2905 "^VCVTNE2PS2BF16Z128rm(k|bkz)$")>; 2906 2907def SPRWriteResGroup283 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2908 let ReleaseAtCycles = [2, 1, 1]; 2909 let Latency = 8; 2910 let NumMicroOps = 4; 2911} 2912def : InstRW<[SPRWriteResGroup283], (instregex "^VCVTNE2PS2BF16Z(128|256)rr$")>; 2913 2914def SPRWriteResGroup284 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2915 let ReleaseAtCycles = [2, 1, 1]; 2916 let Latency = 10; 2917 let NumMicroOps = 4; 2918} 2919def : InstRW<[SPRWriteResGroup284], (instregex "^VCVTNE2PS2BF16Z(128|256)rrk(z?)$")>; 2920 2921def SPRWriteResGroup285 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2922 let ReleaseAtCycles = [2, 1, 1, 1]; 2923 let Latency = 16; 2924 let NumMicroOps = 5; 2925} 2926def : InstRW<[SPRWriteResGroup285, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(b?)$")>; 2927 2928def SPRWriteResGroup286 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2929 let ReleaseAtCycles = [2, 1, 1, 1]; 2930 let Latency = 18; 2931 let NumMicroOps = 5; 2932} 2933def : InstRW<[SPRWriteResGroup286, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(bk|kz)$", 2934 "^VCVTNE2PS2BF16Z256rm(k|bkz)$")>; 2935 2936def SPRWriteResGroup287 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 2937 let ReleaseAtCycles = [2, 1, 2]; 2938 let Latency = 16; 2939 let NumMicroOps = 5; 2940} 2941def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(b?)$", 2942 "^VDPBF16PSZm((b|k|bk|kz)?)$")>; 2943def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instrs VDPBF16PSZmbkz)>; 2944 2945def SPRWriteResGroup288 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 2946 let ReleaseAtCycles = [2, 1, 2]; 2947 let Latency = 18; 2948 let NumMicroOps = 5; 2949} 2950def : InstRW<[SPRWriteResGroup288, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(bk|kz)$", 2951 "^VCVTNE2PS2BF16Zrm(k|bkz)$")>; 2952 2953def SPRWriteResGroup289 : SchedWriteRes<[SPRPort00, SPRPort05]> { 2954 let ReleaseAtCycles = [2, 2]; 2955 let Latency = 8; 2956 let NumMicroOps = 4; 2957} 2958def : InstRW<[SPRWriteResGroup289], (instregex "^VDPBF16PSZr((k|kz)?)$")>; 2959def : InstRW<[SPRWriteResGroup289], (instrs VCVTNE2PS2BF16Zrr)>; 2960 2961def SPRWriteResGroup290 : SchedWriteRes<[SPRPort00, SPRPort05]> { 2962 let ReleaseAtCycles = [2, 2]; 2963 let Latency = 10; 2964 let NumMicroOps = 4; 2965} 2966def : InstRW<[SPRWriteResGroup290], (instregex "^VCVTNE2PS2BF16Zrrk(z?)$")>; 2967 2968def SPRWriteResGroup291 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2969 let Latency = 8; 2970 let NumMicroOps = 3; 2971} 2972def : InstRW<[SPRWriteResGroup291], (instregex "^VCVTNEPS2BF16Z(128|256)rr$")>; 2973 2974def SPRWriteResGroup292 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> { 2975 let Latency = 10; 2976 let NumMicroOps = 3; 2977} 2978def : InstRW<[SPRWriteResGroup292], (instregex "^VCVTNEPS2BF16Z(128|256)rrk(z?)$")>; 2979 2980def SPRWriteResGroup293 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2981 let Latency = 16; 2982 let NumMicroOps = 4; 2983} 2984def : InstRW<[SPRWriteResGroup293], (instregex "^VCVTNEPS2BF16Z256rm(b?)$")>; 2985 2986def SPRWriteResGroup294 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 2987 let Latency = 18; 2988 let NumMicroOps = 4; 2989} 2990def : InstRW<[SPRWriteResGroup294], (instregex "^VCVTNEPS2BF16Z256rm(bk|kz)$", 2991 "^VCVTNEPS2BF16Z256rm(k|bkz)$")>; 2992 2993def SPRWriteResGroup295 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 2994 let ReleaseAtCycles = [1, 1, 2]; 2995 let Latency = 16; 2996 let NumMicroOps = 4; 2997} 2998def : InstRW<[SPRWriteResGroup295], (instregex "^VCVTNEPS2BF16Zrm(b?)$")>; 2999 3000def SPRWriteResGroup296 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3001 let ReleaseAtCycles = [1, 1, 2]; 3002 let Latency = 18; 3003 let NumMicroOps = 4; 3004} 3005def : InstRW<[SPRWriteResGroup296], (instregex "^VCVTNEPS2BF16Zrm(bk|kz)$", 3006 "^VCVTNEPS2BF16Zrm(k|bkz)$")>; 3007 3008def SPRWriteResGroup297 : SchedWriteRes<[SPRPort00, SPRPort05]> { 3009 let ReleaseAtCycles = [1, 2]; 3010 let Latency = 8; 3011 let NumMicroOps = 3; 3012} 3013def : InstRW<[SPRWriteResGroup297], (instrs VCVTNEPS2BF16Zrr)>; 3014 3015def SPRWriteResGroup298 : SchedWriteRes<[SPRPort00, SPRPort05]> { 3016 let ReleaseAtCycles = [1, 2]; 3017 let Latency = 10; 3018 let NumMicroOps = 3; 3019} 3020def : InstRW<[SPRWriteResGroup298], (instregex "^VCVTNEPS2BF16Zrrk(z?)$")>; 3021 3022def SPRWriteResGroup299 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3023 let Latency = 15; 3024 let NumMicroOps = 3; 3025} 3026def : InstRW<[SPRWriteResGroup299], (instregex "^VCVT(T?)PD2DQYrm$", 3027 "^VCVT(T?)P(D|H)2(U?)DQZ256rm(b?)$", 3028 "^VCVT(T?)PD2(U?)DQZ256rm(bk|kz)$", 3029 "^VCVT(T?)PD2(U?)DQZ256rm(k|bkz)$", 3030 "^VCVTPH2PSXZ128rm(bk|kz)$", 3031 "^VCVTPH2PSXZ128rm(k|bkz)$", 3032 "^VCVTPH2PSXZ256rm(b?)$", 3033 "^VCVT(U?)QQ2PSZ256rm((b|k|bk|kz)?)$", 3034 "^VCVT(U?)QQ2PSZ256rmbkz$")>; 3035 3036def SPRWriteResGroup300 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3037 let Latency = 15; 3038 let NumMicroOps = 3; 3039} 3040def : InstRW<[SPRWriteResGroup300], (instregex "^VCVT(T?)P(D|H)2(U?)DQZrm(b?)$", 3041 "^VCVT(T?)PD2(U?)DQZrm(bk|kz)$", 3042 "^VCVT(T?)PD2(U?)DQZrm(k|bkz)$", 3043 "^VCVTPH2PSXZrm(b?)$", 3044 "^VCVT(U?)QQ2PSZrm((b|k|bk|kz)?)$", 3045 "^VCVT(U?)QQ2PSZrmbkz$")>; 3046 3047def SPRWriteResGroup301 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3048 let ReleaseAtCycles = [2, 1, 1, 1, 2]; 3049 let Latency = 19; 3050 let NumMicroOps = 7; 3051} 3052def : InstRW<[SPRWriteResGroup301], (instregex "^VCVTPD2PHZ128rm(b?)$")>; 3053 3054def SPRWriteResGroup302 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3055 let ReleaseAtCycles = [2, 1, 1, 1, 2]; 3056 let Latency = 22; 3057 let NumMicroOps = 7; 3058} 3059def : InstRW<[SPRWriteResGroup302], (instregex "^VCVTPD2PHZ128rm(bk|kz)$", 3060 "^VCVTPD2PHZ128rm(k|bkz)$")>; 3061 3062def SPRWriteResGroup303 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 3063 let ReleaseAtCycles = [2, 1, 2]; 3064 let Latency = 12; 3065 let NumMicroOps = 5; 3066} 3067def : InstRW<[SPRWriteResGroup303], (instrs VCVTPD2PHZ128rr)>; 3068 3069def SPRWriteResGroup304 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 3070 let ReleaseAtCycles = [2, 1, 2]; 3071 let Latency = 15; 3072 let NumMicroOps = 5; 3073} 3074def : InstRW<[SPRWriteResGroup304], (instregex "^VCVTPD2PHZ128rrk(z?)$")>; 3075 3076def SPRWriteResGroup305 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3077 let ReleaseAtCycles = [2, 1, 1, 2]; 3078 let Latency = 21; 3079 let NumMicroOps = 6; 3080} 3081def : InstRW<[SPRWriteResGroup305], (instregex "^VCVTPD2PHZ256rm(b?)$")>; 3082 3083def SPRWriteResGroup306 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3084 let ReleaseAtCycles = [2, 1, 1, 2]; 3085 let Latency = 24; 3086 let NumMicroOps = 6; 3087} 3088def : InstRW<[SPRWriteResGroup306], (instregex "^VCVTPD2PHZ256rm(bk|kz)$", 3089 "^VCVTPD2PHZ256rm(k|bkz)$")>; 3090 3091def SPRWriteResGroup307 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3092 let ReleaseAtCycles = [2, 2]; 3093 let Latency = 13; 3094 let NumMicroOps = 4; 3095} 3096def : InstRW<[SPRWriteResGroup307], (instrs VCVTPD2PHZ256rr)>; 3097 3098def SPRWriteResGroup308 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3099 let ReleaseAtCycles = [2, 2]; 3100 let Latency = 16; 3101 let NumMicroOps = 4; 3102} 3103def : InstRW<[SPRWriteResGroup308], (instregex "^VCVTPD2PHZ256rrk(z?)$")>; 3104 3105def SPRWriteResGroup309 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3106 let ReleaseAtCycles = [2, 1, 1, 2]; 3107 let Latency = 23; 3108 let NumMicroOps = 6; 3109} 3110def : InstRW<[SPRWriteResGroup309], (instregex "^VCVTP(D2PH|H2PD)Zrm(b?)$")>; 3111 3112def SPRWriteResGroup310 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3113 let ReleaseAtCycles = [2, 1, 1, 2]; 3114 let Latency = 26; 3115 let NumMicroOps = 6; 3116} 3117def : InstRW<[SPRWriteResGroup310], (instregex "^VCVTP(D2PH|H2PD)Zrm(bk|kz)$", 3118 "^VCVTP(D2PH|H2PD)Zrm(k|bkz)$")>; 3119 3120def SPRWriteResGroup311 : SchedWriteRes<[SPRPort00, SPRPort05]> { 3121 let ReleaseAtCycles = [2, 2]; 3122 let Latency = 15; 3123 let NumMicroOps = 4; 3124} 3125def : InstRW<[SPRWriteResGroup311], (instregex "^VCVTP(D2PH|H2PD)Zrr(b?)$")>; 3126 3127def SPRWriteResGroup312 : SchedWriteRes<[SPRPort00, SPRPort05]> { 3128 let ReleaseAtCycles = [2, 2]; 3129 let Latency = 18; 3130 let NumMicroOps = 4; 3131} 3132def : InstRW<[SPRWriteResGroup312], (instregex "^VCVTP(D2PH|H2PD)Zrr(bk|kz)$", 3133 "^VCVTP(D2PH|H2PD)Zrr(k|bkz)$")>; 3134 3135def SPRWriteResGroup313 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 3136 let Latency = 11; 3137 let NumMicroOps = 2; 3138} 3139def : InstRW<[SPRWriteResGroup313], (instregex "^VCVT(T?)PD2(U?)QQZ128rm((b|k|bk|kz)?)$", 3140 "^VCVT(T?)PD2(U?)QQZ128rmbkz$", 3141 "^VPABS(B|W)Z(128|256)rmk(z?)$", 3142 "^VPLZCNT(D|Q)Z128rm((b|k|bk|kz)?)$", 3143 "^VPLZCNT(D|Q)Z128rmbkz$", 3144 "^VPS(L|R)LWZ(128|256)mik(z?)$", 3145 "^VPSRAWZ(128|256)mik(z?)$")>; 3146def : InstRW<[SPRWriteResGroup313, ReadAfterVecLd], (instregex "^VFIXUPIMMS(D|S)Zrmi((k|kz)?)$", 3147 "^VSCALEFS(D|S)Zrm((k|kz)?)$")>; 3148def : InstRW<[SPRWriteResGroup313, ReadAfterVecXLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Z128rmk(z?)$", 3149 "^VPAVG(B|W)Z128rmk(z?)$", 3150 "^VPM(AX|IN)(SB|UW)Z128rmk(z?)$", 3151 "^VPM(AX|IN)(SW|UB)Z128rmk(z?)$", 3152 "^VPSH(L|R)DVWZ128mk(z?)$", 3153 "^VPS(L|R)L(V?)WZ128rmk(z?)$", 3154 "^VPSRA(V?)WZ128rmk(z?)$")>; 3155def : InstRW<[SPRWriteResGroup313, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Z256rmk(z?)$", 3156 "^VPAVG(B|W)Z256rmk(z?)$", 3157 "^VPM(AX|IN)(SB|UW)Z256rmk(z?)$", 3158 "^VPM(AX|IN)(SW|UB)Z256rmk(z?)$", 3159 "^VPSH(L|R)DVWZ256mk(z?)$", 3160 "^VPS(L|R)L(V?)WZ256rmk(z?)$", 3161 "^VPSRA(V?)WZ256rmk(z?)$")>; 3162def : InstRW<[SPRWriteResGroup313, ReadAfterVecXLd, ReadAfterVecXLd], (instregex "^VPMADD52(H|L)UQZ128m((b|k|bk|kz)?)$", 3163 "^VPMADD52(H|L)UQZ128mbkz$")>; 3164 3165def SPRWriteResGroup314 : SchedWriteRes<[SPRPort00_01]> { 3166 let Latency = 4; 3167} 3168def : InstRW<[SPRWriteResGroup314], (instregex "^VCVT(T?)PD2(U?)QQZ(128|256)rr((k|kz)?)$", 3169 "^VCVT(U?)QQ2PDZ(128|256)rr((k|kz)?)$", 3170 "^VFIXUPIMMS(D|S)Zrri((k|kz)?)$", 3171 "^VPLZCNT(D|Q)Z(128|256)rr((k|kz)?)$", 3172 "^VPMADD52(H|L)UQZ(128|256)r((k|kz)?)$", 3173 "^VSCALEFS(D|S)Zrr((k|kz)?)$", 3174 "^VSCALEFS(D|S)Zrrb((k|kz)?)_Int$")>; 3175def : InstRW<[SPRWriteResGroup314, ReadAfterVecLd], (instregex "^VFIXUPIMMS(D|S)Zrrib((k|kz)?)$")>; 3176 3177def SPRWriteResGroup315 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3178 let Latency = 14; 3179 let NumMicroOps = 3; 3180} 3181def : InstRW<[SPRWriteResGroup315], (instregex "^VCVT(T?)PH2(U?)DQZ128rm(b?)$", 3182 "^VCVTPS2PHXZ128rm(b?)$")>; 3183 3184def SPRWriteResGroup316 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3185 let Latency = 17; 3186 let NumMicroOps = 3; 3187} 3188def : InstRW<[SPRWriteResGroup316], (instregex "^VCVT(T?)PH2(U?)DQZ128rm(bk|kz)$", 3189 "^VCVT(T?)PH2(U?)DQZ128rm(k|bkz)$")>; 3190 3191def SPRWriteResGroup317 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3192 let Latency = 11; 3193 let NumMicroOps = 2; 3194} 3195def : InstRW<[SPRWriteResGroup317], (instregex "^VCVT(T?)PH2(U?)DQZ(128|256)rrk(z?)$", 3196 "^VCVTP(H2PS|S2PH)(X?)Z256rrk(z?)$")>; 3197 3198def SPRWriteResGroup318 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3199 let Latency = 18; 3200 let NumMicroOps = 3; 3201} 3202def : InstRW<[SPRWriteResGroup318], (instregex "^VCVT(T?)PH2(U?)DQZ256rm(bk|kz)$", 3203 "^VCVT(T?)PH2(U?)DQZ256rm(k|bkz)$", 3204 "^VCVTP(H2PS|S2PH)XZ256rm(bk|kz)$", 3205 "^VCVTP(H2PS|S2PH)XZ256rm(k|bkz)$")>; 3206 3207def SPRWriteResGroup319 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3208 let Latency = 18; 3209 let NumMicroOps = 3; 3210} 3211def : InstRW<[SPRWriteResGroup319], (instregex "^VCVT(T?)PH2(U?)DQZrm(bk|kz)$", 3212 "^VCVT(T?)PH2(U?)DQZrm(k|bkz)$", 3213 "^VCVTP(H2PS|S2PH)XZrm(bk|kz)$", 3214 "^VCVTP(H2PS|S2PH)XZrm(k|bkz)$")>; 3215 3216def SPRWriteResGroup320 : SchedWriteRes<[SPRPort00, SPRPort05]> { 3217 let Latency = 8; 3218 let NumMicroOps = 2; 3219} 3220def : InstRW<[SPRWriteResGroup320], (instregex "^VCVT(T?)PH2(U?)DQZrr(b?)$", 3221 "^VCVTP(H2PS|S2PH)(X?)Zrr(b?)$", 3222 "^VPSHUFBITQMBZ(128|256)rrk$")>; 3223def : InstRW<[SPRWriteResGroup320], (instrs VPSHUFBITQMBZrrk)>; 3224 3225def SPRWriteResGroup321 : SchedWriteRes<[SPRPort00, SPRPort05]> { 3226 let Latency = 11; 3227 let NumMicroOps = 2; 3228} 3229def : InstRW<[SPRWriteResGroup321], (instregex "^VCVT(T?)PH2(U?)DQZrr(bk|kz)$", 3230 "^VCVT(T?)PH2(U?)DQZrr(k|bkz)$", 3231 "^VCVTP(H2PS|S2PH)XZrr(bk|kz)$", 3232 "^VCVTP(H2PS|S2PH)XZrr(k|bkz)$")>; 3233 3234def SPRWriteResGroup322 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3235 let ReleaseAtCycles = [2, 1, 1, 1, 2]; 3236 let Latency = 23; 3237 let NumMicroOps = 7; 3238} 3239def : InstRW<[SPRWriteResGroup322], (instregex "^VCVTPH2PDZ128rm(b?)$")>; 3240 3241def SPRWriteResGroup323 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3242 let ReleaseAtCycles = [2, 1, 1, 1, 2]; 3243 let Latency = 26; 3244 let NumMicroOps = 7; 3245} 3246def : InstRW<[SPRWriteResGroup323], (instregex "^VCVTPH2PDZ128rm(bk|kz)$", 3247 "^VCVTPH2PDZ128rm(k|bkz)$")>; 3248 3249def SPRWriteResGroup324 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> { 3250 let ReleaseAtCycles = [2, 1, 1, 2]; 3251 let Latency = 16; 3252 let NumMicroOps = 6; 3253} 3254def : InstRW<[SPRWriteResGroup324], (instrs VCVTPH2PDZ128rr)>; 3255 3256def SPRWriteResGroup325 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> { 3257 let ReleaseAtCycles = [2, 1, 1, 2]; 3258 let Latency = 19; 3259 let NumMicroOps = 6; 3260} 3261def : InstRW<[SPRWriteResGroup325], (instregex "^VCVTPH2PDZ128rrk(z?)$")>; 3262 3263def SPRWriteResGroup326 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3264 let ReleaseAtCycles = [2, 1, 2]; 3265 let Latency = 22; 3266 let NumMicroOps = 5; 3267} 3268def : InstRW<[SPRWriteResGroup326], (instregex "^VCVTPH2PDZ256rm(b?)$")>; 3269 3270def SPRWriteResGroup327 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3271 let ReleaseAtCycles = [2, 1, 2]; 3272 let Latency = 25; 3273 let NumMicroOps = 5; 3274} 3275def : InstRW<[SPRWriteResGroup327], (instregex "^VCVTPH2PDZ256rm(bk|kz)$", 3276 "^VCVTPH2PDZ256rm(k|bkz)$")>; 3277 3278def SPRWriteResGroup328 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3279 let ReleaseAtCycles = [2, 2]; 3280 let Latency = 15; 3281 let NumMicroOps = 4; 3282} 3283def : InstRW<[SPRWriteResGroup328], (instrs VCVTPH2PDZ256rr)>; 3284 3285def SPRWriteResGroup329 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3286 let ReleaseAtCycles = [2, 2]; 3287 let Latency = 18; 3288 let NumMicroOps = 4; 3289} 3290def : InstRW<[SPRWriteResGroup329], (instregex "^VCVTPH2PDZ256rrk(z?)$")>; 3291 3292def SPRWriteResGroup330 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3293 let Latency = 9; 3294 let NumMicroOps = 2; 3295} 3296def : InstRW<[SPRWriteResGroup330], (instregex "^VCVTP(H2PS|S2PH)(X?)Z128rrk(z?)$")>; 3297 3298def SPRWriteResGroup331 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 3299 let Latency = 14; 3300 let NumMicroOps = 2; 3301} 3302def : InstRW<[SPRWriteResGroup331], (instregex "^VCVTPH2PSZ(128|256)rmk(z?)$")>; 3303def : InstRW<[SPRWriteResGroup331, ReadAfterVecLd], (instregex "^VCVTSH2SSZrmk(z?)_Int$")>; 3304def : InstRW<[SPRWriteResGroup331, ReadAfterVecXLd], (instregex "^VPMADDUBSWZ128rmk(z?)$", 3305 "^VPMULH((U|RS)?)WZ128rmk(z?)$", 3306 "^VPMULLWZ128rmk(z?)$")>; 3307def : InstRW<[SPRWriteResGroup331, ReadAfterVecYLd], (instregex "^VPMADDUBSWZ256rmk(z?)$", 3308 "^VPMULH((U|RS)?)WZ256rmk(z?)$", 3309 "^VPMULLWZ256rmk(z?)$")>; 3310 3311def SPRWriteResGroup332 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3312 let Latency = 13; 3313 let NumMicroOps = 3; 3314} 3315def : InstRW<[SPRWriteResGroup332], (instregex "^VCVT(T?)PS2(U?)QQZrm((b|k|bk|kz)?)$", 3316 "^VCVT(T?)PS2(U?)QQZrmbkz$")>; 3317def : InstRW<[SPRWriteResGroup332], (instrs VCVTPH2PSZrm)>; 3318def : InstRW<[SPRWriteResGroup332, ReadAfterVecYLd], (instregex "^VPERMWZrmk(z?)$")>; 3319 3320def SPRWriteResGroup333 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3321 let ReleaseAtCycles = [1, 2, 1, 1, 1]; 3322 let Latency = 17; 3323 let NumMicroOps = 6; 3324} 3325def : InstRW<[SPRWriteResGroup333], (instregex "^VCVT(T?)PH2(U?)QQZ128rm((b|k|bk|kz)?)$", 3326 "^VCVT(T?)PH2(U?)QQZ128rmbkz$")>; 3327 3328def SPRWriteResGroup334 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 3329 let ReleaseAtCycles = [1, 2, 1]; 3330 let Latency = 10; 3331 let NumMicroOps = 4; 3332} 3333def : InstRW<[SPRWriteResGroup334], (instregex "^VCVT(T?)PH2(U?)QQZ(128|256)rr((k|kz)?)$")>; 3334 3335def SPRWriteResGroup335 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3336 let ReleaseAtCycles = [1, 2, 1, 1, 1]; 3337 let Latency = 18; 3338 let NumMicroOps = 6; 3339} 3340def : InstRW<[SPRWriteResGroup335], (instregex "^VCVT(T?)PH2(U?)QQZ256rm((b|k|bk|kz)?)$", 3341 "^VCVT(T?)PH2(U?)QQZ256rmbkz$")>; 3342 3343def SPRWriteResGroup336 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3344 let Latency = 16; 3345 let NumMicroOps = 3; 3346} 3347def : InstRW<[SPRWriteResGroup336], (instregex "^VCVTPS2PHXZ128rm(bk|kz)$", 3348 "^VCVTPS2PHXZ128rm(k|bkz)$", 3349 "^VCVTPS2PHXZ256rm(b?)$")>; 3350 3351def SPRWriteResGroup337 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3352 let Latency = 16; 3353 let NumMicroOps = 3; 3354} 3355def : InstRW<[SPRWriteResGroup337], (instregex "^VCVTPS2PHXZrm(b?)$")>; 3356 3357def SPRWriteResGroup338 : SchedWriteRes<[SPRPort00_01, SPRPort04_09, SPRPort07_08]> { 3358 let Latency = 16; 3359 let NumMicroOps = 3; 3360} 3361def : InstRW<[SPRWriteResGroup338], (instregex "^VCVTPS2PHZ(128|256)mrk$")>; 3362 3363def SPRWriteResGroup339 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> { 3364 let Latency = 16; 3365 let NumMicroOps = 3; 3366} 3367def : InstRW<[SPRWriteResGroup339], (instrs VCVTPS2PHZmrk)>; 3368 3369def SPRWriteResGroup340 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3370 let Latency = 5; 3371 let NumMicroOps = 2; 3372} 3373def : InstRW<[SPRWriteResGroup340], (instregex "^VCVT(T?)PS2(U?)QQZ128rr((k|kz)?)$", 3374 "^VCVT(U?)QQ2PSZ128rr((k|kz)?)$")>; 3375 3376def SPRWriteResGroup341 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 3377 let Latency = 15; 3378 let NumMicroOps = 5; 3379} 3380def : InstRW<[SPRWriteResGroup341], (instregex "^VCVT(U?)QQ2PHZ128rm(b?)$")>; 3381 3382def SPRWriteResGroup342 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 3383 let Latency = 17; 3384 let NumMicroOps = 5; 3385} 3386def : InstRW<[SPRWriteResGroup342], (instregex "^VCVT(U?)QQ2PHZ128rm(bk|kz)$", 3387 "^VCVT(U?)QQ2PHZ128rm(k|bkz)$")>; 3388 3389def SPRWriteResGroup343 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> { 3390 let Latency = 8; 3391 let NumMicroOps = 4; 3392} 3393def : InstRW<[SPRWriteResGroup343], (instregex "^VCVT(U?)QQ2PHZ128rr$")>; 3394 3395def SPRWriteResGroup344 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> { 3396 let Latency = 10; 3397 let NumMicroOps = 4; 3398} 3399def : InstRW<[SPRWriteResGroup344], (instregex "^VCVT(U?)QQ2PHZ128rrk(z?)$", 3400 "^VCVT(U?)QQ2PHZ256rr$")>; 3401 3402def SPRWriteResGroup345 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 3403 let Latency = 18; 3404 let NumMicroOps = 5; 3405} 3406def : InstRW<[SPRWriteResGroup345], (instregex "^VCVT(U?)QQ2PHZ256rm(b?)$")>; 3407 3408def SPRWriteResGroup346 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 3409 let Latency = 20; 3410 let NumMicroOps = 5; 3411} 3412def : InstRW<[SPRWriteResGroup346], (instregex "^VCVT(U?)QQ2PHZ256rm(bk|kz)$", 3413 "^VCVT(U?)QQ2PHZ256rm(k|bkz)$")>; 3414 3415def SPRWriteResGroup347 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> { 3416 let Latency = 12; 3417 let NumMicroOps = 4; 3418} 3419def : InstRW<[SPRWriteResGroup347], (instregex "^VCVT(U?)QQ2PHZ256rrk(z?)$")>; 3420 3421def SPRWriteResGroup348 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 3422 let ReleaseAtCycles = [1, 1, 1, 2]; 3423 let Latency = 18; 3424 let NumMicroOps = 5; 3425} 3426def : InstRW<[SPRWriteResGroup348], (instregex "^VCVT(U?)QQ2PHZrm(b?)$")>; 3427 3428def SPRWriteResGroup349 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 3429 let ReleaseAtCycles = [1, 1, 1, 2]; 3430 let Latency = 20; 3431 let NumMicroOps = 5; 3432} 3433def : InstRW<[SPRWriteResGroup349], (instregex "^VCVT(U?)QQ2PHZrm(bk|kz)$", 3434 "^VCVT(U?)QQ2PHZrm(k|bkz)$")>; 3435 3436def SPRWriteResGroup350 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 3437 let ReleaseAtCycles = [1, 1, 2]; 3438 let Latency = 10; 3439 let NumMicroOps = 4; 3440} 3441def : InstRW<[SPRWriteResGroup350], (instregex "^VCVT(U?)QQ2PHZrr(b?)$")>; 3442 3443def SPRWriteResGroup351 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 3444 let ReleaseAtCycles = [1, 1, 2]; 3445 let Latency = 12; 3446 let NumMicroOps = 4; 3447} 3448def : InstRW<[SPRWriteResGroup351], (instregex "^VCVT(U?)QQ2PHZrr(bk|kz)$", 3449 "^VCVT(U?)QQ2PHZrr(k|bkz)$")>; 3450 3451def SPRWriteResGroup352 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3452 let ReleaseAtCycles = [2, 2, 1, 1, 1]; 3453 let Latency = 18; 3454 let NumMicroOps = 7; 3455} 3456def : InstRW<[SPRWriteResGroup352, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm((_Int)?)$")>; 3457 3458def SPRWriteResGroup353 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3459 let ReleaseAtCycles = [2, 2, 1, 1, 1]; 3460 let Latency = 21; 3461 let NumMicroOps = 7; 3462} 3463def : InstRW<[SPRWriteResGroup353, ReadAfterVecLd], (instregex "^VCVTSD2SHZrmk(z?)_Int$")>; 3464 3465def SPRWriteResGroup354 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 3466 let ReleaseAtCycles = [2, 1, 1]; 3467 let Latency = 11; 3468 let NumMicroOps = 4; 3469} 3470def : InstRW<[SPRWriteResGroup354], (instregex "^VCVTSD2SHZrr(b?)_Int$")>; 3471def : InstRW<[SPRWriteResGroup354], (instrs VCVTSD2SHZrr)>; 3472 3473def SPRWriteResGroup355 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 3474 let ReleaseAtCycles = [2, 1, 1]; 3475 let Latency = 14; 3476 let NumMicroOps = 4; 3477} 3478def : InstRW<[SPRWriteResGroup355], (instregex "^VCVTSD2SHZrr(b?)k(z?)_Int$")>; 3479 3480def SPRWriteResGroup356 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3481 let ReleaseAtCycles = [2, 1, 1]; 3482 let Latency = 18; 3483 let NumMicroOps = 4; 3484} 3485def : InstRW<[SPRWriteResGroup356, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm((_Int)?)$")>; 3486 3487def SPRWriteResGroup357 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3488 let ReleaseAtCycles = [2, 1, 1]; 3489 let Latency = 20; 3490 let NumMicroOps = 4; 3491} 3492def : InstRW<[SPRWriteResGroup357, ReadAfterVecLd], (instregex "^VCVTSH2SDZrmk(z?)_Int$")>; 3493 3494def SPRWriteResGroup358 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3495 let ReleaseAtCycles = [2, 1]; 3496 let Latency = 10; 3497 let NumMicroOps = 3; 3498} 3499def : InstRW<[SPRWriteResGroup358], (instregex "^VCVTSH2SDZrr(b?)_Int$")>; 3500def : InstRW<[SPRWriteResGroup358], (instrs VCVTSH2SDZrr)>; 3501 3502def SPRWriteResGroup359 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3503 let ReleaseAtCycles = [2, 1]; 3504 let Latency = 13; 3505 let NumMicroOps = 3; 3506} 3507def : InstRW<[SPRWriteResGroup359], (instregex "^VCVTSH2SDZrr(b?)k(z?)_Int$")>; 3508 3509def SPRWriteResGroup360 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_10]> { 3510 let Latency = 13; 3511 let NumMicroOps = 3; 3512} 3513def : InstRW<[SPRWriteResGroup360, ReadAfterVecLd], (instregex "^VCVT(T?)SH2(U?)SI((64)?)Zrm_Int$", 3514 "^VCVTTSH2(U?)SI((64)?)Zrm$")>; 3515 3516def SPRWriteResGroup361 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05]> { 3517 let Latency = 8; 3518 let NumMicroOps = 3; 3519} 3520def : InstRW<[SPRWriteResGroup361], (instregex "^VCVT(T?)SH2(U?)SI((64)?)Zrr(b?)_Int$", 3521 "^VCVTTSH2(U?)SI((64)?)Zrr$")>; 3522 3523def SPRWriteResGroup362 : SchedWriteRes<[SPRPort00_01]> { 3524 let Latency = 8; 3525} 3526def : InstRW<[SPRWriteResGroup362], (instregex "^VCVTSH2SSZrr(b?)k(z?)_Int$")>; 3527 3528def SPRWriteResGroup363 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> { 3529 let Latency = 14; 3530 let NumMicroOps = 3; 3531} 3532def : InstRW<[SPRWriteResGroup363, ReadAfterVecLd], (instregex "^VCVT(U?)SI((64)?)2SHZrm((_Int)?)$", 3533 "^VCVTSS2SHZrm((_Int)?)$")>; 3534 3535def SPRWriteResGroup364 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> { 3536 let Latency = 16; 3537 let NumMicroOps = 3; 3538} 3539def : InstRW<[SPRWriteResGroup364, ReadAfterVecLd], (instregex "^VCVTSS2SHZrmk(z?)_Int$")>; 3540 3541def SPRWriteResGroup365 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> { 3542 let Latency = 6; 3543 let NumMicroOps = 2; 3544} 3545def : InstRW<[SPRWriteResGroup365], (instregex "^VCVTSS2SHZrr(b?)_Int$")>; 3546def : InstRW<[SPRWriteResGroup365], (instrs VCVTSS2SHZrr)>; 3547 3548def SPRWriteResGroup366 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> { 3549 let Latency = 9; 3550 let NumMicroOps = 2; 3551} 3552def : InstRW<[SPRWriteResGroup366], (instregex "^VCVTSS2SHZrr(b?)k(z?)_Int$")>; 3553 3554def SPRWriteResGroup367 : SchedWriteRes<[SPRPort05]> { 3555 let Latency = 5; 3556} 3557def : InstRW<[SPRWriteResGroup367], (instregex "^VDBPSADBWZ(128|256)rrik(z?)$", 3558 "^VDBPSADBWZrrik(z?)$", 3559 "^VPACK(S|U)S(DW|WB)Z(128|256)rrk(z?)$", 3560 "^VPACK(S|U)S(DW|WB)Zrrk(z?)$", 3561 "^VPBROADCAST(B|W|Dr|Qr|Wr)Z((256)?)rrk(z?)$", 3562 "^VPBROADCAST(B|D|Q|W)rZ(128|256)rr$", 3563 "^VPBROADCASTBrZ(128|256)rrk(z?)$", 3564 "^VPBROADCAST(B|D|Q|W)rZrr$", 3565 "^VPBROADCASTBrZrrk(z?)$", 3566 "^VPBROADCAST(D|Q|W)rZ128rrk(z?)$", 3567 "^VPERMBZ(128|256)rrk(z?)$", 3568 "^VPERMBZrrk(z?)$", 3569 "^VPMOV(S|Z)XBWZ((256)?)rrk(z?)$", 3570 "^VPMULTISHIFTQBZ(128|256)rrk(z?)$", 3571 "^VPMULTISHIFTQBZrrk(z?)$", 3572 "^VPOPCNT(B|W)Z(128|256)rrk(z?)$", 3573 "^VPOPCNT(B|W)Zrrk(z?)$")>; 3574 3575def SPRWriteResGroup368 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 3576 let ReleaseAtCycles = [2, 1, 1]; 3577 let Latency = 36; 3578 let NumMicroOps = 4; 3579} 3580def : InstRW<[SPRWriteResGroup368, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(b?)$")>; 3581 3582def SPRWriteResGroup369 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 3583 let ReleaseAtCycles = [2, 1, 1]; 3584 let Latency = 38; 3585 let NumMicroOps = 4; 3586} 3587def : InstRW<[SPRWriteResGroup369, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(bk|kz)$", 3588 "^VDIVPHZ128rm(k|bkz)$")>; 3589 3590def SPRWriteResGroup370 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 3591 let ReleaseAtCycles = [2, 1]; 3592 let Latency = 31; 3593 let NumMicroOps = 3; 3594} 3595def : InstRW<[SPRWriteResGroup370], (instregex "^VDIVPHZ(128|256)rr$")>; 3596 3597def SPRWriteResGroup371 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 3598 let ReleaseAtCycles = [2, 1]; 3599 let Latency = 33; 3600 let NumMicroOps = 3; 3601} 3602def : InstRW<[SPRWriteResGroup371], (instregex "^VDIVPHZ(128|256)rrk$", 3603 "^VSQRTPHZ(128|256)r$")>; 3604def : InstRW<[SPRWriteResGroup371], (instrs VDIVPHZ128rrkz)>; 3605 3606def SPRWriteResGroup372 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 3607 let ReleaseAtCycles = [2, 1, 1]; 3608 let Latency = 37; 3609 let NumMicroOps = 4; 3610} 3611def : InstRW<[SPRWriteResGroup372, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(b?)$")>; 3612 3613def SPRWriteResGroup373 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 3614 let ReleaseAtCycles = [2, 1, 1]; 3615 let Latency = 39; 3616 let NumMicroOps = 4; 3617} 3618def : InstRW<[SPRWriteResGroup373, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(bk|kz)$", 3619 "^VDIVPHZ256rm(k|bkz)$")>; 3620def : InstRW<[SPRWriteResGroup373, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(b?)$")>; 3621 3622def SPRWriteResGroup374 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 3623 let ReleaseAtCycles = [2, 1]; 3624 let Latency = 11; 3625 let NumMicroOps = 3; 3626} 3627def : InstRW<[SPRWriteResGroup374], (instrs VDIVPHZ256rrkz)>; 3628 3629def SPRWriteResGroup375 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3630 let ReleaseAtCycles = [4, 2, 1, 1, 1]; 3631 let Latency = 49; 3632 let NumMicroOps = 9; 3633} 3634def : InstRW<[SPRWriteResGroup375, ReadAfterVecYLd], (instregex "^VDIVPHZrm(b?)$")>; 3635 3636def SPRWriteResGroup376 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 3637 let ReleaseAtCycles = [4, 2, 1, 1, 1]; 3638 let Latency = 51; 3639 let NumMicroOps = 9; 3640} 3641def : InstRW<[SPRWriteResGroup376, ReadAfterVecYLd], (instregex "^VDIVPHZrm(bk|kz)$", 3642 "^VDIVPHZrm(k|bkz)$")>; 3643 3644def SPRWriteResGroup377 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> { 3645 let ReleaseAtCycles = [4, 1, 1]; 3646 let Latency = 41; 3647 let NumMicroOps = 6; 3648} 3649def : InstRW<[SPRWriteResGroup377], (instregex "^VDIVPHZrr(b?)$")>; 3650 3651def SPRWriteResGroup378 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> { 3652 let ReleaseAtCycles = [4, 1, 1]; 3653 let Latency = 43; 3654 let NumMicroOps = 6; 3655} 3656def : InstRW<[SPRWriteResGroup378], (instregex "^VDIVPHZrr(bk|kz)$", 3657 "^VDIVPHZrr(k|bkz)$")>; 3658 3659def SPRWriteResGroup379 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 3660 let ReleaseAtCycles = [2, 1]; 3661 let Latency = 17; 3662 let NumMicroOps = 3; 3663} 3664def : InstRW<[SPRWriteResGroup379], (instrs VDIVPSZrr)>; 3665 3666def SPRWriteResGroup380 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 3667 let Latency = 21; 3668 let NumMicroOps = 2; 3669} 3670def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instregex "^VDIVSHZrm((k|kz)?)_Int$")>; 3671def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instrs VDIVSHZrm)>; 3672 3673def SPRWriteResGroup381 : SchedWriteRes<[SPRPort00]> { 3674 let Latency = 14; 3675} 3676def : InstRW<[SPRWriteResGroup381], (instrs VDIVSHZrr_Int, 3677 VSQRTSHZr_Int)>; 3678 3679def SPRWriteResGroup382 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3680 let ReleaseAtCycles = [2, 1, 2]; 3681 let Latency = 15; 3682 let NumMicroOps = 5; 3683} 3684def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instregex "^VDPBF16PSZ128m((b|k|bk|kz)?)$")>; 3685def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instrs VDPBF16PSZ128mbkz)>; 3686 3687def SPRWriteResGroup383 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 3688 let ReleaseAtCycles = [2, 2]; 3689 let Latency = 8; 3690 let NumMicroOps = 4; 3691} 3692def : InstRW<[SPRWriteResGroup383], (instregex "^VDPBF16PSZ(128|256)r((k|kz)?)$")>; 3693 3694def SPRWriteResGroup384 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 3695 let ReleaseAtCycles = [2, 1, 2]; 3696 let Latency = 16; 3697 let NumMicroOps = 5; 3698} 3699def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instregex "^VDPBF16PSZ256m((b|k|bk|kz)?)$")>; 3700def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instrs VDPBF16PSZ256mbkz)>; 3701 3702def SPRWriteResGroup385 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> { 3703 let ReleaseAtCycles = [6, 7, 18]; 3704 let Latency = 81; 3705 let NumMicroOps = 31; 3706} 3707def : InstRW<[SPRWriteResGroup385], (instrs VERRm)>; 3708 3709def SPRWriteResGroup386 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> { 3710 let ReleaseAtCycles = [6, 7, 17]; 3711 let Latency = 74; 3712 let NumMicroOps = 30; 3713} 3714def : InstRW<[SPRWriteResGroup386], (instrs VERRr)>; 3715 3716def SPRWriteResGroup387 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> { 3717 let ReleaseAtCycles = [5, 8, 21]; 3718 let Latency = 81; 3719 let NumMicroOps = 34; 3720} 3721def : InstRW<[SPRWriteResGroup387], (instrs VERWm)>; 3722 3723def SPRWriteResGroup388 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_10]> { 3724 let ReleaseAtCycles = [5, 8, 20]; 3725 let Latency = 74; 3726 let NumMicroOps = 33; 3727} 3728def : InstRW<[SPRWriteResGroup388], (instrs VERWr)>; 3729 3730def SPRWriteResGroup389 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 3731 let ReleaseAtCycles = [1, 2]; 3732 let Latency = 10; 3733 let NumMicroOps = 3; 3734} 3735def : InstRW<[SPRWriteResGroup389, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z128rm((k|kz)?)$", 3736 "^VPEXPAND(B|D|Q|W)Z128rm$", 3737 "^VPEXPAND(D|Q)Z128rmk(z?)$")>; 3738 3739def SPRWriteResGroup390 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 3740 let ReleaseAtCycles = [2, 1]; 3741 let Latency = 16; 3742 let NumMicroOps = 3; 3743} 3744def : InstRW<[SPRWriteResGroup390], (instregex "^VF(C?)MADDCPHZ(128|256)m(b?)$", 3745 "^VROUNDP(D|S)Ymi$")>; 3746def : InstRW<[SPRWriteResGroup390, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZm$", 3747 "^VF(C?)MULCPHZ128rm(b?)$", 3748 "^VF(C?)MULCSHZrm$", 3749 "^VRNDSCALEPHZ128rm(b?)i$", 3750 "^VRNDSCALESHZrmi((_Int)?)$", 3751 "^VSCALEFPHZ128rm(b?)$")>; 3752def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(b?)$", 3753 "^VRNDSCALEP(D|H|S)Z256rm(b?)i$", 3754 "^VRNDSCALEP(D|S)Z256rm(b?)ik(z?)$", 3755 "^VSCALEFPHZ256rm(b?)$")>; 3756def : InstRW<[SPRWriteResGroup390, ReadAfterVecLd], (instrs VSCALEFSHZrm)>; 3757 3758def SPRWriteResGroup391 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 3759 let ReleaseAtCycles = [2, 1]; 3760 let Latency = 21; 3761 let NumMicroOps = 3; 3762} 3763def : InstRW<[SPRWriteResGroup391], (instregex "^VF(C?)MADDCPHZ(128|256)m(bk|kz)$", 3764 "^VF(C?)MADDCPHZ(128|256)m(k|bkz)$")>; 3765def : InstRW<[SPRWriteResGroup391, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZmk(z?)$", 3766 "^VF(C?)MULCPHZ128rm(bk|kz)$", 3767 "^VF(C?)MULCPHZ128rm(k|bkz)$", 3768 "^VF(C?)MULCSHZrmk(z?)$")>; 3769def : InstRW<[SPRWriteResGroup391, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(bk|kz)$", 3770 "^VF(C?)MULCPHZ256rm(k|bkz)$")>; 3771 3772def SPRWriteResGroup392 : SchedWriteRes<[SPRPort00_01]> { 3773 let ReleaseAtCycles = [2]; 3774 let Latency = 9; 3775 let NumMicroOps = 2; 3776} 3777def : InstRW<[SPRWriteResGroup392], (instregex "^VF(C?)MADDCPHZ(128|256)r$", 3778 "^VF(C?)MADDCSHZr(b?)$", 3779 "^VF(C?)MULCPHZ(128|256)rr$", 3780 "^VF(C?)MULCSHZrr(b?)$", 3781 "^VRNDSCALEPHZ(128|256)rri$", 3782 "^VRNDSCALESHZrri(b?)_Int$", 3783 "^VSCALEFPHZ(128|256)rr$")>; 3784def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZrri, 3785 VSCALEFSHZrr, 3786 VSCALEFSHZrrb_Int)>; 3787 3788def SPRWriteResGroup393 : SchedWriteRes<[SPRPort00_01]> { 3789 let ReleaseAtCycles = [2]; 3790 let Latency = 15; 3791 let NumMicroOps = 2; 3792} 3793def : InstRW<[SPRWriteResGroup393], (instregex "^VF(C?)MADDCPHZ(128|256)rk(z?)$", 3794 "^VF(C?)MADDCSHZr(bk|kz)$", 3795 "^VF(C?)MADDCSHZr(k|bkz)$", 3796 "^VF(C?)MULCPHZ(128|256)rrk(z?)$", 3797 "^VF(C?)MULCSHZrr(bk|kz)$", 3798 "^VF(C?)MULCSHZrr(k|bkz)$")>; 3799 3800def SPRWriteResGroup394 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 3801 let ReleaseAtCycles = [2, 1]; 3802 let Latency = 16; 3803 let NumMicroOps = 3; 3804} 3805def : InstRW<[SPRWriteResGroup394], (instregex "^VF(C?)MADDCPHZm(b?)$")>; 3806def : InstRW<[SPRWriteResGroup394, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(b?)$", 3807 "^VRNDSCALEP(D|H|S)Zrm(b?)i$", 3808 "^VRNDSCALEP(D|S)Zrm(b?)ik(z?)$", 3809 "^VSCALEFPHZrm(b?)$")>; 3810 3811def SPRWriteResGroup395 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 3812 let ReleaseAtCycles = [2, 1]; 3813 let Latency = 21; 3814 let NumMicroOps = 3; 3815} 3816def : InstRW<[SPRWriteResGroup395], (instregex "^VF(C?)MADDCPHZm(bk|kz)$", 3817 "^VF(C?)MADDCPHZm(k|bkz)$")>; 3818def : InstRW<[SPRWriteResGroup395, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(bk|kz)$", 3819 "^VF(C?)MULCPHZrm(k|bkz)$")>; 3820 3821def SPRWriteResGroup396 : SchedWriteRes<[SPRPort00]> { 3822 let ReleaseAtCycles = [2]; 3823 let Latency = 9; 3824 let NumMicroOps = 2; 3825} 3826def : InstRW<[SPRWriteResGroup396], (instregex "^VF(C?)MADDCPHZr(b?)$", 3827 "^VF(C?)MULCPHZrr(b?)$", 3828 "^VRNDSCALEPHZrri(b?)$", 3829 "^VSCALEFPHZrr(b?)$")>; 3830 3831def SPRWriteResGroup397 : SchedWriteRes<[SPRPort00]> { 3832 let ReleaseAtCycles = [2]; 3833 let Latency = 15; 3834 let NumMicroOps = 2; 3835} 3836def : InstRW<[SPRWriteResGroup397], (instregex "^VF(C?)MADDCPHZr(bk|kz)$", 3837 "^VF(C?)MADDCPHZr(k|bkz)$", 3838 "^VF(C?)MULCPHZrr(bk|kz)$", 3839 "^VF(C?)MULCPHZrr(k|bkz)$")>; 3840 3841def SPRWriteResGroup398 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> { 3842 let ReleaseAtCycles = [1, 1, 2, 4]; 3843 let Latency = 29; 3844 let NumMicroOps = 8; 3845} 3846def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$", 3847 "^VPGATHER(D|Q)QYrm$")>; 3848def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm, 3849 VPGATHERQDYrm)>; 3850 3851def SPRWriteResGroup399 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> { 3852 let ReleaseAtCycles = [1, 1, 2]; 3853 let Latency = 20; 3854 let NumMicroOps = 4; 3855} 3856def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ128rm$", 3857 "^VPGATHER(D|Q)QZ128rm$")>; 3858def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ128rm, 3859 VPGATHERQDZ128rm)>; 3860 3861def SPRWriteResGroup400 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> { 3862 let ReleaseAtCycles = [1, 2, 4]; 3863 let Latency = 28; 3864 let NumMicroOps = 7; 3865} 3866def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ256rm$", 3867 "^VPGATHER(D|Q)QZ256rm$")>; 3868def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ256rm, 3869 VPGATHERQDZ256rm)>; 3870 3871def SPRWriteResGroup401 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3872 let ReleaseAtCycles = [1, 8, 2]; 3873 let Latency = 28; 3874 let NumMicroOps = 11; 3875} 3876def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZrm$", 3877 "^VPGATHER(D|Q)QZrm$")>; 3878def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZrm, 3879 VPGATHERQDZrm)>; 3880 3881def SPRWriteResGroup402 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> { 3882 let ReleaseAtCycles = [1, 1, 1, 2]; 3883 let Latency = 20; 3884 let NumMicroOps = 5; 3885} 3886def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$", 3887 "^VPGATHER(D|Q)Qrm$")>; 3888def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm, 3889 VPGATHERQDrm)>; 3890 3891def SPRWriteResGroup403 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> { 3892 let ReleaseAtCycles = [1, 1, 2, 8]; 3893 let Latency = 30; 3894 let NumMicroOps = 12; 3895} 3896def : InstRW<[SPRWriteResGroup403, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm, 3897 VPGATHERDDYrm)>; 3898 3899def SPRWriteResGroup404 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> { 3900 let ReleaseAtCycles = [1, 2, 4]; 3901 let Latency = 27; 3902 let NumMicroOps = 7; 3903} 3904def : InstRW<[SPRWriteResGroup404, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ128rm, 3905 VPGATHERDDZ128rm)>; 3906 3907def SPRWriteResGroup405 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_10]> { 3908 let ReleaseAtCycles = [1, 2, 8]; 3909 let Latency = 29; 3910 let NumMicroOps = 11; 3911} 3912def : InstRW<[SPRWriteResGroup405, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ256rm, 3913 VPGATHERDDZ256rm)>; 3914 3915def SPRWriteResGroup406 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 3916 let ReleaseAtCycles = [1, 16, 2]; 3917 let Latency = 30; 3918 let NumMicroOps = 19; 3919} 3920def : InstRW<[SPRWriteResGroup406, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZrm, 3921 VPGATHERDDZrm)>; 3922 3923def SPRWriteResGroup407 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10]> { 3924 let ReleaseAtCycles = [1, 1, 2, 4]; 3925 let Latency = 28; 3926 let NumMicroOps = 8; 3927} 3928def : InstRW<[SPRWriteResGroup407, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm, 3929 VPGATHERDDrm)>; 3930 3931def SPRWriteResGroup408 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 3932 let Latency = 15; 3933 let NumMicroOps = 2; 3934} 3935def : InstRW<[SPRWriteResGroup408, ReadAfterVecXLd], (instregex "^VGF2P8AFFINE((INV)?)QBZ128rm(b?)ik(z?)$", 3936 "^VGF2P8MULBZ128rmk(z?)$")>; 3937def : InstRW<[SPRWriteResGroup408, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZ256rm(b?)ik(z?)$", 3938 "^VGF2P8MULBZ256rmk(z?)$")>; 3939 3940def SPRWriteResGroup409 : SchedWriteRes<[SPRPort00_01]> { 3941 let Latency = 9; 3942} 3943def : InstRW<[SPRWriteResGroup409], (instregex "^VGF2P8AFFINE((INV)?)QBZ(128|256)rrik$", 3944 "^VGF2P8MULBZ(128|256)rrk$")>; 3945 3946def SPRWriteResGroup410 : SchedWriteRes<[SPRPort00_01]> { 3947 let Latency = 10; 3948} 3949def : InstRW<[SPRWriteResGroup410], (instregex "^VGF2P8AFFINE((INV)?)QBZ(128|256)rrikz$", 3950 "^VGF2P8MULBZ(128|256)rrkz$")>; 3951 3952def SPRWriteResGroup411 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 3953 let Latency = 15; 3954 let NumMicroOps = 2; 3955} 3956def : InstRW<[SPRWriteResGroup411, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZrm(b?)ik(z?)$", 3957 "^VGF2P8MULBZrmk(z?)$")>; 3958 3959def SPRWriteResGroup412 : SchedWriteRes<[SPRPort00]> { 3960 let Latency = 9; 3961} 3962def : InstRW<[SPRWriteResGroup412], (instregex "^VGF2P8AFFINE((INV)?)QBZrrik$")>; 3963def : InstRW<[SPRWriteResGroup412], (instrs VGF2P8MULBZrrk)>; 3964 3965def SPRWriteResGroup413 : SchedWriteRes<[SPRPort00]> { 3966 let Latency = 10; 3967} 3968def : InstRW<[SPRWriteResGroup413], (instregex "^VGF2P8AFFINE((INV)?)QBZrrikz$")>; 3969def : InstRW<[SPRWriteResGroup413], (instrs VGF2P8MULBZrrkz)>; 3970 3971def SPRWriteResGroup414 : SchedWriteRes<[SPRPort01_05, SPRPort05]> { 3972 let ReleaseAtCycles = [1, 2]; 3973 let Latency = 5; 3974 let NumMicroOps = 3; 3975} 3976def : InstRW<[SPRWriteResGroup414], (instregex "^VH(ADD|SUB)P(D|S)rr$")>; 3977 3978def SPRWriteResGroup415 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_10]> { 3979 let Latency = 7; 3980 let NumMicroOps = 3; 3981} 3982def : InstRW<[SPRWriteResGroup415], (instrs VLDMXCSR)>; 3983 3984def SPRWriteResGroup416 : SchedWriteRes<[SPRPort01, SPRPort01_05, SPRPort02_03, SPRPort02_03_10, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> { 3985 let ReleaseAtCycles = [1, 1, 1, 8, 1, 1, 2, 3]; 3986 let Latency = 40; 3987 let NumMicroOps = 18; 3988} 3989def : InstRW<[SPRWriteResGroup416], (instrs VMCLEARm)>; 3990 3991def SPRWriteResGroup417 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10]> { 3992 let Latency = 11; 3993 let NumMicroOps = 2; 3994} 3995def : InstRW<[SPRWriteResGroup417], (instregex "^VMOVDQU(8|16)Z(128|256)rmk(z?)$", 3996 "^VMOVSHZrmk(z?)$")>; 3997def : InstRW<[SPRWriteResGroup417, ReadAfterVecXLd], (instregex "^VP(ADD|SUB)(B|W)Z128rmk(z?)$", 3998 "^VPBLENDM(B|W)Z128rmk(z?)$")>; 3999def : InstRW<[SPRWriteResGroup417, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(B|W)Z256rmk(z?)$", 4000 "^VPBLENDM(B|W)Z256rmk(z?)$")>; 4001 4002def SPRWriteResGroup418 : SchedWriteRes<[SPRPort00_01_05]> { 4003 let Latency = 3; 4004} 4005def : InstRW<[SPRWriteResGroup418], (instregex "^VMOVDQU(8|16)Z(128|256)rrk(z?)((_REV)?)$", 4006 "^VMOVSHZrrk(z?)((_REV)?)$", 4007 "^VP(ADD|SUB)(B|W)Z(128|256)rrk(z?)$", 4008 "^VPBLENDM(B|W)Z(128|256)rrk(z?)$", 4009 "^VPMOVM2(B|W)Z(128|256)rk$")>; 4010 4011def SPRWriteResGroup419 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 4012 let ReleaseAtCycles = [1, 2, 2]; 4013 let Latency = 12; 4014 let NumMicroOps = 5; 4015} 4016def : InstRW<[SPRWriteResGroup419], (instrs VMOVDQU8Zmrk)>; 4017 4018def SPRWriteResGroup420 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4019 let Latency = 477; 4020 let NumMicroOps = 2; 4021} 4022def : InstRW<[SPRWriteResGroup420], (instrs VMOVNTDQZ128mr)>; 4023 4024def SPRWriteResGroup421 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4025 let Latency = 470; 4026 let NumMicroOps = 2; 4027} 4028def : InstRW<[SPRWriteResGroup421], (instrs VMOVNTDQZ256mr, 4029 VMOVNTPSmr)>; 4030 4031def SPRWriteResGroup422 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4032 let Latency = 473; 4033 let NumMicroOps = 2; 4034} 4035def : InstRW<[SPRWriteResGroup422], (instregex "^VMOVNT(PD|DQZ)mr$")>; 4036 4037def SPRWriteResGroup423 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4038 let Latency = 521; 4039 let NumMicroOps = 2; 4040} 4041def : InstRW<[SPRWriteResGroup423], (instrs VMOVNTDQmr)>; 4042 4043def SPRWriteResGroup424 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4044 let Latency = 550; 4045 let NumMicroOps = 2; 4046} 4047def : InstRW<[SPRWriteResGroup424], (instrs VMOVNTPDZ128mr)>; 4048 4049def SPRWriteResGroup425 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4050 let Latency = 474; 4051 let NumMicroOps = 2; 4052} 4053def : InstRW<[SPRWriteResGroup425], (instrs VMOVNTPDZ256mr)>; 4054 4055def SPRWriteResGroup426 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4056 let Latency = 464; 4057 let NumMicroOps = 2; 4058} 4059def : InstRW<[SPRWriteResGroup426], (instrs VMOVNTPDZmr)>; 4060 4061def SPRWriteResGroup427 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4062 let Latency = 494; 4063 let NumMicroOps = 2; 4064} 4065def : InstRW<[SPRWriteResGroup427], (instrs VMOVNTPSYmr)>; 4066 4067def SPRWriteResGroup428 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4068 let Latency = 475; 4069 let NumMicroOps = 2; 4070} 4071def : InstRW<[SPRWriteResGroup428], (instrs VMOVNTPSZ128mr)>; 4072 4073def SPRWriteResGroup429 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4074 let Latency = 476; 4075 let NumMicroOps = 2; 4076} 4077def : InstRW<[SPRWriteResGroup429], (instrs VMOVNTPSZ256mr)>; 4078 4079def SPRWriteResGroup430 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> { 4080 let Latency = 471; 4081 let NumMicroOps = 2; 4082} 4083def : InstRW<[SPRWriteResGroup430], (instrs VMOVNTPSZmr)>; 4084 4085def SPRWriteResGroup431 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4086 let ReleaseAtCycles = [3, 1, 8]; 4087 let Latency = 10; 4088 let NumMicroOps = 12; 4089} 4090def : InstRW<[SPRWriteResGroup431, ReadAfterVecXLd], (instregex "^VP2INTERSECTDZ128rm(b?)$")>; 4091def : InstRW<[SPRWriteResGroup431, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZ256rm(b?)$")>; 4092 4093def SPRWriteResGroup432 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> { 4094 let ReleaseAtCycles = [4, 8]; 4095 let Latency = 10; 4096 let NumMicroOps = 12; 4097} 4098def : InstRW<[SPRWriteResGroup432], (instrs VP2INTERSECTDZ128rr, 4099 VP2INTERSECTQZ256rr)>; 4100 4101def SPRWriteResGroup433 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_10, SPRPort05]> { 4102 let ReleaseAtCycles = [1, 8, 7, 2, 1, 11]; 4103 let Latency = 27; 4104 let NumMicroOps = 30; 4105} 4106def : InstRW<[SPRWriteResGroup433, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZ256rm(b?)$")>; 4107 4108def SPRWriteResGroup434 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> { 4109 let ReleaseAtCycles = [1, 8, 8, 2, 11]; 4110 let Latency = 27; 4111 let NumMicroOps = 30; 4112} 4113def : InstRW<[SPRWriteResGroup434], (instrs VP2INTERSECTDZ256rr)>; 4114 4115def SPRWriteResGroup435 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4116 let ReleaseAtCycles = [13, 9, 1, 23]; 4117 let Latency = 40; 4118 let NumMicroOps = 46; 4119} 4120def : InstRW<[SPRWriteResGroup435, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZrm(b?)$")>; 4121 4122def SPRWriteResGroup436 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 4123 let ReleaseAtCycles = [13, 10, 23]; 4124 let Latency = 40; 4125 let NumMicroOps = 46; 4126} 4127def : InstRW<[SPRWriteResGroup436], (instrs VP2INTERSECTDZrr)>; 4128 4129def SPRWriteResGroup437 : SchedWriteRes<[SPRPort02_03_10, SPRPort05]> { 4130 let ReleaseAtCycles = [1, 4]; 4131 let Latency = 6; 4132 let NumMicroOps = 5; 4133} 4134def : InstRW<[SPRWriteResGroup437, ReadAfterVecXLd], (instregex "^VP2INTERSECTQZ128rm(b?)$")>; 4135 4136def SPRWriteResGroup438 : SchedWriteRes<[SPRPort05]> { 4137 let ReleaseAtCycles = [4]; 4138 let Latency = 6; 4139 let NumMicroOps = 4; 4140} 4141def : InstRW<[SPRWriteResGroup438], (instrs VP2INTERSECTQZ128rr)>; 4142 4143def SPRWriteResGroup439 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4144 let ReleaseAtCycles = [8, 7, 1, 14]; 4145 let Latency = 29; 4146 let NumMicroOps = 30; 4147} 4148def : InstRW<[SPRWriteResGroup439, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZrm(b?)$")>; 4149 4150def SPRWriteResGroup440 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 4151 let ReleaseAtCycles = [8, 8, 14]; 4152 let Latency = 30; 4153 let NumMicroOps = 30; 4154} 4155def : InstRW<[SPRWriteResGroup440], (instrs VP2INTERSECTQZrr)>; 4156 4157def SPRWriteResGroup441 : SchedWriteRes<[SPRPort00_01]> { 4158 let Latency = 3; 4159} 4160def : InstRW<[SPRWriteResGroup441], (instregex "^VP(A|SU)BS(B|W)Z(128|256)rrk(z?)$", 4161 "^VPADD(U?)S(B|W)Z(128|256)rrk(z?)$", 4162 "^VPAVG(B|W)Z(128|256)rrk(z?)$", 4163 "^VPM(AX|IN)(SB|UW)Z(128|256)rrk(z?)$", 4164 "^VPM(AX|IN)(SW|UB)Z(128|256)rrk(z?)$", 4165 "^VPSH(L|R)DVWZ(128|256)rk(z?)$", 4166 "^VPS(L|R)LVWZ(128|256)rrk(z?)$", 4167 "^VPS(L|R)LWZ(128|256)rik(z?)$", 4168 "^VPSRAVWZ(128|256)rrk(z?)$", 4169 "^VPSRAWZ(128|256)rik(z?)$", 4170 "^VPSUBUS(B|W)Z(128|256)rrk(z?)$")>; 4171 4172def SPRWriteResGroup442 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_10]> { 4173 let Latency = 9; 4174 let NumMicroOps = 2; 4175} 4176def : InstRW<[SPRWriteResGroup442, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$", 4177 "^VSHUFP(D|S)Z256rm(bi|ik)$", 4178 "^VSHUFP(D|S)Z256rmbik(z?)$", 4179 "^VSHUFP(D|S)Z256rmi((kz)?)$")>; 4180def : InstRW<[SPRWriteResGroup442, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>; 4181 4182def SPRWriteResGroup443 : SchedWriteRes<[SPRPort00, SPRPort05]> { 4183 let Latency = 6; 4184 let NumMicroOps = 2; 4185} 4186def : InstRW<[SPRWriteResGroup443], (instregex "^VPBROADCASTM(B2Q|W2D)Z(128|256)rr$", 4187 "^VPBROADCASTM(B2Q|W2D)Zrr$", 4188 "^VP(ERM|SRA)WZrrk(z?)$", 4189 "^VPSHUFBITQMBZ(128|256)rr$", 4190 "^VPS(L|R)LWZrrk(z?)$")>; 4191def : InstRW<[SPRWriteResGroup443], (instrs VPSHUFBITQMBZrr)>; 4192 4193def SPRWriteResGroup444 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4194 let ReleaseAtCycles = [1, 1, 1, 2, 1]; 4195 let Latency = 12; 4196 let NumMicroOps = 6; 4197} 4198def : InstRW<[SPRWriteResGroup444], (instregex "^VPCOMPRESS(B|W)Z(128|256)mr$")>; 4199def : InstRW<[SPRWriteResGroup444], (instrs VPCOMPRESSWZmr)>; 4200 4201def SPRWriteResGroup445 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4202 let ReleaseAtCycles = [1, 1, 1, 2, 1]; 4203 let Latency = 14; 4204 let NumMicroOps = 6; 4205} 4206def : InstRW<[SPRWriteResGroup445], (instregex "^VPCOMPRESS(B|W)Z(128|256)mrk$")>; 4207def : InstRW<[SPRWriteResGroup445], (instrs VPCOMPRESSWZmrk)>; 4208 4209def SPRWriteResGroup446 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4210 let ReleaseAtCycles = [1, 1, 2, 2, 2]; 4211 let Latency = 12; 4212 let NumMicroOps = 8; 4213} 4214def : InstRW<[SPRWriteResGroup446], (instrs VPCOMPRESSBZmr)>; 4215 4216def SPRWriteResGroup447 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4217 let ReleaseAtCycles = [1, 1, 2, 2, 2]; 4218 let Latency = 14; 4219 let NumMicroOps = 8; 4220} 4221def : InstRW<[SPRWriteResGroup447], (instrs VPCOMPRESSBZmrk)>; 4222 4223def SPRWriteResGroup448 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4224 let ReleaseAtCycles = [5, 4, 1, 5]; 4225 let Latency = 17; 4226 let NumMicroOps = 15; 4227} 4228def : InstRW<[SPRWriteResGroup448], (instregex "^VPCONFLICTDZ128rm((b|k|bk|kz)?)$")>; 4229def : InstRW<[SPRWriteResGroup448], (instrs VPCONFLICTDZ128rmbkz)>; 4230 4231def SPRWriteResGroup449 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 4232 let ReleaseAtCycles = [5, 5, 5]; 4233 let Latency = 12; 4234 let NumMicroOps = 15; 4235} 4236def : InstRW<[SPRWriteResGroup449], (instregex "^VPCONFLICTDZ128rr((k|kz)?)$")>; 4237 4238def SPRWriteResGroup450 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 4239 let ReleaseAtCycles = [7, 5, 1, 1, 9]; 4240 let Latency = 24; 4241 let NumMicroOps = 23; 4242} 4243def : InstRW<[SPRWriteResGroup450], (instregex "^VPCONFLICTDZ256rm((b|k|bk|kz)?)$")>; 4244def : InstRW<[SPRWriteResGroup450], (instrs VPCONFLICTDZ256rmbkz)>; 4245 4246def SPRWriteResGroup451 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> { 4247 let ReleaseAtCycles = [7, 6, 1, 9]; 4248 let Latency = 17; 4249 let NumMicroOps = 23; 4250} 4251def : InstRW<[SPRWriteResGroup451], (instregex "^VPCONFLICTDZ256rr((k|kz)?)$")>; 4252 4253def SPRWriteResGroup452 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4254 let ReleaseAtCycles = [11, 8, 1, 17]; 4255 let Latency = 33; 4256 let NumMicroOps = 37; 4257} 4258def : InstRW<[SPRWriteResGroup452], (instregex "^VPCONFLICTDZrm((b|k|bk|kz)?)$")>; 4259def : InstRW<[SPRWriteResGroup452], (instrs VPCONFLICTDZrmbkz)>; 4260 4261def SPRWriteResGroup453 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 4262 let ReleaseAtCycles = [11, 9, 17]; 4263 let Latency = 26; 4264 let NumMicroOps = 37; 4265} 4266def : InstRW<[SPRWriteResGroup453], (instregex "^VPCONFLICTDZrr((kz)?)$")>; 4267 4268def SPRWriteResGroup454 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 4269 let ReleaseAtCycles = [11, 9, 17]; 4270 let Latency = 25; 4271 let NumMicroOps = 37; 4272} 4273def : InstRW<[SPRWriteResGroup454], (instrs VPCONFLICTDZrrk)>; 4274 4275def SPRWriteResGroup455 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4276 let ReleaseAtCycles = [1, 1, 2]; 4277 let Latency = 11; 4278 let NumMicroOps = 4; 4279} 4280def : InstRW<[SPRWriteResGroup455], (instregex "^VPCONFLICTQZ128rm((b|k|bk|kz)?)$")>; 4281def : InstRW<[SPRWriteResGroup455], (instrs VPCONFLICTQZ128rmbkz)>; 4282def : InstRW<[SPRWriteResGroup455, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ128rm$")>; 4283 4284def SPRWriteResGroup456 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> { 4285 let ReleaseAtCycles = [1, 2]; 4286 let Latency = 4; 4287 let NumMicroOps = 3; 4288} 4289def : InstRW<[SPRWriteResGroup456], (instregex "^VPCONFLICTQZ128rr((k|kz)?)$")>; 4290 4291def SPRWriteResGroup457 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4292 let ReleaseAtCycles = [5, 4, 1, 5]; 4293 let Latency = 20; 4294 let NumMicroOps = 15; 4295} 4296def : InstRW<[SPRWriteResGroup457], (instregex "^VPCONFLICTQZ256rm((b|k|bk|kz)?)$")>; 4297def : InstRW<[SPRWriteResGroup457], (instrs VPCONFLICTQZ256rmbkz)>; 4298 4299def SPRWriteResGroup458 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> { 4300 let ReleaseAtCycles = [5, 5, 5]; 4301 let Latency = 13; 4302 let NumMicroOps = 15; 4303} 4304def : InstRW<[SPRWriteResGroup458], (instregex "^VPCONFLICTQZ256rr((k|kz)?)$")>; 4305 4306def SPRWriteResGroup459 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4307 let ReleaseAtCycles = [7, 5, 1, 9]; 4308 let Latency = 23; 4309 let NumMicroOps = 22; 4310} 4311def : InstRW<[SPRWriteResGroup459], (instregex "^VPCONFLICTQZrm((b|k|bk|kz)?)$")>; 4312def : InstRW<[SPRWriteResGroup459], (instrs VPCONFLICTQZrmbkz)>; 4313 4314def SPRWriteResGroup460 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 4315 let ReleaseAtCycles = [7, 6, 9]; 4316 let Latency = 17; 4317 let NumMicroOps = 22; 4318} 4319def : InstRW<[SPRWriteResGroup460], (instregex "^VPCONFLICTQZrr((kz)?)$")>; 4320 4321def SPRWriteResGroup461 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> { 4322 let ReleaseAtCycles = [7, 6, 9]; 4323 let Latency = 16; 4324 let NumMicroOps = 22; 4325} 4326def : InstRW<[SPRWriteResGroup461], (instrs VPCONFLICTQZrrk)>; 4327 4328def SPRWriteResGroup462 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4329 let ReleaseAtCycles = [1, 1, 2]; 4330 let Latency = 13; 4331 let NumMicroOps = 4; 4332} 4333def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ128rmk(z?)$")>; 4334def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instrs VPERMT2WZ128rm)>; 4335 4336def SPRWriteResGroup463 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> { 4337 let ReleaseAtCycles = [1, 2]; 4338 let Latency = 5; 4339 let NumMicroOps = 3; 4340} 4341def : InstRW<[SPRWriteResGroup463], (instregex "^VPERM(I|T)2BZ(128|256)rr$")>; 4342 4343def SPRWriteResGroup464 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> { 4344 let ReleaseAtCycles = [1, 2]; 4345 let Latency = 7; 4346 let NumMicroOps = 3; 4347} 4348def : InstRW<[SPRWriteResGroup464], (instregex "^VPERM(I|T)2BZ(128|256)rrk(z?)$", 4349 "^VPERM(I|T)2WZ(128|256)rr$")>; 4350 4351def SPRWriteResGroup465 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4352 let ReleaseAtCycles = [1, 1, 2]; 4353 let Latency = 12; 4354 let NumMicroOps = 4; 4355} 4356def : InstRW<[SPRWriteResGroup465, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ256rm$")>; 4357 4358def SPRWriteResGroup466 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4359 let ReleaseAtCycles = [1, 1, 2]; 4360 let Latency = 14; 4361 let NumMicroOps = 4; 4362} 4363def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ256rmk(z?)$")>; 4364def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instrs VPERMI2WZ128rm, 4365 VPERMT2WZ256rm)>; 4366 4367def SPRWriteResGroup467 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4368 let ReleaseAtCycles = [1, 1, 2]; 4369 let Latency = 12; 4370 let NumMicroOps = 4; 4371} 4372def : InstRW<[SPRWriteResGroup467, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZrm$")>; 4373 4374def SPRWriteResGroup468 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4375 let ReleaseAtCycles = [1, 1, 2]; 4376 let Latency = 14; 4377 let NumMicroOps = 4; 4378} 4379def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZrmk(z?)$")>; 4380def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instrs VPERMT2WZrm)>; 4381 4382def SPRWriteResGroup469 : SchedWriteRes<[SPRPort00_05, SPRPort05]> { 4383 let ReleaseAtCycles = [1, 2]; 4384 let Latency = 5; 4385 let NumMicroOps = 3; 4386} 4387def : InstRW<[SPRWriteResGroup469], (instregex "^VPERM(I|T)2BZrr$")>; 4388 4389def SPRWriteResGroup470 : SchedWriteRes<[SPRPort00_05, SPRPort05]> { 4390 let ReleaseAtCycles = [1, 2]; 4391 let Latency = 7; 4392 let NumMicroOps = 3; 4393} 4394def : InstRW<[SPRWriteResGroup470], (instregex "^VPERM(I|T)2BZrrk(z?)$", 4395 "^VPERM(I|T)2WZrr$")>; 4396 4397def SPRWriteResGroup471 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4398 let ReleaseAtCycles = [1, 1, 2]; 4399 let Latency = 16; 4400 let NumMicroOps = 4; 4401} 4402def : InstRW<[SPRWriteResGroup471, ReadAfterVecYLd], (instregex "^VPERMI2WZ128rmk(z?)$", 4403 "^VPERMT2WZ256rmk(z?)$")>; 4404 4405def SPRWriteResGroup472 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> { 4406 let ReleaseAtCycles = [1, 2]; 4407 let Latency = 9; 4408 let NumMicroOps = 3; 4409} 4410def : InstRW<[SPRWriteResGroup472], (instregex "^VPERM(I|T)2WZ(128|256)rrk(z?)$")>; 4411 4412def SPRWriteResGroup473 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4413 let ReleaseAtCycles = [1, 1, 2]; 4414 let Latency = 15; 4415 let NumMicroOps = 4; 4416} 4417def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instregex "^VPERMT2WZ128rmk(z?)$")>; 4418def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instrs VPERMI2WZ256rm)>; 4419 4420def SPRWriteResGroup474 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_10, SPRPort05]> { 4421 let ReleaseAtCycles = [1, 1, 2]; 4422 let Latency = 17; 4423 let NumMicroOps = 4; 4424} 4425def : InstRW<[SPRWriteResGroup474, ReadAfterVecYLd], (instregex "^VPERMI2WZ256rmk(z?)$")>; 4426 4427def SPRWriteResGroup475 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4428 let ReleaseAtCycles = [1, 1, 2]; 4429 let Latency = 15; 4430 let NumMicroOps = 4; 4431} 4432def : InstRW<[SPRWriteResGroup475, ReadAfterVecYLd], (instrs VPERMI2WZrm)>; 4433 4434def SPRWriteResGroup476 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4435 let ReleaseAtCycles = [1, 1, 2]; 4436 let Latency = 17; 4437 let NumMicroOps = 4; 4438} 4439def : InstRW<[SPRWriteResGroup476, ReadAfterVecYLd], (instregex "^VPERMI2WZrmk(z?)$")>; 4440 4441def SPRWriteResGroup477 : SchedWriteRes<[SPRPort00_05, SPRPort05]> { 4442 let ReleaseAtCycles = [1, 2]; 4443 let Latency = 9; 4444 let NumMicroOps = 3; 4445} 4446def : InstRW<[SPRWriteResGroup477], (instregex "^VPERM(I|T)2WZrrk(z?)$")>; 4447 4448def SPRWriteResGroup478 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_10, SPRPort05]> { 4449 let ReleaseAtCycles = [1, 1, 2]; 4450 let Latency = 16; 4451 let NumMicroOps = 4; 4452} 4453def : InstRW<[SPRWriteResGroup478, ReadAfterVecYLd], (instregex "^VPERMT2WZrmk(z?)$")>; 4454 4455def SPRWriteResGroup479 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 4456 let Latency = 10; 4457 let NumMicroOps = 3; 4458} 4459def : InstRW<[SPRWriteResGroup479, ReadAfterVecYLd], (instrs VPERMWZ128rm)>; 4460 4461def SPRWriteResGroup480 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 4462 let Latency = 13; 4463 let NumMicroOps = 3; 4464} 4465def : InstRW<[SPRWriteResGroup480, ReadAfterVecYLd], (instregex "^VPERMWZ(128|256)rmk(z?)$")>; 4466 4467def SPRWriteResGroup481 : SchedWriteRes<[SPRPort00_01, SPRPort05]> { 4468 let Latency = 4; 4469 let NumMicroOps = 2; 4470} 4471def : InstRW<[SPRWriteResGroup481], (instregex "^VPERMWZ(128|256)rr$")>; 4472 4473def SPRWriteResGroup482 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10, SPRPort05]> { 4474 let Latency = 11; 4475 let NumMicroOps = 3; 4476} 4477def : InstRW<[SPRWriteResGroup482, ReadAfterVecYLd], (instrs VPERMWZ256rm)>; 4478 4479def SPRWriteResGroup483 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 4480 let Latency = 11; 4481 let NumMicroOps = 3; 4482} 4483def : InstRW<[SPRWriteResGroup483, ReadAfterVecYLd], (instrs VPERMWZrm)>; 4484 4485def SPRWriteResGroup484 : SchedWriteRes<[SPRPort05]> { 4486 let ReleaseAtCycles = [2]; 4487 let Latency = 8; 4488 let NumMicroOps = 2; 4489} 4490def : InstRW<[SPRWriteResGroup484], (instregex "^VPEXPAND(B|W)Z(128|256)rrk(z?)$", 4491 "^VPEXPAND(B|W)Zrrk(z?)$")>; 4492 4493def SPRWriteResGroup485 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_10]> { 4494 let ReleaseAtCycles = [1, 2, 1]; 4495 let Latency = 10; 4496 let NumMicroOps = 4; 4497} 4498def : InstRW<[SPRWriteResGroup485, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>; 4499 4500def SPRWriteResGroup486 : SchedWriteRes<[SPRPort00_01]> { 4501 let Latency = 7; 4502} 4503def : InstRW<[SPRWriteResGroup486], (instregex "^VPMADDUBSWZ(128|256)rrk(z?)$", 4504 "^VPMULH((U|RS)?)WZ(128|256)rrk(z?)$", 4505 "^VPMULLWZ(128|256)rrk(z?)$")>; 4506 4507def SPRWriteResGroup487 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4508 let Latency = 14; 4509 let NumMicroOps = 2; 4510} 4511def : InstRW<[SPRWriteResGroup487, ReadAfterVecYLd], (instregex "^VPMADDUBSWZrmk(z?)$", 4512 "^VPMULH((U|RS)?)WZrmk(z?)$", 4513 "^VPMULLWZrmk(z?)$")>; 4514 4515def SPRWriteResGroup488 : SchedWriteRes<[SPRPort00]> { 4516 let Latency = 7; 4517} 4518def : InstRW<[SPRWriteResGroup488], (instregex "^VPMADDUBSWZrrk(z?)$", 4519 "^VPMULH((U|RS)?)WZrrk(z?)$", 4520 "^VPMULLWZrrk(z?)$")>; 4521 4522def SPRWriteResGroup489 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4523 let Latency = 12; 4524 let NumMicroOps = 4; 4525} 4526def : InstRW<[SPRWriteResGroup489], (instregex "^VPMOV((US)?)DBZ(128|256)mr$", 4527 "^VPMOV((S|US)?)(D|Q)WZ(128|256)mr$", 4528 "^VPMOV(Q|W|SD|SW)BZ256mr$", 4529 "^VPMOV(W|SD)BZ128mr$", 4530 "^VPMOV(U?)SQBZ256mr$", 4531 "^VPMOV(U?)SQDZ(128|256)mr$", 4532 "^VPMOV(U?)SWBZ128mr$")>; 4533def : InstRW<[SPRWriteResGroup489], (instrs VPMOVUSWBZ256mr)>; 4534 4535def SPRWriteResGroup490 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4536 let Latency = 13; 4537 let NumMicroOps = 4; 4538} 4539def : InstRW<[SPRWriteResGroup490], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128mrk$", 4540 "^VPMOV((S|US)?)(D|Q)WZ128mrk$", 4541 "^VPMOV(U?)S(DB|QD)Z128mrk$", 4542 "^VPMOVUS(Q|W)BZ128mrk$")>; 4543 4544def SPRWriteResGroup491 : SchedWriteRes<[SPRPort01_05, SPRPort05]> { 4545 let Latency = 2; 4546 let NumMicroOps = 2; 4547} 4548def : InstRW<[SPRWriteResGroup491], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128rr$", 4549 "^VPMOV((S|US)?)(D|Q)WZ128rr$", 4550 "^VPMOV(U?)S(DB|QD)Z128rr$", 4551 "^VPMOV(U?)SQDZ128rrk(z?)$", 4552 "^VPMOVUS(Q|W)BZ128rr$")>; 4553 4554def SPRWriteResGroup492 : SchedWriteRes<[SPRPort01_05, SPRPort05]> { 4555 let Latency = 4; 4556 let NumMicroOps = 2; 4557} 4558def : InstRW<[SPRWriteResGroup492], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128rrk(z?)$", 4559 "^VPMOV(D|Q|W|SQ|SW)BZ256rr$", 4560 "^VPMOV((S|US)?)(D|Q)WZ128rrk(z?)$", 4561 "^VPMOV((S|US)?)(D|Q)WZ256rr$", 4562 "^VPMOV(U?)SDBZ128rrk(z?)$", 4563 "^VPMOV(U?)S(DB|QD)Z256rr$", 4564 "^VPMOV(U?)SQDZ256rrk(z?)$", 4565 "^VPMOVUS(Q|W)BZ128rrk(z?)$", 4566 "^VPMOVUS(Q|W)BZ256rr$")>; 4567 4568def SPRWriteResGroup493 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4569 let Latency = 15; 4570 let NumMicroOps = 4; 4571} 4572def : InstRW<[SPRWriteResGroup493], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ256mrk$", 4573 "^VPMOV((S|US)?)(D|Q)WZ256mrk$", 4574 "^VPMOV(U?)S(DB|QD)Z256mrk$", 4575 "^VPMOVUS(Q|W)BZ256mrk$")>; 4576 4577def SPRWriteResGroup494 : SchedWriteRes<[SPRPort01_05, SPRPort05]> { 4578 let Latency = 6; 4579 let NumMicroOps = 2; 4580} 4581def : InstRW<[SPRWriteResGroup494], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ256rrk(z?)$", 4582 "^VPMOV((S|US)?)(D|Q)WZ256rrk(z?)$", 4583 "^VPMOV(U?)SDBZ256rrk(z?)$", 4584 "^VPMOVUS(Q|W)BZ256rrk(z?)$")>; 4585 4586def SPRWriteResGroup495 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> { 4587 let Latency = 20; 4588 let NumMicroOps = 4; 4589} 4590def : InstRW<[SPRWriteResGroup495], (instregex "^VPMOV((S|US)?)QBZ128mr$")>; 4591 4592def SPRWriteResGroup496 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> { 4593 let Latency = 14; 4594 let NumMicroOps = 3; 4595} 4596def : InstRW<[SPRWriteResGroup496], (instregex "^VPMOVQDZ((256)?)mrk$")>; 4597 4598def SPRWriteResGroup497 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 4599 let ReleaseAtCycles = [3, 1]; 4600 let Latency = 23; 4601 let NumMicroOps = 4; 4602} 4603def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instregex "^VPMULLQZ128rm((b|k|bk|kz)?)$")>; 4604def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instrs VPMULLQZ128rmbkz)>; 4605def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instregex "^VPMULLQZ256rm((b|k|bk|kz)?)$")>; 4606def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instrs VPMULLQZ256rmbkz)>; 4607 4608def SPRWriteResGroup498 : SchedWriteRes<[SPRPort00_01]> { 4609 let ReleaseAtCycles = [3]; 4610 let Latency = 15; 4611 let NumMicroOps = 3; 4612} 4613def : InstRW<[SPRWriteResGroup498], (instregex "^VPMULLQZ(128|256)rr((k|kz)?)$")>; 4614 4615def SPRWriteResGroup499 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4616 let ReleaseAtCycles = [3, 1]; 4617 let Latency = 23; 4618 let NumMicroOps = 4; 4619} 4620def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instregex "^VPMULLQZrm((b|k|bk|kz)?)$")>; 4621def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instrs VPMULLQZrmbkz)>; 4622 4623def SPRWriteResGroup500 : SchedWriteRes<[SPRPort00]> { 4624 let ReleaseAtCycles = [3]; 4625 let Latency = 15; 4626 let NumMicroOps = 3; 4627} 4628def : InstRW<[SPRWriteResGroup500], (instregex "^VPMULLQZrr((k|kz)?)$")>; 4629 4630def SPRWriteResGroup501 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 4631 let ReleaseAtCycles = [1, 1, 1, 4, 4]; 4632 let Latency = 12; 4633 let NumMicroOps = 11; 4634} 4635def : InstRW<[SPRWriteResGroup501], (instregex "^VPSCATTER(D|Q)QZ256mr$", 4636 "^VSCATTER(D|Q)PDZ256mr$")>; 4637def : InstRW<[SPRWriteResGroup501], (instrs VPSCATTERDDZ128mr, 4638 VPSCATTERQDZ256mr, 4639 VSCATTERDPSZ128mr, 4640 VSCATTERQPSZ256mr)>; 4641 4642def SPRWriteResGroup502 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 4643 let ReleaseAtCycles = [1, 1, 1, 8, 8]; 4644 let Latency = 12; 4645 let NumMicroOps = 19; 4646} 4647def : InstRW<[SPRWriteResGroup502], (instrs VPSCATTERDDZ256mr, 4648 VSCATTERDPSZ256mr)>; 4649 4650def SPRWriteResGroup503 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 4651 let ReleaseAtCycles = [2, 1, 16, 16]; 4652 let Latency = 19; 4653 let NumMicroOps = 35; 4654} 4655def : InstRW<[SPRWriteResGroup503], (instrs VPSCATTERDDZmr, 4656 VSCATTERDPSZmr)>; 4657 4658def SPRWriteResGroup504 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 4659 let ReleaseAtCycles = [1, 1, 1, 2, 2]; 4660 let Latency = 12; 4661 let NumMicroOps = 7; 4662} 4663def : InstRW<[SPRWriteResGroup504], (instregex "^VPSCATTER(D|Q)QZ128mr$", 4664 "^VSCATTER(D|Q)PDZ128mr$")>; 4665def : InstRW<[SPRWriteResGroup504], (instrs VPSCATTERQDZ128mr, 4666 VSCATTERQPSZ128mr)>; 4667 4668def SPRWriteResGroup505 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_11, SPRPort04_09, SPRPort07_08]> { 4669 let ReleaseAtCycles = [2, 1, 8, 8]; 4670 let Latency = 12; 4671 let NumMicroOps = 19; 4672} 4673def : InstRW<[SPRWriteResGroup505], (instregex "^VPSCATTER(D|Q)QZmr$", 4674 "^VSCATTER(D|Q)PDZmr$")>; 4675def : InstRW<[SPRWriteResGroup505], (instrs VPSCATTERQDZmr, 4676 VSCATTERQPSZmr)>; 4677 4678def SPRWriteResGroup506 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 4679 let Latency = 8; 4680 let NumMicroOps = 2; 4681} 4682def : InstRW<[SPRWriteResGroup506, ReadAfterVecXLd], (instregex "^VPSH(L|R)D(D|Q)Z128rmbi$", 4683 "^VPSH(L|R)D(D|Q|W)Z128rmi$", 4684 "^VPSH(L|R)DV(D|Q|W)Z128m$", 4685 "^VPSH(L|R)DV(D|Q)Z128m(b|k|kz)$", 4686 "^VPSH(L|R)DV(D|Q)Z128mbk(z?)$")>; 4687 4688def SPRWriteResGroup507 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> { 4689 let Latency = 9; 4690 let NumMicroOps = 3; 4691} 4692def : InstRW<[SPRWriteResGroup507, ReadAfterVecXLd], (instregex "^VPSH(L|R)D(D|Q)Z128rm(b?)ik(z?)$")>; 4693 4694def SPRWriteResGroup508 : SchedWriteRes<[SPRPort00_01]>; 4695def : InstRW<[SPRWriteResGroup508], (instregex "^VPSH(L|R)D(D|Q|W)Z(128|256)rri$", 4696 "^VPSH(L|R)DV(D|Q|W)Z(128|256)r$", 4697 "^VPSH(L|R)DV(D|Q)Z(128|256)rk(z?)$")>; 4698 4699def SPRWriteResGroup509 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> { 4700 let Latency = 2; 4701 let NumMicroOps = 2; 4702} 4703def : InstRW<[SPRWriteResGroup509], (instregex "^VPSH(L|R)D(D|Q)Z(128|256)rrik(z?)$")>; 4704 4705def SPRWriteResGroup510 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 4706 let Latency = 9; 4707 let NumMicroOps = 2; 4708} 4709def : InstRW<[SPRWriteResGroup510, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Z256rmbi$", 4710 "^VPSH(L|R)D(D|Q|W)Z256rmi$", 4711 "^VPSH(L|R)DV(D|Q|W)Z256m$", 4712 "^VPSH(L|R)DV(D|Q)Z256m(b|k|kz)$", 4713 "^VPSH(L|R)DV(D|Q)Z256mbk(z?)$")>; 4714 4715def SPRWriteResGroup511 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> { 4716 let Latency = 10; 4717 let NumMicroOps = 3; 4718} 4719def : InstRW<[SPRWriteResGroup511, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Z256rm(b?)ik(z?)$")>; 4720 4721def SPRWriteResGroup512 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4722 let Latency = 9; 4723 let NumMicroOps = 2; 4724} 4725def : InstRW<[SPRWriteResGroup512, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Zrmbi$", 4726 "^VPSH(L|R)D(D|Q|W)Zrmi$", 4727 "^VPSH(L|R)DV(D|Q|W)Zm$", 4728 "^VPSH(L|R)DV(D|Q)Zm(b|k|kz)$", 4729 "^VPSH(L|R)DV(D|Q)Zmbk(z?)$")>; 4730 4731def SPRWriteResGroup513 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> { 4732 let Latency = 10; 4733 let NumMicroOps = 3; 4734} 4735def : InstRW<[SPRWriteResGroup513, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Zrm(b?)ik(z?)$")>; 4736 4737def SPRWriteResGroup514 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 4738 let Latency = 2; 4739 let NumMicroOps = 2; 4740} 4741def : InstRW<[SPRWriteResGroup514], (instregex "^VPSH(L|R)D(D|Q)Zrrik(z?)$")>; 4742 4743def SPRWriteResGroup515 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> { 4744 let Latency = 11; 4745 let NumMicroOps = 3; 4746} 4747def : InstRW<[SPRWriteResGroup515, ReadAfterVecXLd], (instregex "^VPSH(L|R)DWZ128rmik(z?)$")>; 4748 4749def SPRWriteResGroup516 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> { 4750 let Latency = 4; 4751 let NumMicroOps = 2; 4752} 4753def : InstRW<[SPRWriteResGroup516], (instregex "^VPSH(L|R)DWZ(128|256)rrik(z?)$")>; 4754 4755def SPRWriteResGroup517 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_10]> { 4756 let Latency = 12; 4757 let NumMicroOps = 3; 4758} 4759def : InstRW<[SPRWriteResGroup517, ReadAfterVecYLd], (instregex "^VPSH(L|R)DWZ256rmik(z?)$")>; 4760 4761def SPRWriteResGroup518 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> { 4762 let Latency = 12; 4763 let NumMicroOps = 3; 4764} 4765def : InstRW<[SPRWriteResGroup518, ReadAfterVecYLd], (instregex "^VPSH(L|R)DWZrmik(z?)$")>; 4766 4767def SPRWriteResGroup519 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 4768 let Latency = 4; 4769 let NumMicroOps = 2; 4770} 4771def : InstRW<[SPRWriteResGroup519], (instregex "^VPSH(L|R)DWZrrik(z?)$")>; 4772 4773def SPRWriteResGroup520 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 4774 let Latency = 6; 4775 let NumMicroOps = 3; 4776} 4777def : InstRW<[SPRWriteResGroup520, ReadAfterVecXLd], (instrs VPSHUFBITQMBZ128rm)>; 4778def : InstRW<[SPRWriteResGroup520, ReadAfterVecYLd], (instregex "^VPSHUFBITQMBZ((256)?)rm$")>; 4779 4780def SPRWriteResGroup521 : SchedWriteRes<[SPRPort00, SPRPort02_03_10, SPRPort05]> { 4781 let Latency = 8; 4782 let NumMicroOps = 3; 4783} 4784def : InstRW<[SPRWriteResGroup521, ReadAfterVecXLd], (instrs VPSHUFBITQMBZ128rmk)>; 4785def : InstRW<[SPRWriteResGroup521, ReadAfterVecYLd], (instregex "^VPSHUFBITQMBZ((256)?)rmk$")>; 4786 4787def SPRWriteResGroup522 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> { 4788 let Latency = 4; 4789 let NumMicroOps = 2; 4790} 4791def : InstRW<[SPRWriteResGroup522], (instregex "^VPS(L|R)LWZ128rrk(z?)$", 4792 "^VPSRAWZ128rrk(z?)$")>; 4793 4794def SPRWriteResGroup523 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> { 4795 let ReleaseAtCycles = [2, 1, 1]; 4796 let Latency = 16; 4797 let NumMicroOps = 4; 4798} 4799def : InstRW<[SPRWriteResGroup523, ReadAfterVecYLd], (instregex "^VR(CP|SQRT)PHZm(bk|kz)$", 4800 "^VR(CP|SQRT)PHZm(k|bkz)$")>; 4801 4802def SPRWriteResGroup524 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 4803 let ReleaseAtCycles = [2, 1]; 4804 let Latency = 9; 4805 let NumMicroOps = 3; 4806} 4807def : InstRW<[SPRWriteResGroup524], (instregex "^VRCPPHZrk(z?)$")>; 4808 4809def SPRWriteResGroup525 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 4810 let ReleaseAtCycles = [3, 1]; 4811 let Latency = 20; 4812 let NumMicroOps = 4; 4813} 4814def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)i$")>; 4815def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instrs VREDUCESHZrmi)>; 4816def : InstRW<[SPRWriteResGroup525, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)i$")>; 4817 4818def SPRWriteResGroup526 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 4819 let ReleaseAtCycles = [3, 1]; 4820 let Latency = 22; 4821 let NumMicroOps = 4; 4822} 4823def : InstRW<[SPRWriteResGroup526, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)ik(z?)$", 4824 "^VREDUCESHZrmik(z?)$")>; 4825def : InstRW<[SPRWriteResGroup526, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)ik(z?)$")>; 4826 4827def SPRWriteResGroup527 : SchedWriteRes<[SPRPort00_01]> { 4828 let ReleaseAtCycles = [3]; 4829 let Latency = 13; 4830 let NumMicroOps = 3; 4831} 4832def : InstRW<[SPRWriteResGroup527], (instregex "^VREDUCEPHZ(128|256)rri$", 4833 "^VREDUCESHZrri(b?)$")>; 4834 4835def SPRWriteResGroup528 : SchedWriteRes<[SPRPort00_01]> { 4836 let ReleaseAtCycles = [3]; 4837 let Latency = 16; 4838 let NumMicroOps = 3; 4839} 4840def : InstRW<[SPRWriteResGroup528], (instregex "^VREDUCEPHZ(128|256)rrik(z?)$", 4841 "^VREDUCESHZrri(bk|kz)$", 4842 "^VREDUCESHZrri(k|bkz)$")>; 4843 4844def SPRWriteResGroup529 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4845 let ReleaseAtCycles = [3, 1]; 4846 let Latency = 20; 4847 let NumMicroOps = 4; 4848} 4849def : InstRW<[SPRWriteResGroup529, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)i$")>; 4850 4851def SPRWriteResGroup530 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4852 let ReleaseAtCycles = [3, 1]; 4853 let Latency = 22; 4854 let NumMicroOps = 4; 4855} 4856def : InstRW<[SPRWriteResGroup530, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)ik(z?)$")>; 4857 4858def SPRWriteResGroup531 : SchedWriteRes<[SPRPort00]> { 4859 let ReleaseAtCycles = [3]; 4860 let Latency = 13; 4861 let NumMicroOps = 3; 4862} 4863def : InstRW<[SPRWriteResGroup531], (instregex "^VREDUCEPHZrri(b?)$")>; 4864 4865def SPRWriteResGroup532 : SchedWriteRes<[SPRPort00]> { 4866 let ReleaseAtCycles = [3]; 4867 let Latency = 16; 4868 let NumMicroOps = 3; 4869} 4870def : InstRW<[SPRWriteResGroup532], (instregex "^VREDUCEPHZrri(bk|kz)$", 4871 "^VREDUCEPHZrri(k|bkz)$")>; 4872 4873def SPRWriteResGroup533 : SchedWriteRes<[SPRPort00]> { 4874 let ReleaseAtCycles = [2]; 4875 let Latency = 8; 4876 let NumMicroOps = 2; 4877} 4878def : InstRW<[SPRWriteResGroup533], (instregex "^VRNDSCALEP(D|S)Zrri((b|k|bk|kz)?)$", 4879 "^VRNDSCALEP(D|S)Zrribkz$")>; 4880 4881def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_10]> { 4882 let ReleaseAtCycles = [2, 1]; 4883 let Latency = 17; 4884 let NumMicroOps = 3; 4885} 4886def : InstRW<[SPRWriteResGroup534, ReadAfterVecXLd], (instregex "^VRNDSCALEPHZ128rm(b?)ik(z?)$", 4887 "^VRNDSCALESHZrmik(z?)_Int$", 4888 "^VSCALEFPHZ128rm(bk|kz)$", 4889 "^VSCALEFPHZ128rm(k|bkz)$")>; 4890def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ256rm(b?)ik(z?)$", 4891 "^VSCALEFPHZ256rm(bk|kz)$", 4892 "^VSCALEFPHZ256rm(k|bkz)$")>; 4893def : InstRW<[SPRWriteResGroup534, ReadAfterVecLd], (instregex "^VSCALEFSHZrmk(z?)$")>; 4894 4895def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> { 4896 let ReleaseAtCycles = [2]; 4897 let Latency = 11; 4898 let NumMicroOps = 2; 4899} 4900def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$", 4901 "^VRNDSCALESHZrri(b?)k(z?)_Int$", 4902 "^VSCALEFPHZ(128|256)rrk(z?)$", 4903 "^VSCALEFSHZrrbk(z?)_Int$", 4904 "^VSCALEFSHZrrk(z?)$")>; 4905 4906def SPRWriteResGroup536 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4907 let ReleaseAtCycles = [2, 1]; 4908 let Latency = 17; 4909 let NumMicroOps = 3; 4910} 4911def : InstRW<[SPRWriteResGroup536, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZrm(b?)ik(z?)$", 4912 "^VSCALEFPHZrm(bk|kz)$", 4913 "^VSCALEFPHZrm(k|bkz)$")>; 4914 4915def SPRWriteResGroup537 : SchedWriteRes<[SPRPort00]> { 4916 let ReleaseAtCycles = [2]; 4917 let Latency = 11; 4918 let NumMicroOps = 2; 4919} 4920def : InstRW<[SPRWriteResGroup537], (instregex "^VRNDSCALEPHZrri(bk|kz)$", 4921 "^VRNDSCALEPHZrri(k|bkz)$", 4922 "^VSCALEFPHZrr(bk|kz)$", 4923 "^VSCALEFPHZrr(k|bkz)$")>; 4924 4925def SPRWriteResGroup538 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 4926 let ReleaseAtCycles = [2, 1]; 4927 let Latency = 6; 4928 let NumMicroOps = 3; 4929} 4930def : InstRW<[SPRWriteResGroup538], (instregex "^VRSQRT14P(D|S)Zr$")>; 4931def : InstRW<[SPRWriteResGroup538], (instrs VRSQRT14PSZrk, 4932 VRSQRTPHZr)>; 4933 4934def SPRWriteResGroup539 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4935 let Latency = 25; 4936 let NumMicroOps = 2; 4937} 4938def : InstRW<[SPRWriteResGroup539], (instrs VSQRTPDYm)>; 4939def : InstRW<[SPRWriteResGroup539, ReadAfterVecYLd], (instregex "^VSQRTPDZ256m(b?)$")>; 4940 4941def SPRWriteResGroup540 : SchedWriteRes<[SPRPort00, SPRPort02_03_10]> { 4942 let Latency = 20; 4943 let NumMicroOps = 2; 4944} 4945def : InstRW<[SPRWriteResGroup540, ReadAfterVecXLd], (instregex "^VSQRTPDZ128m(bk|kz)$", 4946 "^VSQRTPDZ128m(k|bkz)$")>; 4947def : InstRW<[SPRWriteResGroup540, ReadAfterVecLd], (instregex "^VSQRTSDZmk(z?)_Int$")>; 4948 4949def SPRWriteResGroup541 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> { 4950 let ReleaseAtCycles = [2, 1, 1]; 4951 let Latency = 38; 4952 let NumMicroOps = 4; 4953} 4954def : InstRW<[SPRWriteResGroup541, ReadAfterVecYLd], (instrs VSQRTPDZm)>; 4955 4956def SPRWriteResGroup542 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_10]> { 4957 let ReleaseAtCycles = [2, 1, 1]; 4958 let Latency = 39; 4959 let NumMicroOps = 4; 4960} 4961def : InstRW<[SPRWriteResGroup542, ReadAfterVecYLd], (instrs VSQRTPDZmb)>; 4962 4963def SPRWriteResGroup543 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 4964 let ReleaseAtCycles = [2, 1]; 4965 let Latency = 31; 4966 let NumMicroOps = 3; 4967} 4968def : InstRW<[SPRWriteResGroup543], (instrs VSQRTPDZr)>; 4969 4970def SPRWriteResGroup544 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 4971 let ReleaseAtCycles = [2, 1, 1]; 4972 let Latency = 41; 4973 let NumMicroOps = 4; 4974} 4975def : InstRW<[SPRWriteResGroup544, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(bk|kz)$", 4976 "^VSQRTPHZ128m(k|bkz)$")>; 4977 4978def SPRWriteResGroup545 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 4979 let ReleaseAtCycles = [2, 1]; 4980 let Latency = 35; 4981 let NumMicroOps = 3; 4982} 4983def : InstRW<[SPRWriteResGroup545], (instregex "^VSQRTPHZ(128|256)rk$")>; 4984def : InstRW<[SPRWriteResGroup545], (instrs VSQRTPHZ256rkz)>; 4985 4986def SPRWriteResGroup546 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> { 4987 let ReleaseAtCycles = [2, 1]; 4988 let Latency = 12; 4989 let NumMicroOps = 3; 4990} 4991def : InstRW<[SPRWriteResGroup546], (instrs VSQRTPHZ128rkz)>; 4992 4993def SPRWriteResGroup547 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 4994 let ReleaseAtCycles = [2, 1, 1]; 4995 let Latency = 40; 4996 let NumMicroOps = 4; 4997} 4998def : InstRW<[SPRWriteResGroup547, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(b?)$")>; 4999 5000def SPRWriteResGroup548 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_10]> { 5001 let ReleaseAtCycles = [2, 1, 1]; 5002 let Latency = 42; 5003 let NumMicroOps = 4; 5004} 5005def : InstRW<[SPRWriteResGroup548, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(bk|kz)$", 5006 "^VSQRTPHZ256m(k|bkz)$")>; 5007 5008def SPRWriteResGroup549 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 5009 let ReleaseAtCycles = [4, 2, 1, 1, 1]; 5010 let Latency = 53; 5011 let NumMicroOps = 9; 5012} 5013def : InstRW<[SPRWriteResGroup549, ReadAfterVecYLd], (instregex "^VSQRTPHZm(b?)$")>; 5014 5015def SPRWriteResGroup550 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_10, SPRPort05]> { 5016 let ReleaseAtCycles = [4, 2, 1, 1, 1]; 5017 let Latency = 55; 5018 let NumMicroOps = 9; 5019} 5020def : InstRW<[SPRWriteResGroup550, ReadAfterVecYLd], (instregex "^VSQRTPHZm(bk|kz)$", 5021 "^VSQRTPHZm(k|bkz)$")>; 5022 5023def SPRWriteResGroup551 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> { 5024 let ReleaseAtCycles = [4, 1, 1]; 5025 let Latency = 45; 5026 let NumMicroOps = 6; 5027} 5028def : InstRW<[SPRWriteResGroup551], (instregex "^VSQRTPHZr(b?)$")>; 5029 5030def SPRWriteResGroup552 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> { 5031 let ReleaseAtCycles = [4, 1, 1]; 5032 let Latency = 47; 5033 let NumMicroOps = 6; 5034} 5035def : InstRW<[SPRWriteResGroup552], (instregex "^VSQRTPHZr(bk|kz)$", 5036 "^VSQRTPHZr(k|bkz)$")>; 5037 5038def SPRWriteResGroup553 : SchedWriteRes<[SPRPort00, SPRPort00_05]> { 5039 let ReleaseAtCycles = [2, 1]; 5040 let Latency = 19; 5041 let NumMicroOps = 3; 5042} 5043def : InstRW<[SPRWriteResGroup553], (instrs VSQRTPSZr)>; 5044 5045def SPRWriteResGroup554 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort01_05_11]> { 5046 let ReleaseAtCycles = [1, 2, 3, 3, 1]; 5047 let Latency = 12; 5048 let NumMicroOps = 10; 5049} 5050def : InstRW<[SPRWriteResGroup554], (instrs VZEROALL)>; 5051 5052def SPRWriteResGroup555 : SchedWriteRes<[SPRPort00_01_05_06]> { 5053 let ReleaseAtCycles = [2]; 5054 let Latency = 2; 5055 let NumMicroOps = 2; 5056} 5057def : InstRW<[SPRWriteResGroup555], (instrs WAIT)>; 5058 5059def SPRWriteResGroup556 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5060 let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1]; 5061 let Latency = SapphireRapidsModel.MaxLatency; 5062 let NumMicroOps = 144; 5063} 5064def : InstRW<[SPRWriteResGroup556], (instrs WRMSR)>; 5065 5066def SPRWriteResGroup557 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06, SPRPort01, SPRPort05]> { 5067 let ReleaseAtCycles = [2, 1, 4, 1]; 5068 let Latency = SapphireRapidsModel.MaxLatency; 5069 let NumMicroOps = 8; 5070} 5071def : InstRW<[SPRWriteResGroup557], (instrs WRPKRUr)>; 5072 5073def SPRWriteResGroup558 : SchedWriteRes<[SPRPort00_01_05_06_11]> { 5074 let ReleaseAtCycles = [2]; 5075 let Latency = 12; 5076 let NumMicroOps = 2; 5077} 5078def : InstRW<[SPRWriteResGroup558, WriteRMW], (instregex "^XADD(16|32|64)rm$")>; 5079 5080def SPRWriteResGroup559 : SchedWriteRes<[SPRPort00_01_05_06_11]> { 5081 let ReleaseAtCycles = [2]; 5082 let Latency = 13; 5083 let NumMicroOps = 2; 5084} 5085def : InstRW<[SPRWriteResGroup559, WriteRMW], (instrs XADD8rm)>; 5086 5087def SPRWriteResGroup560 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 5088 let ReleaseAtCycles = [4, 1]; 5089 let Latency = 39; 5090 let NumMicroOps = 5; 5091} 5092def : InstRW<[SPRWriteResGroup560, WriteRMW], (instregex "^XCHG(16|32)rm$")>; 5093 5094def SPRWriteResGroup561 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 5095 let ReleaseAtCycles = [5, 1]; 5096 let Latency = 39; 5097 let NumMicroOps = 6; 5098} 5099def : InstRW<[SPRWriteResGroup561, WriteRMW], (instrs XCHG64rm)>; 5100 5101def SPRWriteResGroup562 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 5102 let ReleaseAtCycles = [4, 1]; 5103 let Latency = 40; 5104 let NumMicroOps = 5; 5105} 5106def : InstRW<[SPRWriteResGroup562, WriteRMW], (instrs XCHG8rm)>; 5107 5108def SPRWriteResGroup563 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_05, SPRPort01, SPRPort05, SPRPort06]> { 5109 let ReleaseAtCycles = [2, 4, 2, 1, 2, 4]; 5110 let Latency = 17; 5111 let NumMicroOps = 15; 5112} 5113def : InstRW<[SPRWriteResGroup563], (instrs XCH_F)>; 5114 5115def SPRWriteResGroup564 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01]> { 5116 let ReleaseAtCycles = [7, 3, 8, 5]; 5117 let Latency = 4; 5118 let NumMicroOps = 23; 5119} 5120def : InstRW<[SPRWriteResGroup564], (instrs XGETBV)>; 5121 5122def SPRWriteResGroup565 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort02_03_10]> { 5123 let ReleaseAtCycles = [2, 1]; 5124 let Latency = 7; 5125 let NumMicroOps = 3; 5126} 5127def : InstRW<[SPRWriteResGroup565], (instrs XLAT)>; 5128 5129def SPRWriteResGroup566 : SchedWriteRes<[SPRPort01, SPRPort02_03, SPRPort02_03_10, SPRPort06]> { 5130 let ReleaseAtCycles = [1, 21, 1, 8]; 5131 let Latency = 37; 5132 let NumMicroOps = 31; 5133} 5134def : InstRW<[SPRWriteResGroup566], (instregex "^XRSTOR((S|64)?)$")>; 5135def : InstRW<[SPRWriteResGroup566], (instrs XRSTORS64)>; 5136 5137def SPRWriteResGroup567 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5138 let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1]; 5139 let Latency = 42; 5140 let NumMicroOps = 140; 5141} 5142def : InstRW<[SPRWriteResGroup567], (instrs XSAVE)>; 5143 5144def SPRWriteResGroup568 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5145 let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1]; 5146 let Latency = 41; 5147 let NumMicroOps = 140; 5148} 5149def : InstRW<[SPRWriteResGroup568], (instrs XSAVE64)>; 5150 5151def SPRWriteResGroup569 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5152 let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2]; 5153 let Latency = 42; 5154 let NumMicroOps = 151; 5155} 5156def : InstRW<[SPRWriteResGroup569], (instrs XSAVEC)>; 5157 5158def SPRWriteResGroup570 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5159 let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2]; 5160 let Latency = 42; 5161 let NumMicroOps = 152; 5162} 5163def : InstRW<[SPRWriteResGroup570], (instrs XSAVEC64)>; 5164 5165def SPRWriteResGroup571 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5166 let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1]; 5167 let Latency = 42; 5168 let NumMicroOps = 155; 5169} 5170def : InstRW<[SPRWriteResGroup571], (instrs XSAVEOPT)>; 5171 5172def SPRWriteResGroup572 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5173 let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1]; 5174 let Latency = 42; 5175 let NumMicroOps = 156; 5176} 5177def : InstRW<[SPRWriteResGroup572], (instrs XSAVEOPT64)>; 5178 5179def SPRWriteResGroup573 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5180 let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2]; 5181 let Latency = 42; 5182 let NumMicroOps = 184; 5183} 5184def : InstRW<[SPRWriteResGroup573], (instrs XSAVES)>; 5185 5186def SPRWriteResGroup574 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_10, SPRPort04_09, SPRPort05, SPRPort07_08]> { 5187 let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2]; 5188 let Latency = 42; 5189 let NumMicroOps = 186; 5190} 5191def : InstRW<[SPRWriteResGroup574], (instrs XSAVES64)>; 5192 5193def SPRWriteResGroup575 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_11, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_11, SPRPort05]> { 5194 let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2]; 5195 let Latency = 5; 5196 let NumMicroOps = 54; 5197} 5198def : InstRW<[SPRWriteResGroup575], (instrs XSETBV)>; 5199 5200def SPRWriteResGroup576 : SchedWriteRes<[SPRPort00_01_05_06_11, SPRPort00_06]> { 5201 let ReleaseAtCycles = [2, 1]; 5202 let Latency = SapphireRapidsModel.MaxLatency; 5203 let NumMicroOps = 3; 5204} 5205def : InstRW<[SPRWriteResGroup576], (instrs XTEST)>; 5206 5207} 5208