1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Broadwell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def BroadwellModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4 16 // instructions per cycle. 17 let IssueWidth = 4; 18 let MicroOpBufferSize = 192; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 16; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = BroadwellModel in { 31 32// Broadwell can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def BWPort0 : ProcResource<1>; 41def BWPort1 : ProcResource<1>; 42def BWPort2 : ProcResource<1>; 43def BWPort3 : ProcResource<1>; 44def BWPort4 : ProcResource<1>; 45def BWPort5 : ProcResource<1>; 46def BWPort6 : ProcResource<1>; 47def BWPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; 51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; 52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; 53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; 54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; 55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; 56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; 57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; 58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; 59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; 60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; 61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; 62 63// 60 Entry Unified Scheduler 64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, 65 BWPort5, BWPort6, BWPort7]> { 66 let BufferSize=60; 67} 68 69// Integer division issued on port 0. 70def BWDivider : ProcResource<1>; 71// FP division and sqrt on port 0. 72def BWFPDivider : ProcResource<1>; 73 74// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 75// cycles after the memory operand. 76def : ReadAdvance<ReadAfterLd, 5>; 77 78// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available 79// until 5/5/6 cycles after the memory operand. 80def : ReadAdvance<ReadAfterVecLd, 5>; 81def : ReadAdvance<ReadAfterVecXLd, 5>; 82def : ReadAdvance<ReadAfterVecYLd, 6>; 83 84def : ReadAdvance<ReadInt2Fpu, 0>; 85 86// Many SchedWrites are defined in pairs with and without a folded load. 87// Instructions with folded loads are usually micro-fused, so they only appear 88// as two micro-ops when queued in the reservation station. 89// This multiclass defines the resource usage for variants with and without 90// folded loads. 91multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW, 92 list<ProcResourceKind> ExePorts, 93 int Lat, list<int> Res = [1], int UOps = 1, 94 int LoadLat = 5, int LoadUOps = 1> { 95 // Register variant is using a single cycle on ExePort. 96 def : WriteRes<SchedRW, ExePorts> { 97 let Latency = Lat; 98 let ReleaseAtCycles = Res; 99 let NumMicroOps = UOps; 100 } 101 102 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 103 // the latency (default = 5). 104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> { 105 let Latency = !add(Lat, LoadLat); 106 let ReleaseAtCycles = !listconcat([1], Res); 107 let NumMicroOps = !add(UOps, LoadUOps); 108 } 109} 110 111// A folded store needs a cycle on port 4 for the store data, and an extra port 112// 2/3/7 cycle to recompute the address. 113def : WriteRes<WriteRMW, [BWPort237,BWPort4]>; 114 115// Loads, stores, and moves, not folded with other operations. 116// Store_addr on 237. 117// Store_data on 4. 118defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>; 119defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>; 120defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>; 121defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>; 122 123// Treat misc copies as a move. 124def : InstRW<[WriteMove], (instrs COPY)>; 125 126// Idioms that clear a register, like xorps %xmm0, %xmm0. 127// These can often bypass execution ports completely. 128def : WriteRes<WriteZero, []>; 129 130// Model the effect of clobbering the read-write mask operand of the GATHER operation. 131// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 132defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 133 134// Arithmetic. 135defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op. 136defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op. 137 138// Integer multiplication. 139defm : BWWriteResPair<WriteIMul8, [BWPort1], 3>; 140defm : BWWriteResPair<WriteIMul16, [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>; 141defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>; 142defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>; 143defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>; 144defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>; 145defm : BWWriteResPair<WriteMULX32, [BWPort1,BWPort06,BWPort0156], 3, [1,1,1], 3>; 146defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>; 147defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>; 148defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>; 149defm : BWWriteResPair<WriteMULX64, [BWPort1,BWPort5], 3, [1,1], 2>; 150defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>; 151defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>; 152def BWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 153def : WriteRes<WriteIMulHLd, []> { 154 let Latency = !add(BWWriteIMulH.Latency, BroadwellModel.LoadLatency); 155} 156 157defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>; 158defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>; 159defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>; 160defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>; 161defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>; 162 163// Integer shifts and rotates. 164defm : BWWriteResPair<WriteShift, [BWPort06], 1>; 165defm : BWWriteResPair<WriteShiftCL, [BWPort06], 3, [3], 3>; 166defm : BWWriteResPair<WriteRotate, [BWPort06], 1, [1], 1>; 167defm : BWWriteResPair<WriteRotateCL, [BWPort06], 3, [3], 3>; 168 169// SHLD/SHRD. 170defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>; 171defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>; 172defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>; 173defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>; 174 175// Branches don't produce values, so they have no latency, but they still 176// consume resources. Indirect branches can fold loads. 177defm : BWWriteResPair<WriteJump, [BWPort06], 1>; 178 179defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>; 180 181defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move. 182defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move. 183 184def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc. 185def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> { 186 let Latency = 2; 187 let NumMicroOps = 3; 188} 189 190defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>; 191defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs 192defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>; 193defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>; 194defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs 195defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>; 196defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>; 197 198// This is for simple LEAs with one or two input operands. 199// The complex ones can only execute on port 1, and they require two cycles on 200// the port to read all inputs. We don't model that. 201def : WriteRes<WriteLEA, [BWPort15]>; 202 203// Bit counts. 204defm : BWWriteResPair<WriteBSF, [BWPort1], 3>; 205defm : BWWriteResPair<WriteBSR, [BWPort1], 3>; 206defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>; 207defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>; 208defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>; 209 210// BMI1 BEXTR/BLS, BMI2 BZHI 211defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>; 212defm : BWWriteResPair<WriteBLS, [BWPort15], 1>; 213defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>; 214 215// TODO: Why isn't the BWDivider used consistently? 216defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>; 217defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 218defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 219defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 220defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 221defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 222defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 223defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 224 225defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>; 226defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>; 227defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>; 228defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>; 229defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 230defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 231defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 232defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 233 234// Floating point. This covers both scalar and vector operations. 235defm : X86WriteRes<WriteFLD0, [BWPort01], 1, [1], 1>; 236defm : X86WriteRes<WriteFLD1, [BWPort01], 1, [2], 2>; 237defm : X86WriteRes<WriteFLDC, [BWPort01], 1, [2], 2>; 238defm : X86WriteRes<WriteFLoad, [BWPort23], 5, [1], 1>; 239defm : X86WriteRes<WriteFLoadX, [BWPort23], 5, [1], 1>; 240defm : X86WriteRes<WriteFLoadY, [BWPort23], 6, [1], 1>; 241defm : X86WriteRes<WriteFMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 242defm : X86WriteRes<WriteFMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 243defm : X86WriteRes<WriteFStore, [BWPort237,BWPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 246defm : X86WriteRes<WriteFStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 247defm : X86WriteRes<WriteFStoreNTX, [BWPort237,BWPort4], 1, [1,1], 2>; 248defm : X86WriteRes<WriteFStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 249 250defm : X86WriteRes<WriteFMaskedStore32, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 251defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 252defm : X86WriteRes<WriteFMaskedStore64, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 253defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 254 255defm : X86WriteRes<WriteFMove, [BWPort5], 1, [1], 1>; 256defm : X86WriteRes<WriteFMoveX, [BWPort5], 1, [1], 1>; 257defm : X86WriteRes<WriteFMoveY, [BWPort5], 1, [1], 1>; 258defm : X86WriteResUnsupported<WriteFMoveZ>; 259defm : X86WriteRes<WriteEMMS, [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>; 260 261defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub. 262defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM). 263defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM). 264defm : X86WriteResPairUnsupported<WriteFAddZ>; 265defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub. 266defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM). 267defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM). 268defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 269 270defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare. 271defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM). 272defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM). 273defm : X86WriteResPairUnsupported<WriteFCmpZ>; 274defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare. 275defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM). 276defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM). 277defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 278 279defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags (X87). 280defm : BWWriteResPair<WriteFComX, [BWPort1], 3>; // Floating point compare to flags (SSE). 281 282defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication. 283defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM). 284defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM). 285defm : X86WriteResPairUnsupported<WriteFMulZ>; 286defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication. 287defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM). 288defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM). 289defm : X86WriteResPairUnsupported<WriteFMul64Z>; 290 291//defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division. 292defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM). 293defm : BWWriteResPair<WriteFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM). 294defm : X86WriteResPairUnsupported<WriteFDivZ>; 295//defm : BWWriteResPair<WriteFDiv64, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division. 296defm : BWWriteResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM). 297defm : BWWriteResPair<WriteFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM). 298defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 299 300defm : BWWriteResPair<WriteFRcp, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate. 301defm : BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM). 302defm : BWWriteResPair<WriteFRcpY, [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM). 303defm : X86WriteResPairUnsupported<WriteFRcpZ>; 304 305defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate. 306defm : BWWriteResPair<WriteFRsqrtX,[BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM). 307defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM). 308defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 309 310defm : X86WriteRes<WriteFSqrt, [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root. 311defm : X86WriteRes<WriteFSqrtLd, [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>; 312defm : BWWriteResPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM). 313defm : BWWriteResPair<WriteFSqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM). 314defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 315defm : X86WriteRes<WriteFSqrt64, [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root. 316defm : X86WriteRes<WriteFSqrt64Ld, [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>; 317defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM). 318defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM). 319defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 320defm : BWWriteResPair<WriteFSqrt80, [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root. 321 322defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add. 323defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM). 324defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM). 325defm : X86WriteResPairUnsupported<WriteFMAZ>; 326defm : BWWriteResPair<WriteDPPD, [BWPort0,BWPort1,BWPort5], 9, [1,1,1], 3, 5>; // Floating point double dot product. 327defm : X86WriteRes<WriteDPPS, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4>; 328defm : X86WriteRes<WriteDPPSY, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4>; 329defm : X86WriteRes<WriteDPPSLd, [BWPort0,BWPort1,BWPort5,BWPort06,BWPort23], 19, [2,1,1,1,1], 6>; 330defm : X86WriteRes<WriteDPPSYLd, [BWPort0,BWPort1,BWPort5,BWPort06,BWPort23], 20, [2,1,1,1,1], 6>; 331defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs. 332defm : BWWriteResPair<WriteFRnd, [BWPort1], 6, [2], 2, 5>; // Floating point rounding. 333defm : BWWriteResPair<WriteFRndY, [BWPort1], 6, [2], 2, 6>; // Floating point rounding (YMM/ZMM). 334defm : X86WriteResPairUnsupported<WriteFRndZ>; 335defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals. 336defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM). 337defm : X86WriteResPairUnsupported<WriteFLogicZ>; 338defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions. 339defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM). 340defm : X86WriteResPairUnsupported<WriteFTestZ>; 341defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles. 342defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM). 343defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 344defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles. 345defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 346defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 347defm : BWWriteResPair<WriteFBlend, [BWPort015], 1, [1], 1, 5>; // Floating point vector blends. 348defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends. 349defm : X86WriteResPairUnsupported<WriteFBlendZ>; 350defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles. 351defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles. 352defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends. 353defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends. 354defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 355 356// FMA Scheduling helper class. 357// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 358 359// Conversion between integer and float. 360defm : BWWriteResPair<WriteCvtSS2I, [BWPort1,BWPort0], 4, [1,1], 2, 5>; 361defm : BWWriteResPair<WriteCvtPS2I, [BWPort1], 3, [1], 1, 5>; 362defm : BWWriteResPair<WriteCvtPS2IY, [BWPort1], 3, [1], 1, 6>; 363defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 364defm : BWWriteResPair<WriteCvtSD2I, [BWPort1,BWPort0], 4, [1,1], 2, 5>; 365defm : BWWriteResPair<WriteCvtPD2I, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 366defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1,BWPort5], 6, [1,1], 2, 6>; 367defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 368 369defm : X86WriteRes<WriteCvtI2SS, [BWPort1,BWPort5], 4, [1,1], 2>; 370defm : X86WriteRes<WriteCvtI2PS, [BWPort1], 3, [1], 1>; 371defm : X86WriteRes<WriteCvtI2PSY, [BWPort1], 3, [1], 1>; 372defm : X86WriteRes<WriteCvtI2SSLd, [BWPort1,BWPort23], 9, [1,1], 2>; 373defm : X86WriteRes<WriteCvtI2PSLd, [BWPort1,BWPort23], 8, [1,1], 2>; 374defm : X86WriteRes<WriteCvtI2PSYLd, [BWPort1,BWPort23], 9, [1,1], 2>; 375defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 376defm : X86WriteRes<WriteCvtI2SD, [BWPort1,BWPort5], 4, [1,1], 2>; 377defm : X86WriteRes<WriteCvtI2PD, [BWPort1,BWPort5], 4, [1,1], 2>; 378defm : X86WriteRes<WriteCvtI2PDY, [BWPort1,BWPort5], 6, [1,1], 2>; 379defm : X86WriteRes<WriteCvtI2SDLd, [BWPort1,BWPort23], 9, [1,1], 2>; 380defm : X86WriteRes<WriteCvtI2PDLd, [BWPort1,BWPort23], 9, [1,1], 2>; 381defm : X86WriteRes<WriteCvtI2PDYLd, [BWPort1,BWPort23],11, [1,1], 2>; 382defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 383 384defm : X86WriteRes<WriteCvtSS2SD, [BWPort0,BWPort5], 2, [1,1], 2>; 385defm : X86WriteRes<WriteCvtPS2PD, [BWPort0,BWPort5], 2, [1,1], 2>; 386defm : X86WriteRes<WriteCvtPS2PDY, [BWPort0,BWPort5], 4, [1,1], 2>; 387defm : X86WriteRes<WriteCvtSS2SDLd, [BWPort0,BWPort23], 6, [1,1], 2>; 388defm : X86WriteRes<WriteCvtPS2PDLd, [BWPort0,BWPort23], 6, [1,1], 2>; 389defm : X86WriteRes<WriteCvtPS2PDYLd, [BWPort0,BWPort23], 9, [1,1], 2>; 390defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 391defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 392defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 393defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1,BWPort5], 6, [1,1], 2, 6>; 394defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 395 396defm : X86WriteRes<WriteCvtPH2PS, [BWPort1,BWPort5], 2, [1,1], 2>; 397defm : X86WriteRes<WriteCvtPH2PSY, [BWPort1,BWPort5], 2, [1,1], 2>; 398defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 399defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort1,BWPort23], 6, [1,1], 2>; 400defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort1,BWPort23], 6, [1,1], 2>; 401defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 402 403defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>; 404defm : X86WriteRes<WriteCvtPS2PHY, [BWPort1,BWPort5], 6, [1,1], 2>; 405defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 406defm : X86WriteRes<WriteCvtPS2PHSt, [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>; 407defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>; 408defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 409 410// Vector integer operations. 411defm : X86WriteRes<WriteVecLoad, [BWPort23], 5, [1], 1>; 412defm : X86WriteRes<WriteVecLoadX, [BWPort23], 5, [1], 1>; 413defm : X86WriteRes<WriteVecLoadY, [BWPort23], 6, [1], 1>; 414defm : X86WriteRes<WriteVecLoadNT, [BWPort23], 5, [1], 1>; 415defm : X86WriteRes<WriteVecLoadNTY, [BWPort23], 6, [1], 1>; 416defm : X86WriteRes<WriteVecMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 417defm : X86WriteRes<WriteVecMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 418defm : X86WriteRes<WriteVecStore, [BWPort237,BWPort4], 1, [1,1], 2>; 419defm : X86WriteRes<WriteVecStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 420defm : X86WriteRes<WriteVecStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 421defm : X86WriteRes<WriteVecStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 422defm : X86WriteRes<WriteVecStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 423defm : X86WriteRes<WriteVecMaskedStore32, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 424defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 425defm : X86WriteRes<WriteVecMaskedStore64, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 426defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort23,BWPort1], 5, [1,1,1,1], 4>; 427defm : X86WriteRes<WriteVecMove, [BWPort015], 1, [1], 1>; 428defm : X86WriteRes<WriteVecMoveX, [BWPort015], 1, [1], 1>; 429defm : X86WriteRes<WriteVecMoveY, [BWPort015], 1, [1], 1>; 430defm : X86WriteResUnsupported<WriteVecMoveZ>; 431defm : X86WriteRes<WriteVecMoveToGpr, [BWPort0], 1, [1], 1>; 432defm : X86WriteRes<WriteVecMoveFromGpr, [BWPort5], 1, [1], 1>; 433 434defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 435defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 436defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM). 437defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 438defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions. 439defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM). 440defm : X86WriteResPairUnsupported<WriteVecTestZ>; 441defm : BWWriteResPair<WriteVecALU, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 442defm : BWWriteResPair<WriteVecALUX, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 443defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM). 444defm : X86WriteResPairUnsupported<WriteVecALUZ>; 445defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 446defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 447defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply. 448defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 449defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // Vector PMULLD. 450defm : BWWriteResPair<WritePMULLDY, [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM). 451defm : X86WriteResPairUnsupported<WritePMULLDZ>; 452defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 453defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 454defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM). 455defm : X86WriteResPairUnsupported<WriteShuffleZ>; 456defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 457defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 458defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM). 459defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 460defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends. 461defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM). 462defm : X86WriteResPairUnsupported<WriteBlendZ>; 463defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles. 464defm : BWWriteResPair<WriteVPMOV256, [BWPort5], 3, [1], 1, 6>; // 256-bit width packed vector width-changing move. 465defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles. 466defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends. 467defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM). 468defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 469defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD. 470defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD. 471defm : X86WriteResPairUnsupported<WriteMPSADZ>; 472defm : BWWriteResPair<WritePSADBW, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 473defm : BWWriteResPair<WritePSADBWX, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 474defm : BWWriteResPair<WritePSADBWY, [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM). 475defm : X86WriteResPairUnsupported<WritePSADBWZ>; 476defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS. 477 478// Vector integer shifts. 479defm : X86WriteRes<WriteVecShift, [BWPort0], 1, [1], 1>; 480defm : X86WriteRes<WriteVecShiftX, [BWPort0,BWPort5], 2, [1,1], 2>; 481defm : X86WriteRes<WriteVecShiftY, [BWPort0,BWPort5], 4, [1,1], 2>; 482defm : X86WriteRes<WriteVecShiftLd, [BWPort0,BWPort23], 6, [1,1], 2>; 483defm : X86WriteRes<WriteVecShiftXLd, [BWPort0,BWPort23], 7, [1,1], 2>; 484defm : X86WriteRes<WriteVecShiftYLd, [BWPort0,BWPort23], 7, [1,1], 2>; 485defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 486 487defm : BWWriteResPair<WriteVecShiftImm, [BWPort0], 1, [1], 1, 5>; 488defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0], 1, [1], 1, 5>; // Vector integer immediate shifts (XMM). 489defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0], 1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM). 490defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 491defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts. 492defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM). 493defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 494 495// Vector insert/extract operations. 496def : WriteRes<WriteVecInsert, [BWPort5]> { 497 let Latency = 2; 498 let NumMicroOps = 2; 499 let ReleaseAtCycles = [2]; 500} 501def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> { 502 let Latency = 6; 503 let NumMicroOps = 2; 504} 505 506def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> { 507 let Latency = 2; 508 let NumMicroOps = 2; 509} 510def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> { 511 let Latency = 2; 512 let NumMicroOps = 3; 513} 514 515// String instructions. 516 517// Packed Compare Implicit Length Strings, Return Mask 518def : WriteRes<WritePCmpIStrM, [BWPort0]> { 519 let Latency = 11; 520 let NumMicroOps = 3; 521 let ReleaseAtCycles = [3]; 522} 523def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> { 524 let Latency = 16; 525 let NumMicroOps = 4; 526 let ReleaseAtCycles = [3,1]; 527} 528 529// Packed Compare Explicit Length Strings, Return Mask 530def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> { 531 let Latency = 19; 532 let NumMicroOps = 9; 533 let ReleaseAtCycles = [4,3,1,1]; 534} 535def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> { 536 let Latency = 24; 537 let NumMicroOps = 10; 538 let ReleaseAtCycles = [4,3,1,1,1]; 539} 540 541// Packed Compare Implicit Length Strings, Return Index 542def : WriteRes<WritePCmpIStrI, [BWPort0]> { 543 let Latency = 11; 544 let NumMicroOps = 3; 545 let ReleaseAtCycles = [3]; 546} 547def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> { 548 let Latency = 16; 549 let NumMicroOps = 4; 550 let ReleaseAtCycles = [3,1]; 551} 552 553// Packed Compare Explicit Length Strings, Return Index 554def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> { 555 let Latency = 18; 556 let NumMicroOps = 8; 557 let ReleaseAtCycles = [4,3,1]; 558} 559def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> { 560 let Latency = 23; 561 let NumMicroOps = 9; 562 let ReleaseAtCycles = [4,3,1,1]; 563} 564 565// MOVMSK Instructions. 566def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; } 567def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; } 568def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; } 569def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; } 570 571// AES Instructions. 572def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption. 573 let Latency = 7; 574 let NumMicroOps = 1; 575 let ReleaseAtCycles = [1]; 576} 577def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> { 578 let Latency = 12; 579 let NumMicroOps = 2; 580 let ReleaseAtCycles = [1,1]; 581} 582 583def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn. 584 let Latency = 14; 585 let NumMicroOps = 2; 586 let ReleaseAtCycles = [2]; 587} 588def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> { 589 let Latency = 19; 590 let NumMicroOps = 3; 591 let ReleaseAtCycles = [2,1]; 592} 593 594def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation. 595 let Latency = 29; 596 let NumMicroOps = 11; 597 let ReleaseAtCycles = [2,7,2]; 598} 599def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> { 600 let Latency = 33; 601 let NumMicroOps = 11; 602 let ReleaseAtCycles = [2,7,1,1]; 603} 604 605// Carry-less multiplication instructions. 606defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>; 607// Load/store MXCSR. 608def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 609def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 610 611// Catch-all for expensive system instructions. 612def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } 613 614// Old microcoded instructions that nobody use. 615def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } 616 617// Fence instructions. 618def : WriteRes<WriteFence, [BWPort23, BWPort4]> { let NumMicroOps = 2; let ReleaseAtCycles = [1,1]; } 619 620// Nop, not very useful expect it provides a model for nops! 621def : WriteRes<WriteNop, []>; 622 623//////////////////////////////////////////////////////////////////////////////// 624// Horizontal add/sub instructions. 625//////////////////////////////////////////////////////////////////////////////// 626 627defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3, 5>; 628defm : BWWriteResPair<WriteFHAddY, [BWPort1,BWPort5], 5, [1,2], 3, 6>; 629defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 630defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 631defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>; 632 633// Remaining instrs. 634 635def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { 636 let Latency = 1; 637 let NumMicroOps = 1; 638 let ReleaseAtCycles = [1]; 639} 640def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", 641 "VPSRLVQ(Y?)rr")>; 642 643def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { 644 let Latency = 1; 645 let NumMicroOps = 1; 646 let ReleaseAtCycles = [1]; 647} 648def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", 649 "UCOM_F(P?)r")>; 650 651def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { 652 let Latency = 1; 653 let NumMicroOps = 1; 654 let ReleaseAtCycles = [1]; 655} 656def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; 657 658def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { 659 let Latency = 1; 660 let NumMicroOps = 1; 661 let ReleaseAtCycles = [1]; 662} 663def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; 664 665def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { 666 let Latency = 1; 667 let NumMicroOps = 1; 668 let ReleaseAtCycles = [1]; 669} 670def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; 671 672def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { 673 let Latency = 1; 674 let NumMicroOps = 1; 675 let ReleaseAtCycles = [1]; 676} 677def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>; 678 679def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { 680 let Latency = 1; 681 let NumMicroOps = 1; 682 let ReleaseAtCycles = [1]; 683} 684def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; 685 686def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { 687 let Latency = 1; 688 let NumMicroOps = 1; 689 let ReleaseAtCycles = [1]; 690} 691def: InstRW<[BWWriteResGroup9], (instrs SGDT64m, 692 SIDT64m, 693 SMSW16m, 694 STRm, 695 SYSCALL)>; 696 697def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { 698 let Latency = 1; 699 let NumMicroOps = 2; 700 let ReleaseAtCycles = [1,1]; 701} 702def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>; 703def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>; 704 705def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { 706 let Latency = 2; 707 let NumMicroOps = 2; 708 let ReleaseAtCycles = [2]; 709} 710def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; 711 712def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { 713 let Latency = 2; 714 let NumMicroOps = 2; 715 let ReleaseAtCycles = [2]; 716} 717def: InstRW<[BWWriteResGroup14], (instrs LFENCE, 718 WAIT, 719 XGETBV)>; 720 721def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { 722 let Latency = 2; 723 let NumMicroOps = 2; 724 let ReleaseAtCycles = [1,1]; 725} 726def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; 727 728def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { 729 let Latency = 2; 730 let NumMicroOps = 2; 731 let ReleaseAtCycles = [1,1]; 732} 733def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>; 734 735def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { 736 let Latency = 2; 737 let NumMicroOps = 2; 738 let ReleaseAtCycles = [1,1]; 739} 740def: InstRW<[BWWriteResGroup20], (instrs CWD, 741 JCXZ, JECXZ, JRCXZ, 742 ADC8i8, SBB8i8, 743 ADC16i16, SBB16i16, 744 ADC32i32, SBB32i32, 745 ADC64i32, SBB64i32)>; 746 747def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { 748 let Latency = 2; 749 let NumMicroOps = 3; 750 let ReleaseAtCycles = [1,1,1]; 751} 752def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; 753 754def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { 755 let Latency = 2; 756 let NumMicroOps = 3; 757 let ReleaseAtCycles = [1,1,1]; 758} 759def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; 760 761def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 762 let Latency = 2; 763 let NumMicroOps = 3; 764 let ReleaseAtCycles = [1,1,1]; 765} 766def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 767 STOSB, STOSL, STOSQ, STOSW)>; 768def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>; 769 770def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { 771 let Latency = 3; 772 let NumMicroOps = 1; 773 let ReleaseAtCycles = [1]; 774} 775def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr")>; 776 777def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { 778 let Latency = 3; 779 let NumMicroOps = 1; 780 let ReleaseAtCycles = [1]; 781} 782def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr, 783 VPBROADCASTWrr)>; 784 785def BWWriteResGroup33 : SchedWriteRes<[BWPort5]> { 786 let Latency = 3; 787 let NumMicroOps = 2; 788 let ReleaseAtCycles = [2]; 789} 790def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr, 791 MMX_PACKSSWBrr, 792 MMX_PACKUSWBrr)>; 793 794def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { 795 let Latency = 3; 796 let NumMicroOps = 3; 797 let ReleaseAtCycles = [1,2]; 798} 799def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; 800 801def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { 802 let Latency = 2; 803 let NumMicroOps = 3; 804 let ReleaseAtCycles = [1,2]; 805} 806def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 807 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 808 809def BWWriteResGroup36 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 810 let Latency = 5; 811 let NumMicroOps = 8; 812 let ReleaseAtCycles = [2,4,2]; 813} 814def: InstRW<[BWWriteResGroup36], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 815 816def BWWriteResGroup36b : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 817 let Latency = 6; 818 let NumMicroOps = 8; 819 let ReleaseAtCycles = [2,4,2]; 820} 821def: InstRW<[BWWriteResGroup36b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 822 823def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { 824 let Latency = 3; 825 let NumMicroOps = 4; 826 let ReleaseAtCycles = [1,1,1,1]; 827} 828def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; 829 830def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 831 let Latency = 3; 832 let NumMicroOps = 4; 833 let ReleaseAtCycles = [1,1,1,1]; 834} 835def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; 836 837 838def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { 839 let Latency = 4; 840 let NumMicroOps = 2; 841 let ReleaseAtCycles = [1,1]; 842} 843def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; 844 845def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { 846 let Latency = 4; 847 let NumMicroOps = 2; 848 let ReleaseAtCycles = [1,1]; 849} 850def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PS2PIrr")>; 851 852def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { 853 let Latency = 4; 854 let NumMicroOps = 3; 855 let ReleaseAtCycles = [1,1,1]; 856} 857def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; 858 859def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { 860 let Latency = 4; 861 let NumMicroOps = 3; 862 let ReleaseAtCycles = [1,1,1]; 863} 864def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", 865 "IST_F(16|32)m")>; 866 867def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { 868 let Latency = 4; 869 let NumMicroOps = 4; 870 let ReleaseAtCycles = [4]; 871} 872def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; 873 874def BWWriteResGroup46 : SchedWriteRes<[]> { 875 let Latency = 0; 876 let NumMicroOps = 4; 877 let ReleaseAtCycles = []; 878} 879def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; 880 881def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { 882 let Latency = 5; 883 let NumMicroOps = 1; 884 let ReleaseAtCycles = [1]; 885} 886def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 887 888def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { 889 let Latency = 5; 890 let NumMicroOps = 1; 891 let ReleaseAtCycles = [1]; 892} 893def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm, 894 VMOVDDUPrm, MOVDDUPrm, 895 VMOVSHDUPrm, MOVSHDUPrm, 896 VMOVSLDUPrm, MOVSLDUPrm, 897 VPBROADCASTDrm, 898 VPBROADCASTQrm)>; 899 900def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { 901 let Latency = 5; 902 let NumMicroOps = 3; 903 let ReleaseAtCycles = [1,2]; 904} 905def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; 906 907def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { 908 let Latency = 5; 909 let NumMicroOps = 3; 910 let ReleaseAtCycles = [1,1,1]; 911} 912def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; 913 914def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { 915 let Latency = 5; 916 let NumMicroOps = 5; 917 let ReleaseAtCycles = [1,4]; 918} 919def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; 920 921def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { 922 let Latency = 5; 923 let NumMicroOps = 5; 924 let ReleaseAtCycles = [1,4]; 925} 926def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; 927 928def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 929 let Latency = 5; 930 let NumMicroOps = 6; 931 let ReleaseAtCycles = [1,1,4]; 932} 933def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; 934 935def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { 936 let Latency = 6; 937 let NumMicroOps = 1; 938 let ReleaseAtCycles = [1]; 939} 940def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>; 941def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128rm, 942 VBROADCASTI128rm, 943 VBROADCASTSDYrm, 944 VBROADCASTSSYrm, 945 VMOVDDUPYrm, 946 VMOVSHDUPYrm, 947 VMOVSLDUPYrm, 948 VPBROADCASTDYrm, 949 VPBROADCASTQYrm)>; 950 951def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { 952 let Latency = 6; 953 let NumMicroOps = 2; 954 let ReleaseAtCycles = [1,1]; 955} 956def: InstRW<[BWWriteResGroup59], (instrs VPSLLVQrm, VPSRLVQrm)>; 957 958def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { 959 let Latency = 6; 960 let NumMicroOps = 2; 961 let ReleaseAtCycles = [1,1]; 962} 963def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>; 964def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>; 965 966def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { 967 let Latency = 6; 968 let NumMicroOps = 2; 969 let ReleaseAtCycles = [1,1]; 970} 971def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", 972 "MOVBE(16|32|64)rm")>; 973 974def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { 975 let Latency = 6; 976 let NumMicroOps = 2; 977 let ReleaseAtCycles = [1,1]; 978} 979def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rmi, 980 VINSERTI128rmi, 981 VPBLENDDrmi)>; 982 983def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { 984 let Latency = 6; 985 let NumMicroOps = 2; 986 let ReleaseAtCycles = [1,1]; 987} 988def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; 989def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; 990 991def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { 992 let Latency = 6; 993 let NumMicroOps = 4; 994 let ReleaseAtCycles = [1,1,1,1]; 995} 996def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; 997 998def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 999 let Latency = 6; 1000 let NumMicroOps = 4; 1001 let ReleaseAtCycles = [1,1,1,1]; 1002} 1003def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 1004 "SHL(8|16|32|64)m(1|i)", 1005 "SHR(8|16|32|64)m(1|i)")>; 1006 1007def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1008 let Latency = 6; 1009 let NumMicroOps = 4; 1010 let ReleaseAtCycles = [1,1,1,1]; 1011} 1012def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", 1013 "PUSH(16|32|64)rmm")>; 1014 1015def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { 1016 let Latency = 6; 1017 let NumMicroOps = 6; 1018 let ReleaseAtCycles = [1,5]; 1019} 1020def: InstRW<[BWWriteResGroup71], (instrs STD)>; 1021 1022def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { 1023 let Latency = 7; 1024 let NumMicroOps = 2; 1025 let ReleaseAtCycles = [1,1]; 1026} 1027def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm, 1028 VPSRLVQYrm)>; 1029 1030def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { 1031 let Latency = 7; 1032 let NumMicroOps = 2; 1033 let ReleaseAtCycles = [1,1]; 1034} 1035def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; 1036 1037def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { 1038 let Latency = 7; 1039 let NumMicroOps = 2; 1040 let ReleaseAtCycles = [1,1]; 1041} 1042def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>; 1043 1044def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { 1045 let Latency = 7; 1046 let NumMicroOps = 3; 1047 let ReleaseAtCycles = [2,1]; 1048} 1049def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm, 1050 MMX_PACKSSWBrm, 1051 MMX_PACKUSWBrm)>; 1052 1053def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { 1054 let Latency = 7; 1055 let NumMicroOps = 3; 1056 let ReleaseAtCycles = [1,2]; 1057} 1058def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, 1059 SCASB, SCASL, SCASQ, SCASW)>; 1060 1061def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { 1062 let Latency = 7; 1063 let NumMicroOps = 3; 1064 let ReleaseAtCycles = [1,1,1]; 1065} 1066def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; 1067 1068def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1069 let Latency = 7; 1070 let NumMicroOps = 3; 1071 let ReleaseAtCycles = [1,1,1]; 1072} 1073def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>; 1074 1075def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1076 let Latency = 7; 1077 let NumMicroOps = 5; 1078 let ReleaseAtCycles = [1,1,1,2]; 1079} 1080def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)", 1081 "ROR(8|16|32|64)m(1|i)")>; 1082 1083def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> { 1084 let Latency = 2; 1085 let NumMicroOps = 2; 1086 let ReleaseAtCycles = [2]; 1087} 1088def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1089 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1090 1091def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1092 let Latency = 7; 1093 let NumMicroOps = 5; 1094 let ReleaseAtCycles = [1,1,1,2]; 1095} 1096def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; 1097 1098def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1099 let Latency = 7; 1100 let NumMicroOps = 5; 1101 let ReleaseAtCycles = [1,1,1,1,1]; 1102} 1103def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>; 1104def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>; 1105 1106def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { 1107 let Latency = 7; 1108 let NumMicroOps = 7; 1109 let ReleaseAtCycles = [2,2,1,2]; 1110} 1111def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; 1112 1113def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { 1114 let Latency = 8; 1115 let NumMicroOps = 2; 1116 let ReleaseAtCycles = [1,1]; 1117} 1118def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>; 1119 1120def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { 1121 let Latency = 8; 1122 let NumMicroOps = 2; 1123 let ReleaseAtCycles = [1,1]; 1124} 1125def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm, 1126 VPMOVSXBQYrm, 1127 VPMOVSXBWYrm, 1128 VPMOVSXDQYrm, 1129 VPMOVSXWDYrm, 1130 VPMOVSXWQYrm, 1131 VPMOVZXWDYrm)>; 1132 1133def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { 1134 let Latency = 8; 1135 let NumMicroOps = 5; 1136 let ReleaseAtCycles = [1,1,1,2]; 1137} 1138def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)", 1139 "RCR(8|16|32|64)m(1|i)")>; 1140 1141def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1142 let Latency = 8; 1143 let NumMicroOps = 6; 1144 let ReleaseAtCycles = [1,1,1,3]; 1145} 1146def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; 1147 1148def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1149 let Latency = 8; 1150 let NumMicroOps = 6; 1151 let ReleaseAtCycles = [1,1,1,2,1]; 1152} 1153def : SchedAlias<WriteADCRMW, BWWriteResGroup100>; 1154def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", 1155 "ROR(8|16|32|64)mCL", 1156 "SAR(8|16|32|64)mCL", 1157 "SHL(8|16|32|64)mCL", 1158 "SHR(8|16|32|64)mCL")>; 1159 1160def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { 1161 let Latency = 9; 1162 let NumMicroOps = 2; 1163 let ReleaseAtCycles = [1,1]; 1164} 1165def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1166 "ILD_F(16|32|64)m")>; 1167 1168def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { 1169 let Latency = 9; 1170 let NumMicroOps = 3; 1171 let ReleaseAtCycles = [1,1,1]; 1172} 1173def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", 1174 "VPBROADCASTW(Y?)rm")>; 1175 1176def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1177 let Latency = 9; 1178 let NumMicroOps = 5; 1179 let ReleaseAtCycles = [1,1,3]; 1180} 1181def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 1182 1183def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1184 let Latency = 9; 1185 let NumMicroOps = 5; 1186 let ReleaseAtCycles = [1,2,1,1]; 1187} 1188def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", 1189 "LSL(16|32|64)rm")>; 1190 1191def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { 1192 let Latency = 10; 1193 let NumMicroOps = 2; 1194 let ReleaseAtCycles = [1,1]; 1195} 1196def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; 1197 1198def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { 1199 let Latency = 10; 1200 let NumMicroOps = 3; 1201 let ReleaseAtCycles = [2,1]; 1202} 1203def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; 1204 1205def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1206 let Latency = 11; 1207 let NumMicroOps = 1; 1208 let ReleaseAtCycles = [1,3]; // Really 2.5 cycle throughput 1209} 1210def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair 1211 1212def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { 1213 let Latency = 11; 1214 let NumMicroOps = 2; 1215 let ReleaseAtCycles = [1,1]; 1216} 1217def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>; 1218def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>; 1219 1220def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 1221 let Latency = 11; 1222 let NumMicroOps = 7; 1223 let ReleaseAtCycles = [2,2,3]; 1224} 1225def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", 1226 "RCR(16|32|64)rCL")>; 1227 1228def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1229 let Latency = 11; 1230 let NumMicroOps = 9; 1231 let ReleaseAtCycles = [1,4,1,3]; 1232} 1233def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>; 1234 1235def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { 1236 let Latency = 11; 1237 let NumMicroOps = 11; 1238 let ReleaseAtCycles = [2,9]; 1239} 1240def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; 1241def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; 1242 1243def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { 1244 let Latency = 12; 1245 let NumMicroOps = 3; 1246 let ReleaseAtCycles = [2,1]; 1247} 1248def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1249 1250def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1251 let Latency = 14; 1252 let NumMicroOps = 1; 1253 let ReleaseAtCycles = [1,4]; 1254} 1255def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair 1256 1257def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1258 let Latency = 14; 1259 let NumMicroOps = 3; 1260 let ReleaseAtCycles = [1,1,1]; 1261} 1262def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; 1263 1264def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1265 let Latency = 14; 1266 let NumMicroOps = 8; 1267 let ReleaseAtCycles = [2,2,1,3]; 1268} 1269def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; 1270 1271def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1272 let Latency = 14; 1273 let NumMicroOps = 10; 1274 let ReleaseAtCycles = [2,3,1,4]; 1275} 1276def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>; 1277 1278def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { 1279 let Latency = 14; 1280 let NumMicroOps = 12; 1281 let ReleaseAtCycles = [2,1,4,5]; 1282} 1283def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; 1284 1285def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { 1286 let Latency = 15; 1287 let NumMicroOps = 1; 1288 let ReleaseAtCycles = [1]; 1289} 1290def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1291 1292def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1293 let Latency = 15; 1294 let NumMicroOps = 10; 1295 let ReleaseAtCycles = [1,1,1,4,1,2]; 1296} 1297def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; 1298 1299def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1300 let Latency = 16; 1301 let NumMicroOps = 2; 1302 let ReleaseAtCycles = [1,1,5]; 1303} 1304def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair 1305 1306def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1307 let Latency = 16; 1308 let NumMicroOps = 14; 1309 let ReleaseAtCycles = [1,1,1,4,2,5]; 1310} 1311def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; 1312 1313def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> { 1314 let Latency = 8; 1315 let NumMicroOps = 20; 1316 let ReleaseAtCycles = [1,1]; 1317} 1318def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; 1319 1320def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { 1321 let Latency = 18; 1322 let NumMicroOps = 8; 1323 let ReleaseAtCycles = [1,1,1,5]; 1324} 1325def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; 1326def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; 1327 1328def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1329 let Latency = 18; 1330 let NumMicroOps = 11; 1331 let ReleaseAtCycles = [2,1,1,3,1,3]; 1332} 1333def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; 1334 1335def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1336 let Latency = 19; 1337 let NumMicroOps = 2; 1338 let ReleaseAtCycles = [1,1,8]; 1339} 1340def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair 1341 1342def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { 1343 let Latency = 20; 1344 let NumMicroOps = 1; 1345 let ReleaseAtCycles = [1]; 1346} 1347def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1348 1349def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1350 let Latency = 20; 1351 let NumMicroOps = 8; 1352 let ReleaseAtCycles = [1,1,1,1,1,1,2]; 1353} 1354def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; 1355 1356def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { 1357 let Latency = 21; 1358 let NumMicroOps = 2; 1359 let ReleaseAtCycles = [1,1]; 1360} 1361def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; 1362 1363def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1364 let Latency = 21; 1365 let NumMicroOps = 19; 1366 let ReleaseAtCycles = [2,1,4,1,1,4,6]; 1367} 1368def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; 1369 1370def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1371 let Latency = 22; 1372 let NumMicroOps = 18; 1373 let ReleaseAtCycles = [1,1,16]; 1374} 1375def: InstRW<[BWWriteResGroup172], (instrs POPF64)>; 1376 1377def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1378 let Latency = 23; 1379 let NumMicroOps = 19; 1380 let ReleaseAtCycles = [3,1,15]; 1381} 1382def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; 1383 1384def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1385 let Latency = 24; 1386 let NumMicroOps = 3; 1387 let ReleaseAtCycles = [1,1,1]; 1388} 1389def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; 1390 1391def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { 1392 let Latency = 26; 1393 let NumMicroOps = 2; 1394 let ReleaseAtCycles = [1,1]; 1395} 1396def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; 1397 1398def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1399 let Latency = 29; 1400 let NumMicroOps = 3; 1401 let ReleaseAtCycles = [1,1,1]; 1402} 1403def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; 1404 1405def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1406 let Latency = 17; 1407 let NumMicroOps = 7; 1408 let ReleaseAtCycles = [1,3,2,1]; 1409} 1410def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm, 1411 VGATHERQPDrm, VPGATHERQQrm)>; 1412 1413def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1414 let Latency = 18; 1415 let NumMicroOps = 9; 1416 let ReleaseAtCycles = [1,3,4,1]; 1417} 1418def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1419 VGATHERQPDYrm, VPGATHERQQYrm)>; 1420 1421def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1422 let Latency = 19; 1423 let NumMicroOps = 9; 1424 let ReleaseAtCycles = [1,5,2,1]; 1425} 1426def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 1427 1428def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1429 let Latency = 19; 1430 let NumMicroOps = 10; 1431 let ReleaseAtCycles = [1,4,4,1]; 1432} 1433def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm, 1434 VGATHERQPSYrm, VPGATHERQDYrm)>; 1435 1436def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1437 let Latency = 21; 1438 let NumMicroOps = 14; 1439 let ReleaseAtCycles = [1,4,8,1]; 1440} 1441def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1442 1443def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1444 let Latency = 29; 1445 let NumMicroOps = 27; 1446 let ReleaseAtCycles = [1,5,1,1,19]; 1447} 1448def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; 1449 1450def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1451 let Latency = 30; 1452 let NumMicroOps = 28; 1453 let ReleaseAtCycles = [1,6,1,1,19]; 1454} 1455def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; 1456def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1457 1458def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { 1459 let Latency = 34; 1460 let NumMicroOps = 23; 1461 let ReleaseAtCycles = [1,5,3,4,10]; 1462} 1463def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", 1464 "IN(8|16|32)rr")>; 1465 1466def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1467 let Latency = 35; 1468 let NumMicroOps = 23; 1469 let ReleaseAtCycles = [1,5,2,1,4,10]; 1470} 1471def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", 1472 "OUT(8|16|32)rr")>; 1473 1474def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { 1475 let Latency = 42; 1476 let NumMicroOps = 22; 1477 let ReleaseAtCycles = [2,20]; 1478} 1479def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; 1480 1481def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { 1482 let Latency = 60; 1483 let NumMicroOps = 64; 1484 let ReleaseAtCycles = [2,2,8,1,10,2,39]; 1485} 1486def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; 1487 1488def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1489 let Latency = 63; 1490 let NumMicroOps = 88; 1491 let ReleaseAtCycles = [4,4,31,1,2,1,45]; 1492} 1493def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; 1494 1495def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1496 let Latency = 63; 1497 let NumMicroOps = 90; 1498 let ReleaseAtCycles = [4,2,33,1,2,1,47]; 1499} 1500def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; 1501 1502def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { 1503 let Latency = 75; 1504 let NumMicroOps = 15; 1505 let ReleaseAtCycles = [6,3,6]; 1506} 1507def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; 1508 1509def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { 1510 let Latency = 115; 1511 let NumMicroOps = 100; 1512 let ReleaseAtCycles = [9,9,11,8,1,11,21,30]; 1513} 1514def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; 1515 1516def: InstRW<[WriteZero], (instrs CLC)>; 1517 1518 1519// Instruction variants handled by the renamer. These might not need execution 1520// ports in certain conditions. 1521// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1522// section "Haswell and Broadwell Pipeline" > "Register allocation and 1523// renaming". 1524// These can be investigated with llvm-exegesis, e.g. 1525// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1526// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1527 1528def BWWriteZeroLatency : SchedWriteRes<[]> { 1529 let Latency = 0; 1530} 1531 1532def BWWriteZeroIdiom : SchedWriteVariant<[ 1533 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1534 SchedVar<NoSchedPred, [WriteALU]> 1535]>; 1536def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1537 XOR32rr, XOR64rr)>; 1538 1539def BWWriteFZeroIdiom : SchedWriteVariant<[ 1540 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1541 SchedVar<NoSchedPred, [WriteFLogic]> 1542]>; 1543def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1544 VXORPDrr)>; 1545 1546def BWWriteFZeroIdiomY : SchedWriteVariant<[ 1547 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1548 SchedVar<NoSchedPred, [WriteFLogicY]> 1549]>; 1550def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1551 1552def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1553 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1554 SchedVar<NoSchedPred, [WriteVecLogicX]> 1555]>; 1556def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1557 1558def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1559 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1560 SchedVar<NoSchedPred, [WriteVecLogicY]> 1561]>; 1562def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1563 1564def BWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1565 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1566 SchedVar<NoSchedPred, [WriteVecALUX]> 1567]>; 1568def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1569 PSUBDrr, VPSUBDrr, 1570 PSUBQrr, VPSUBQrr, 1571 PSUBWrr, VPSUBWrr, 1572 PCMPGTBrr, VPCMPGTBrr, 1573 PCMPGTDrr, VPCMPGTDrr, 1574 PCMPGTWrr, VPCMPGTWrr)>; 1575 1576def BWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1577 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1578 SchedVar<NoSchedPred, [WriteVecALUY]> 1579]>; 1580def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1581 VPSUBDYrr, 1582 VPSUBQYrr, 1583 VPSUBWYrr, 1584 VPCMPGTBYrr, 1585 VPCMPGTDYrr, 1586 VPCMPGTWYrr)>; 1587 1588def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> { 1589 let Latency = 5; 1590 let NumMicroOps = 1; 1591 let ReleaseAtCycles = [1]; 1592} 1593 1594def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1595 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1596 SchedVar<NoSchedPred, [BWWritePCMPGTQ]> 1597]>; 1598def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1599 VPCMPGTQYrr)>; 1600 1601 1602// CMOVs that use both Z and C flag require an extra uop. 1603def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> { 1604 let Latency = 2; 1605 let ReleaseAtCycles = [1,1]; 1606 let NumMicroOps = 2; 1607} 1608 1609def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1610 let Latency = 7; 1611 let ReleaseAtCycles = [1,1,1]; 1612 let NumMicroOps = 3; 1613} 1614 1615def BWCMOVA_CMOVBErr : SchedWriteVariant<[ 1616 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>, 1617 SchedVar<NoSchedPred, [WriteCMOV]> 1618]>; 1619 1620def BWCMOVA_CMOVBErm : SchedWriteVariant<[ 1621 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>, 1622 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1623]>; 1624 1625def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1626def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1627 1628// SETCCs that use both Z and C flag require an extra uop. 1629def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> { 1630 let Latency = 2; 1631 let ReleaseAtCycles = [1,1]; 1632 let NumMicroOps = 2; 1633} 1634 1635def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 1636 let Latency = 3; 1637 let ReleaseAtCycles = [1,1,1,1]; 1638 let NumMicroOps = 4; 1639} 1640 1641def BWSETA_SETBErr : SchedWriteVariant<[ 1642 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>, 1643 SchedVar<NoSchedPred, [WriteSETCC]> 1644]>; 1645 1646def BWSETA_SETBErm : SchedWriteVariant<[ 1647 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>, 1648 SchedVar<NoSchedPred, [WriteSETCCStore]> 1649]>; 1650 1651def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>; 1652def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>; 1653 1654/////////////////////////////////////////////////////////////////////////////// 1655// Dependency breaking instructions. 1656/////////////////////////////////////////////////////////////////////////////// 1657 1658def : IsZeroIdiomFunction<[ 1659 // GPR Zero-idioms. 1660 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 1661 1662 // SSE Zero-idioms. 1663 DepBreakingClass<[ 1664 // fp variants. 1665 XORPSrr, XORPDrr, 1666 1667 // int variants. 1668 PXORrr, 1669 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 1670 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 1671 ], ZeroIdiomPredicate>, 1672 1673 // AVX Zero-idioms. 1674 DepBreakingClass<[ 1675 // xmm fp variants. 1676 VXORPSrr, VXORPDrr, 1677 1678 // xmm int variants. 1679 VPXORrr, 1680 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 1681 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 1682 1683 // ymm variants. 1684 VXORPSYrr, VXORPDYrr, VPXORYrr, 1685 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 1686 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr 1687 ], ZeroIdiomPredicate>, 1688]>; 1689 1690} // SchedModel 1691