1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("State.getMachineFunction()." 17 "getSubtarget<X86Subtarget>().", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!State.getMachineFunction()." 23 "getSubtarget<X86Subtarget>().", F), 24 A>; 25 26/// CCIfRegCallv4 - Match if RegCall ABIv4 is respected. 27class CCIfRegCallv4<CCAction A> 28 : CCIf<"State.getMachineFunction().getFunction().getParent()->getModuleFlag(\"RegCallv4\")!=nullptr", 29 A>; 30 31/// CCIfIsVarArgOnWin - Match if isVarArg on Windows 32bits. 32class CCIfIsVarArgOnWin<CCAction A> 33 : CCIf<"State.isVarArg() && " 34 "State.getMachineFunction().getSubtarget().getTargetTriple()." 35 "isWindowsMSVCEnvironment()", 36 A>; 37 38// Register classes for RegCall 39class RC_X86_RegCall { 40 list<Register> GPR_8 = []; 41 list<Register> GPR_16 = []; 42 list<Register> GPR_32 = []; 43 list<Register> GPR_64 = []; 44 list<Register> FP_CALL = [FP0]; 45 list<Register> FP_RET = [FP0, FP1]; 46 list<Register> XMM = []; 47 list<Register> YMM = []; 48 list<Register> ZMM = []; 49} 50 51// RegCall register classes for 32 bits 52def RC_X86_32_RegCall : RC_X86_RegCall { 53 let GPR_8 = [AL, CL, DL, DIL, SIL]; 54 let GPR_16 = [AX, CX, DX, DI, SI]; 55 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 56 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 57 ///< \todo Fix AssignToReg to enable empty lists 58 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 59 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 60 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 61} 62 63// RegCall register classes for 32 bits if it respect regcall ABI v.4 64// Change in __regcall ABI v.4: don't use EAX as a spare register is 65// needed to code virtual call thunk, 66def RC_X86_32_RegCallv4_Win : RC_X86_RegCall { 67 let GPR_8 = [CL, DL, DIL, SIL]; 68 let GPR_16 = [CX, DX, DI, SI]; 69 let GPR_32 = [ECX, EDX, EDI, ESI]; 70 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 71 ///< \todo Fix AssignToReg to enable empty lists 72 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 73 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 74 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 75} 76 77class RC_X86_64_RegCall : RC_X86_RegCall { 78 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 79 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 80 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 81 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 82 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 83 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 84} 85 86def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 87 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 88 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 89 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 91} 92 93// On Windows 64 we don't want to use R13 - it is reserved for 94// largely aligned stack. 95// Change in __regcall ABI v.4: additionally don't use R10 as a 96// a spare register is needed to code virtual call thunk. 97// 98def RC_X86_64_RegCallv4_Win : RC_X86_64_RegCall { 99 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R11B, R12B, R14B, R15B]; 100 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R11W, R12W, R14W, R15W]; 101 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R11D, R12D, R14D, R15D]; 102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15]; 103} 104 105def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 106 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 107 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 108 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 110} 111 112// X86-64 Intel regcall calling convention. 113multiclass X86_RegCall_base<RC_X86_RegCall RC> { 114def CC_#NAME : CallingConv<[ 115 // Handles byval parameters. 116 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 117 CCIfByVal<CCPassByVal<4, 4>>, 118 119 // Promote i1/i8/i16/v1i1 arguments to i32. 120 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 121 122 // Promote v8i1/v16i1/v32i1 arguments to i32. 123 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 124 125 // bool, char, int, enum, long, pointer --> GPR 126 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 127 128 // long long, __int64 --> GPR 129 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 130 131 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 132 CCIfType<[v64i1], CCPromoteToType<i64>>, 133 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 134 CCAssignToReg<RC.GPR_64>>>, 135 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 136 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 137 138 // float, double, float128 --> XMM 139 // In the case of SSE disabled --> save to stack 140 CCIfType<[f32, f64, f128], 141 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 142 143 // long double --> FP 144 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 145 146 // __m128, __m128i, __m128d --> XMM 147 // In the case of SSE disabled --> save to stack 148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 149 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 150 151 // __m256, __m256i, __m256d --> YMM 152 // In the case of SSE disabled --> save to stack 153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 154 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 155 156 // __m512, __m512i, __m512d --> ZMM 157 // In the case of SSE disabled --> save to stack 158 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 159 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 160 161 // If no register was found -> assign to stack 162 163 // In 64 bit, assign 64/32 bit values to 8 byte stack 164 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 165 CCAssignToStack<8, 8>>>, 166 167 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 168 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 169 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 170 171 // float 128 get stack slots whose size and alignment depends 172 // on the subtarget. 173 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 174 175 // Vectors get 16-byte stack slots that are 16-byte aligned. 176 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 177 CCAssignToStack<16, 16>>, 178 179 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 180 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 181 CCAssignToStack<32, 32>>, 182 183 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 184 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 185 CCAssignToStack<64, 64>> 186]>; 187 188def RetCC_#NAME : CallingConv<[ 189 // Promote i1, v1i1, v8i1 arguments to i8. 190 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 191 192 // Promote v16i1 arguments to i16. 193 CCIfType<[v16i1], CCPromoteToType<i16>>, 194 195 // Promote v32i1 arguments to i32. 196 CCIfType<[v32i1], CCPromoteToType<i32>>, 197 198 // bool, char, int, enum, long, pointer --> GPR 199 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 200 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 201 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 202 203 // long long, __int64 --> GPR 204 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 205 206 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 207 CCIfType<[v64i1], CCPromoteToType<i64>>, 208 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 209 CCAssignToReg<RC.GPR_64>>>, 210 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 211 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 212 213 // long double --> FP 214 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 215 216 // float, double, float128 --> XMM 217 CCIfType<[f32, f64, f128], 218 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 219 220 // __m128, __m128i, __m128d --> XMM 221 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 222 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 223 224 // __m256, __m256i, __m256d --> YMM 225 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 226 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 227 228 // __m512, __m512i, __m512d --> ZMM 229 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 230 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 231]>; 232} 233 234//===----------------------------------------------------------------------===// 235// Return Value Calling Conventions 236//===----------------------------------------------------------------------===// 237 238// Return-value conventions common to all X86 CC's. 239def RetCC_X86Common : CallingConv<[ 240 // Scalar values are returned in AX first, then DX. For i8, the ABI 241 // requires the values to be in AL and AH, however this code uses AL and DL 242 // instead. This is because using AH for the second register conflicts with 243 // the way LLVM does multiple return values -- a return of {i16,i8} would end 244 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 245 // for functions that return two i8 values are currently expected to pack the 246 // values into an i16 (which uses AX, and thus AL:AH). 247 // 248 // For code that doesn't care about the ABI, we allow returning more than two 249 // integer values in registers. 250 CCIfType<[v1i1], CCPromoteToType<i8>>, 251 CCIfType<[i1], CCPromoteToType<i8>>, 252 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 253 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 254 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 255 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 256 257 // Boolean vectors of AVX-512 are returned in SIMD registers. 258 // The call from AVX to AVX-512 function should work, 259 // since the boolean types in AVX/AVX2 are promoted by default. 260 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 261 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 262 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 263 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 264 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 265 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 266 267 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 268 // can only be used by ABI non-compliant code. If the target doesn't have XMM 269 // registers, it won't have vector types. 270 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 271 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 272 273 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 274 // can only be used by ABI non-compliant code. This vector type is only 275 // supported while using the AVX target feature. 276 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 277 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 278 279 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 280 // can only be used by ABI non-compliant code. This vector type is only 281 // supported while using the AVX-512 target feature. 282 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 283 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 284 285 // Long double types are always returned in FP0 (even with SSE), 286 // except on Win64. 287 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 288]>; 289 290// X86-32 C return-value convention. 291def RetCC_X86_32_C : CallingConv<[ 292 // The X86-32 calling convention returns FP values in FP0, unless marked 293 // with "inreg" (used here to distinguish one kind of reg from another, 294 // weirdly; this is really the sse-regparm calling convention) in which 295 // case they use XMM0, otherwise it is the same as the common X86 calling 296 // conv. 297 CCIfInReg<CCIfSubtarget<"hasSSE2()", 298 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 299 CCIfSubtarget<"hasX87()", 300 CCIfType<[f32, f64], CCAssignToReg<[FP0, FP1]>>>, 301 CCIfNotSubtarget<"hasX87()", 302 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>, 303 CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>, 304 CCDelegateTo<RetCC_X86Common> 305]>; 306 307// X86-32 FastCC return-value convention. 308def RetCC_X86_32_Fast : CallingConv<[ 309 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 310 // SSE2. 311 // This can happen when a float, 2 x float, or 3 x float vector is split by 312 // target lowering, and is returned in 1-3 sse regs. 313 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 314 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 315 316 // For integers, ECX can be used as an extra return register 317 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 318 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 319 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 320 321 // Otherwise, it is the same as the common X86 calling convention. 322 CCDelegateTo<RetCC_X86Common> 323]>; 324 325// Intel_OCL_BI return-value convention. 326def RetCC_Intel_OCL_BI : CallingConv<[ 327 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 328 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 329 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 330 331 // 256-bit FP vectors 332 // No more than 4 registers 333 CCIfType<[v8f32, v4f64, v8i32, v4i64], 334 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 335 336 // 512-bit FP vectors 337 CCIfType<[v16f32, v8f64, v16i32, v8i64], 338 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 339 340 // i32, i64 in the standard way 341 CCDelegateTo<RetCC_X86Common> 342]>; 343 344// X86-32 HiPE return-value convention. 345def RetCC_X86_32_HiPE : CallingConv<[ 346 // Promote all types to i32 347 CCIfType<[i8, i16], CCPromoteToType<i32>>, 348 349 // Return: HP, P, VAL1, VAL2 350 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 351]>; 352 353// X86-32 Vectorcall return-value convention. 354def RetCC_X86_32_VectorCall : CallingConv<[ 355 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 356 CCIfType<[f32, f64, f128], 357 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 358 359 // Return integers in the standard way. 360 CCDelegateTo<RetCC_X86Common> 361]>; 362 363// X86-64 C return-value convention. 364def RetCC_X86_64_C : CallingConv<[ 365 // The X86-64 calling convention always returns FP values in XMM0. 366 CCIfType<[f16], CCAssignToReg<[XMM0, XMM1]>>, 367 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 368 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 369 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 370 371 // Pointers are always returned in full 64-bit registers. 372 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 373 374 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 375 376 CCDelegateTo<RetCC_X86Common> 377]>; 378 379// X86-Win64 C return-value convention. 380def RetCC_X86_Win64_C : CallingConv<[ 381 // GCC returns FP values in RAX on Win64. 382 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 383 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 384 385 // Otherwise, everything is the same as 'normal' X86-64 C CC. 386 CCDelegateTo<RetCC_X86_64_C> 387]>; 388 389// X86-64 vectorcall return-value convention. 390def RetCC_X86_64_Vectorcall : CallingConv<[ 391 // Vectorcall calling convention always returns FP values in XMMs. 392 CCIfType<[f32, f64, f128], 393 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 394 395 // Otherwise, everything is the same as Windows X86-64 C CC. 396 CCDelegateTo<RetCC_X86_Win64_C> 397]>; 398 399// X86-64 HiPE return-value convention. 400def RetCC_X86_64_HiPE : CallingConv<[ 401 // Promote all types to i64 402 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 403 404 // Return: HP, P, VAL1, VAL2 405 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 406]>; 407 408def RetCC_X86_64_Swift : CallingConv<[ 409 410 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 411 412 // For integers, ECX, R8D can be used as extra return registers. 413 CCIfType<[v1i1], CCPromoteToType<i8>>, 414 CCIfType<[i1], CCPromoteToType<i8>>, 415 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 416 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 417 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 418 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 419 420 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 421 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 422 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 423 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 424 425 CCDelegateTo<RetCC_X86Common> 426]>; 427 428// X86-64 AnyReg return-value convention. No explicit register is specified for 429// the return-value. The register allocator is allowed and expected to choose 430// any free register. 431// 432// This calling convention is currently only supported by the stackmap and 433// patchpoint intrinsics. All other uses will result in an assert on Debug 434// builds. On Release builds we fallback to the X86 C calling convention. 435def RetCC_X86_64_AnyReg : CallingConv<[ 436 CCCustom<"CC_X86_AnyReg_Error"> 437]>; 438 439 440defm X86_32_RegCall : 441 X86_RegCall_base<RC_X86_32_RegCall>; 442defm X86_32_RegCallv4_Win : 443 X86_RegCall_base<RC_X86_32_RegCallv4_Win>; 444defm X86_Win64_RegCall : 445 X86_RegCall_base<RC_X86_64_RegCall_Win>; 446defm X86_Win64_RegCallv4 : 447 X86_RegCall_base<RC_X86_64_RegCallv4_Win>; 448defm X86_SysV64_RegCall : 449 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 450 451// This is the root return-value convention for the X86-32 backend. 452def RetCC_X86_32 : CallingConv<[ 453 // If FastCC, use RetCC_X86_32_Fast. 454 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 455 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 456 // CFGuard_Check never returns a value so does not need a RetCC. 457 // If HiPE, use RetCC_X86_32_HiPE. 458 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 459 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 460 CCIfCC<"CallingConv::X86_RegCall", 461 CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<RetCC_X86_32_RegCallv4_Win>>>>, 462 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 463 464 // Otherwise, use RetCC_X86_32_C. 465 CCDelegateTo<RetCC_X86_32_C> 466]>; 467 468// This is the root return-value convention for the X86-64 backend. 469def RetCC_X86_64 : CallingConv<[ 470 // HiPE uses RetCC_X86_64_HiPE 471 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 472 473 // Handle AnyReg calls. 474 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 475 476 // Handle Swift calls. 477 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 478 CCIfCC<"CallingConv::SwiftTail", CCDelegateTo<RetCC_X86_64_Swift>>, 479 480 // Handle explicit CC selection 481 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 482 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 483 484 // Handle Vectorcall CC 485 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 486 487 CCIfCC<"CallingConv::X86_RegCall", 488 CCIfSubtarget<"isTargetWin64()", CCIfRegCallv4<CCDelegateTo<RetCC_X86_Win64_RegCallv4>>>>, 489 490 CCIfCC<"CallingConv::X86_RegCall", 491 CCIfSubtarget<"isTargetWin64()", 492 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 493 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 494 495 // Mingw64 and native Win64 use Win64 CC 496 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 497 498 // Otherwise, drop to normal X86-64 CC 499 CCDelegateTo<RetCC_X86_64_C> 500]>; 501 502// This is the return-value convention used for the entire X86 backend. 503let Entry = 1 in 504def RetCC_X86 : CallingConv<[ 505 506 // Check if this is the Intel OpenCL built-ins calling convention 507 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 508 509 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 510 CCDelegateTo<RetCC_X86_32> 511]>; 512 513//===----------------------------------------------------------------------===// 514// X86-64 Argument Calling Conventions 515//===----------------------------------------------------------------------===// 516 517def CC_X86_64_C : CallingConv<[ 518 // Handles byval parameters. 519 CCIfByVal<CCPassByVal<8, 8>>, 520 521 // Promote i1/i8/i16/v1i1 arguments to i32. 522 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 523 524 // The 'nest' parameter, if any, is passed in R10. 525 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 526 CCIfNest<CCAssignToReg<[R10]>>, 527 528 // Pass SwiftSelf in a callee saved register. 529 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 530 531 // A SwiftError is passed in R12. 532 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 533 534 // Pass SwiftAsync in an otherwise callee saved register so that calls to 535 // normal functions don't need to save it somewhere. 536 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 537 538 // For Swift Calling Conventions, pass sret in %rax. 539 CCIfCC<"CallingConv::Swift", 540 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 541 CCIfCC<"CallingConv::SwiftTail", 542 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 543 544 // Pointers are always passed in full 64-bit registers. 545 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 546 547 // The first 6 integer arguments are passed in integer registers. 548 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 549 550 // i128 can be either passed in two i64 registers, or on the stack, but 551 // not split across register and stack. Handle this with a custom function. 552 CCIfType<[i64], 553 CCIfConsecutiveRegs<CCCustom<"CC_X86_64_I128">>>, 554 555 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 556 557 // Boolean vectors of AVX-512 are passed in SIMD registers. 558 // The call from AVX to AVX-512 function should work, 559 // since the boolean types in AVX/AVX2 are promoted by default. 560 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 561 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 562 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 563 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 564 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 565 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 566 567 // The first 8 FP/Vector arguments are passed in XMM registers. 568 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 569 CCIfSubtarget<"hasSSE1()", 570 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 571 572 // The first 8 256-bit vector arguments are passed in YMM registers, unless 573 // this is a vararg function. 574 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 575 // fixed arguments to vararg functions are supposed to be passed in 576 // registers. Actually modeling that would be a lot of work, though. 577 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 578 CCIfSubtarget<"hasAVX()", 579 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 580 YMM4, YMM5, YMM6, YMM7]>>>>, 581 582 // The first 8 512-bit vector arguments are passed in ZMM registers. 583 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 584 CCIfSubtarget<"hasAVX512()", 585 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 586 587 // Integer/FP values get stored in stack slots that are 8 bytes in size and 588 // 8-byte aligned if there are no more registers to hold them. 589 CCIfType<[i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>, 590 591 // Long doubles get stack slots whose size and alignment depends on the 592 // subtarget. 593 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 594 595 // Vectors get 16-byte stack slots that are 16-byte aligned. 596 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCAssignToStack<16, 16>>, 597 598 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 599 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 600 CCAssignToStack<32, 32>>, 601 602 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 603 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 604 CCAssignToStack<64, 64>> 605]>; 606 607// Calling convention used on Win64 608def CC_X86_Win64_C : CallingConv<[ 609 // FIXME: Handle varargs. 610 611 // Byval aggregates are passed by pointer 612 CCIfByVal<CCPassIndirect<i64>>, 613 614 // Promote i1/v1i1 arguments to i8. 615 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 616 617 // The 'nest' parameter, if any, is passed in R10. 618 CCIfNest<CCAssignToReg<[R10]>>, 619 620 // A SwiftError is passed in R12. 621 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 622 623 // Pass SwiftSelf in a callee saved register. 624 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 625 626 // Pass SwiftAsync in an otherwise callee saved register so that calls to 627 // normal functions don't need to save it somewhere. 628 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 629 630 // The 'CFGuardTarget' parameter, if any, is passed in RAX. 631 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>, 632 633 // 128 bit vectors are passed by pointer 634 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>, 635 636 // 256 bit vectors are passed by pointer 637 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>, 638 639 // 512 bit vectors are passed by pointer 640 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 641 642 // Long doubles are passed by pointer 643 CCIfType<[f80], CCPassIndirect<i64>>, 644 645 // If SSE was disabled, pass FP values smaller than 64-bits as integers in 646 // GPRs or on the stack. 647 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 648 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 649 650 // The first 4 FP/Vector arguments are passed in XMM registers. 651 CCIfType<[f16, f32, f64], 652 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 653 [RCX , RDX , R8 , R9 ]>>, 654 655 // The first 4 integer arguments are passed in integer registers. 656 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 657 [XMM0, XMM1, XMM2, XMM3]>>, 658 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 659 [XMM0, XMM1, XMM2, XMM3]>>, 660 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 661 [XMM0, XMM1, XMM2, XMM3]>>, 662 663 // Do not pass the sret argument in RCX, the Win64 thiscall calling 664 // convention requires "this" to be passed in RCX. 665 CCIfCC<"CallingConv::X86_ThisCall", 666 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 667 [XMM1, XMM2, XMM3]>>>>, 668 669 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 670 [XMM0, XMM1, XMM2, XMM3]>>, 671 672 // Integer/FP values get stored in stack slots that are 8 bytes in size and 673 // 8-byte aligned if there are no more registers to hold them. 674 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>> 675]>; 676 677def CC_X86_Win64_VectorCall : CallingConv<[ 678 CCCustom<"CC_X86_64_VectorCall">, 679 680 // Delegate to fastcall to handle integer types. 681 CCDelegateTo<CC_X86_Win64_C> 682]>; 683 684 685def CC_X86_64_GHC : CallingConv<[ 686 // Promote i8/i16/i32 arguments to i64. 687 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 688 689 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 690 CCIfType<[i64], 691 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 692 693 // Pass in STG registers: F1, F2, F3, F4, D1, D2 694 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 695 CCIfSubtarget<"hasSSE1()", 696 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 697 // AVX 698 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 699 CCIfSubtarget<"hasAVX()", 700 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 701 // AVX-512 702 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 703 CCIfSubtarget<"hasAVX512()", 704 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 705]>; 706 707def CC_X86_64_HiPE : CallingConv<[ 708 // Promote i8/i16/i32 arguments to i64. 709 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 710 711 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 712 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 713 714 // Integer/FP values get stored in stack slots that are 8 bytes in size and 715 // 8-byte aligned if there are no more registers to hold them. 716 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 717]>; 718 719// No explicit register is specified for the AnyReg calling convention. The 720// register allocator may assign the arguments to any free register. 721// 722// This calling convention is currently only supported by the stackmap and 723// patchpoint intrinsics. All other uses will result in an assert on Debug 724// builds. On Release builds we fallback to the X86 C calling convention. 725def CC_X86_64_AnyReg : CallingConv<[ 726 CCCustom<"CC_X86_AnyReg_Error"> 727]>; 728 729//===----------------------------------------------------------------------===// 730// X86 C Calling Convention 731//===----------------------------------------------------------------------===// 732 733/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 734/// values are spilled on the stack. 735def CC_X86_32_Vector_Common : CallingConv<[ 736 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 737 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 738 CCAssignToStack<16, 16>>, 739 740 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 741 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 742 CCAssignToStack<32, 32>>, 743 744 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 745 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 746 CCAssignToStack<64, 64>> 747]>; 748 749/// CC_X86_Win32_Vector - In X86 Win32 calling conventions, extra vector 750/// values are spilled on the stack. 751def CC_X86_Win32_Vector : CallingConv<[ 752 // Other SSE vectors get 16-byte stack slots that are 4-byte aligned. 753 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 754 CCAssignToStack<16, 4>>, 755 756 // 256-bit AVX vectors get 32-byte stack slots that are 4-byte aligned. 757 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 758 CCAssignToStack<32, 4>>, 759 760 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 4-byte aligned. 761 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 762 CCAssignToStack<64, 4>> 763]>; 764 765// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 766// vector registers 767def CC_X86_32_Vector_Standard : CallingConv<[ 768 // SSE vector arguments are passed in XMM registers. 769 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 770 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 771 772 // AVX 256-bit vector arguments are passed in YMM registers. 773 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 774 CCIfSubtarget<"hasAVX()", 775 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 776 777 // AVX 512-bit vector arguments are passed in ZMM registers. 778 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 779 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 780 781 CCIfIsVarArgOnWin<CCDelegateTo<CC_X86_Win32_Vector>>, 782 CCDelegateTo<CC_X86_32_Vector_Common> 783]>; 784 785// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 786// vector registers. 787def CC_X86_32_Vector_Darwin : CallingConv<[ 788 // SSE vector arguments are passed in XMM registers. 789 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 790 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 791 792 // AVX 256-bit vector arguments are passed in YMM registers. 793 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 794 CCIfSubtarget<"hasAVX()", 795 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 796 797 // AVX 512-bit vector arguments are passed in ZMM registers. 798 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 799 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 800 801 CCDelegateTo<CC_X86_32_Vector_Common> 802]>; 803 804/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 805/// values are spilled on the stack. 806def CC_X86_32_Common : CallingConv<[ 807 // Handles byval/preallocated parameters. 808 CCIfByVal<CCPassByVal<4, 4>>, 809 CCIfPreallocated<CCPassByVal<4, 4>>, 810 811 // The first 3 float or double arguments, if marked 'inreg' and if the call 812 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 813 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 814 CCIfSubtarget<"hasSSE2()", 815 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 816 817 CCIfNotVarArg<CCIfInReg<CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 818 819 CCIfType<[f16], CCAssignToStack<4, 4>>, 820 821 // Integer/Float values get stored in stack slots that are 4 bytes in 822 // size and 4-byte aligned. 823 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 824 825 // Doubles get 8-byte slots that are 4-byte aligned. 826 CCIfType<[f64], CCAssignToStack<8, 4>>, 827 828 // Long doubles get slots whose size and alignment depends on the subtarget. 829 CCIfType<[f80], CCAssignToStack<0, 0>>, 830 831 // Boolean vectors of AVX-512 are passed in SIMD registers. 832 // The call from AVX to AVX-512 function should work, 833 // since the boolean types in AVX/AVX2 are promoted by default. 834 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 835 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 836 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 837 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 838 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 839 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 840 841 // Darwin passes vectors in a form that differs from the i386 psABI 842 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 843 844 // Otherwise, drop to 'normal' X86-32 CC 845 CCDelegateTo<CC_X86_32_Vector_Standard> 846]>; 847 848def CC_X86_32_C : CallingConv<[ 849 // Promote i1/i8/i16/v1i1 arguments to i32. 850 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 851 852 // The 'nest' parameter, if any, is passed in ECX. 853 CCIfNest<CCAssignToReg<[ECX]>>, 854 855 // On swifttailcc pass swiftself in ECX. 856 CCIfCC<"CallingConv::SwiftTail", 857 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[ECX]>>>>, 858 859 // The first 3 integer arguments, if marked 'inreg' and if the call is not 860 // a vararg call, are passed in integer registers. 861 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 862 863 // Otherwise, same as everything else. 864 CCDelegateTo<CC_X86_32_Common> 865]>; 866 867def CC_X86_32_MCU : CallingConv<[ 868 // Handles byval parameters. Note that, like FastCC, we can't rely on 869 // the delegation to CC_X86_32_Common because that happens after code that 870 // puts arguments in registers. 871 CCIfByVal<CCPassByVal<4, 4>>, 872 873 // Promote i1/i8/i16/v1i1 arguments to i32. 874 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 875 876 // If the call is not a vararg call, some arguments may be passed 877 // in integer registers. 878 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 879 880 // Otherwise, same as everything else. 881 CCDelegateTo<CC_X86_32_Common> 882]>; 883 884def CC_X86_32_FastCall : CallingConv<[ 885 // Promote i1 to i8. 886 CCIfType<[i1], CCPromoteToType<i8>>, 887 888 // The 'nest' parameter, if any, is passed in EAX. 889 CCIfNest<CCAssignToReg<[EAX]>>, 890 891 // The first 2 integer arguments are passed in ECX/EDX 892 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 893 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 894 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 895 896 // Otherwise, same as everything else. 897 CCDelegateTo<CC_X86_32_Common> 898]>; 899 900def CC_X86_Win32_VectorCall : CallingConv<[ 901 // Pass floating point in XMMs 902 CCCustom<"CC_X86_32_VectorCall">, 903 904 // Delegate to fastcall to handle integer types. 905 CCDelegateTo<CC_X86_32_FastCall> 906]>; 907 908def CC_X86_32_ThisCall_Common : CallingConv<[ 909 // The first integer argument is passed in ECX 910 CCIfType<[i32], CCAssignToReg<[ECX]>>, 911 912 // Otherwise, same as everything else. 913 CCDelegateTo<CC_X86_32_Common> 914]>; 915 916def CC_X86_32_ThisCall_Mingw : CallingConv<[ 917 // Promote i1/i8/i16/v1i1 arguments to i32. 918 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 919 920 CCDelegateTo<CC_X86_32_ThisCall_Common> 921]>; 922 923def CC_X86_32_ThisCall_Win : CallingConv<[ 924 // Promote i1/i8/i16/v1i1 arguments to i32. 925 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 926 927 // Pass sret arguments indirectly through stack. 928 CCIfSRet<CCAssignToStack<4, 4>>, 929 930 CCDelegateTo<CC_X86_32_ThisCall_Common> 931]>; 932 933def CC_X86_32_ThisCall : CallingConv<[ 934 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 935 CCDelegateTo<CC_X86_32_ThisCall_Win> 936]>; 937 938def CC_X86_32_FastCC : CallingConv<[ 939 // Handles byval parameters. Note that we can't rely on the delegation 940 // to CC_X86_32_Common for this because that happens after code that 941 // puts arguments in registers. 942 CCIfByVal<CCPassByVal<4, 4>>, 943 944 // Promote i1/i8/i16/v1i1 arguments to i32. 945 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 946 947 // The 'nest' parameter, if any, is passed in EAX. 948 CCIfNest<CCAssignToReg<[EAX]>>, 949 950 // The first 2 integer arguments are passed in ECX/EDX 951 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 952 953 // The first 3 float or double arguments, if the call is not a vararg 954 // call and if SSE2 is available, are passed in SSE registers. 955 CCIfNotVarArg<CCIfType<[f32,f64], 956 CCIfSubtarget<"hasSSE2()", 957 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 958 959 // Doubles get 8-byte slots that are 8-byte aligned. 960 CCIfType<[f64], CCAssignToStack<8, 8>>, 961 962 // Otherwise, same as everything else. 963 CCDelegateTo<CC_X86_32_Common> 964]>; 965 966def CC_X86_Win32_CFGuard_Check : CallingConv<[ 967 // The CFGuard check call takes exactly one integer argument 968 // (i.e. the target function address), which is passed in ECX. 969 CCIfType<[i32], CCAssignToReg<[ECX]>> 970]>; 971 972def CC_X86_32_GHC : CallingConv<[ 973 // Promote i8/i16 arguments to i32. 974 CCIfType<[i8, i16], CCPromoteToType<i32>>, 975 976 // Pass in STG registers: Base, Sp, Hp, R1 977 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 978]>; 979 980def CC_X86_32_HiPE : CallingConv<[ 981 // Promote i8/i16 arguments to i32. 982 CCIfType<[i8, i16], CCPromoteToType<i32>>, 983 984 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 985 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 986 987 // Integer/Float values get stored in stack slots that are 4 bytes in 988 // size and 4-byte aligned. 989 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 990]>; 991 992// X86-64 Intel OpenCL built-ins calling convention. 993def CC_Intel_OCL_BI : CallingConv<[ 994 995 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 996 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 997 998 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 999 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 1000 1001 CCIfType<[i32], CCAssignToStack<4, 4>>, 1002 1003 // The SSE vector arguments are passed in XMM registers. 1004 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 1005 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 1006 1007 // The 256-bit vector arguments are passed in YMM registers. 1008 CCIfType<[v8f32, v4f64, v8i32, v4i64], 1009 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 1010 1011 // The 512-bit vector arguments are passed in ZMM registers. 1012 CCIfType<[v16f32, v8f64, v16i32, v8i64], 1013 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 1014 1015 // Pass masks in mask registers 1016 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 1017 1018 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1019 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 1020 CCDelegateTo<CC_X86_32_C> 1021]>; 1022 1023def CC_X86_64_Preserve_None : CallingConv<[ 1024 // We don't preserve general registers, so all of them can be used to pass 1025 // arguments except 1026 // - RBP frame pointer 1027 // - R10 'nest' parameter 1028 // - RBX base pointer 1029 // - R16 - R31 these are not available everywhere 1030 // Use non-volatile registers first, so functions using this convention can 1031 // call "normal" functions without saving and restoring incoming values: 1032 CCIfType<[i32], CCAssignToReg<[R12D, R13D, R14D, R15D, EDI, ESI, 1033 EDX, ECX, R8D, R9D, R11D, EAX]>>, 1034 1035 CCIfType<[i64], CCAssignToReg<[R12, R13, R14, R15, RDI, RSI, 1036 RDX, RCX, R8, R9, R11, RAX]>>, 1037 1038 // Otherwise it's the same as the regular C calling convention. 1039 CCDelegateTo<CC_X86_64_C> 1040]>; 1041 1042//===----------------------------------------------------------------------===// 1043// X86 Root Argument Calling Conventions 1044//===----------------------------------------------------------------------===// 1045 1046// This is the root argument convention for the X86-32 backend. 1047def CC_X86_32 : CallingConv<[ 1048 // X86_INTR calling convention is valid in MCU target and should override the 1049 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 1050 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1051 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1052 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1053 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1054 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1055 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>, 1056 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1057 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1058 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1059 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1060 CCIfCC<"CallingConv::X86_RegCall", 1061 CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<CC_X86_32_RegCallv4_Win>>>>, 1062 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1063 1064 // Otherwise, drop to normal X86-32 CC 1065 CCDelegateTo<CC_X86_32_C> 1066]>; 1067 1068// This is the root argument convention for the X86-64 backend. 1069def CC_X86_64 : CallingConv<[ 1070 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1071 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1072 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1073 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1074 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1075 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1076 CCIfCC<"CallingConv::X86_RegCall", 1077 CCIfSubtarget<"isTargetWin64()", CCIfRegCallv4<CCDelegateTo<CC_X86_Win64_RegCallv4>>>>, 1078 CCIfCC<"CallingConv::X86_RegCall", 1079 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1080 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1081 CCIfCC<"CallingConv::PreserveNone", CCDelegateTo<CC_X86_64_Preserve_None>>, 1082 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1083 1084 // Mingw64 and native Win64 use Win64 CC 1085 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1086 1087 // Otherwise, drop to normal X86-64 CC 1088 CCDelegateTo<CC_X86_64_C> 1089]>; 1090 1091// This is the argument convention used for the entire X86 backend. 1092let Entry = 1 in 1093def CC_X86 : CallingConv<[ 1094 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1095 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1096 CCDelegateTo<CC_X86_32> 1097]>; 1098 1099//===----------------------------------------------------------------------===// 1100// Callee-saved Registers. 1101//===----------------------------------------------------------------------===// 1102 1103def CSR_NoRegs : CalleeSavedRegs<(add)>; 1104 1105def CSR_IPRA_32 : CalleeSavedRegs<(add EBP, ESI)>; 1106def CSR_IPRA_64 : CalleeSavedRegs<(add RBP, RBX)>; 1107 1108def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1109def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1110 1111def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1112def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>; 1113 1114def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1115def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1116 1117def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1118 1119def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1120 (sequence "XMM%u", 6, 15))>; 1121 1122def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1123def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>; 1124 1125// The function used by Darwin to obtain the address of a thread-local variable 1126// uses rdi to pass a single parameter and rax for the return value. All other 1127// GPRs are preserved. 1128def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1129 R8, R9, R10, R11)>; 1130 1131// CSRs that are handled by prologue, epilogue. 1132def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1133 1134// CSRs that are handled explicitly via copies. 1135def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1136 1137// All GPRs - except r11 and return registers. 1138def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1139 R8, R9, R10)>; 1140 1141def CSR_Win64_RT_MostRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1142 (sequence "XMM%u", 6, 15))>; 1143 1144// All registers - except r11 and return registers. 1145def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1146 (sequence "XMM%u", 0, 15))>; 1147def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1148 (sequence "YMM%u", 0, 15))>; 1149 1150def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1151 R11, R12, R13, R14, R15, RBP, 1152 (sequence "XMM%u", 0, 15))>; 1153 1154def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1155 EDI)>; 1156def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1157 (sequence "XMM%u", 0, 7))>; 1158def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1159 (sequence "YMM%u", 0, 7))>; 1160def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1161 (sequence "ZMM%u", 0, 7), 1162 (sequence "K%u", 0, 7))>; 1163 1164def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1165def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1166 R10, R11, R12, R13, R14, R15, RBP)>; 1167def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1168 (sequence "YMM%u", 0, 15)), 1169 (sequence "XMM%u", 0, 15))>; 1170def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1171 (sequence "ZMM%u", 0, 31), 1172 (sequence "K%u", 0, 7)), 1173 (sequence "XMM%u", 0, 15))>; 1174def CSR_64_NoneRegs : CalleeSavedRegs<(add RBP)>; 1175 1176// Standard C + YMM6-15 1177def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1178 R13, R14, R15, 1179 (sequence "YMM%u", 6, 15))>; 1180 1181def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1182 R12, R13, R14, R15, 1183 (sequence "ZMM%u", 6, 21), 1184 K4, K5, K6, K7)>; 1185//Standard C + XMM 8-15 1186def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1187 (sequence "XMM%u", 8, 15))>; 1188 1189//Standard C + YMM 8-15 1190def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1191 (sequence "YMM%u", 8, 15))>; 1192 1193def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15, 1194 (sequence "ZMM%u", 16, 31), 1195 K4, K5, K6, K7)>; 1196 1197// Register calling convention preserves few GPR and XMM8-15 1198def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1199def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1200 (sequence "XMM%u", 4, 7))>; 1201def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>; 1202def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>; 1203def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1204 (sequence "R%u", 10, 15))>; 1205def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1206 (sequence "XMM%u", 8, 15))>; 1207def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1208 (sequence "R%u", 12, 15))>; 1209def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1210 (sequence "XMM%u", 8, 15))>; 1211