1 //=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file contains the WebAssembly implementation of the 11 /// TargetInstrInfo class. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H 16 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H 17 18 #include "WebAssemblyRegisterInfo.h" 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 22 #define GET_INSTRINFO_HEADER 23 #include "WebAssemblyGenInstrInfo.inc" 24 25 #define GET_INSTRINFO_OPERAND_ENUM 26 #include "WebAssemblyGenInstrInfo.inc" 27 28 namespace llvm { 29 30 namespace WebAssembly { 31 32 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 33 34 } 35 36 class WebAssemblySubtarget; 37 38 class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo { 39 const WebAssemblyRegisterInfo RI; 40 41 public: 42 explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI); 43 44 const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; } 45 46 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; 47 48 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 49 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 50 bool KillSrc, bool RenamableDest = false, 51 bool RenamableSrc = false) const override; 52 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 53 unsigned OpIdx1, 54 unsigned OpIdx2) const override; 55 56 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 57 MachineBasicBlock *&FBB, 58 SmallVectorImpl<MachineOperand> &Cond, 59 bool AllowModify = false) const override; 60 unsigned removeBranch(MachineBasicBlock &MBB, 61 int *BytesRemoved = nullptr) const override; 62 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 63 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 64 const DebugLoc &DL, 65 int *BytesAdded = nullptr) const override; 66 bool 67 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 68 69 ArrayRef<std::pair<int, const char *>> 70 getSerializableTargetIndices() const override; 71 72 const MachineOperand &getCalleeOperand(const MachineInstr &MI) const override; 73 74 bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index, 75 int64_t &Offset) const override; 76 }; 77 78 } // end namespace llvm 79 80 #endif 81