1 //===-- SystemZLongBranch.cpp - Branch lengthening for SystemZ ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This pass makes sure that all branches are in range. There are several ways 10 // in which this could be done. One aggressive approach is to assume that all 11 // branches are in range and successively replace those that turn out not 12 // to be in range with a longer form (branch relaxation). A simple 13 // implementation is to continually walk through the function relaxing 14 // branches until no more changes are needed and a fixed point is reached. 15 // However, in the pathological worst case, this implementation is 16 // quadratic in the number of blocks; relaxing branch N can make branch N-1 17 // go out of range, which in turn can make branch N-2 go out of range, 18 // and so on. 19 // 20 // An alternative approach is to assume that all branches must be 21 // converted to their long forms, then reinstate the short forms of 22 // branches that, even under this pessimistic assumption, turn out to be 23 // in range (branch shortening). This too can be implemented as a function 24 // walk that is repeated until a fixed point is reached. In general, 25 // the result of shortening is not as good as that of relaxation, and 26 // shortening is also quadratic in the worst case; shortening branch N 27 // can bring branch N-1 in range of the short form, which in turn can do 28 // the same for branch N-2, and so on. The main advantage of shortening 29 // is that each walk through the function produces valid code, so it is 30 // possible to stop at any point after the first walk. The quadraticness 31 // could therefore be handled with a maximum pass count, although the 32 // question then becomes: what maximum count should be used? 33 // 34 // On SystemZ, long branches are only needed for functions bigger than 64k, 35 // which are relatively rare to begin with, and the long branch sequences 36 // are actually relatively cheap. It therefore doesn't seem worth spending 37 // much compilation time on the problem. Instead, the approach we take is: 38 // 39 // (1) Work out the address that each block would have if no branches 40 // need relaxing. Exit the pass early if all branches are in range 41 // according to this assumption. 42 // 43 // (2) Work out the address that each block would have if all branches 44 // need relaxing. 45 // 46 // (3) Walk through the block calculating the final address of each instruction 47 // and relaxing those that need to be relaxed. For backward branches, 48 // this check uses the final address of the target block, as calculated 49 // earlier in the walk. For forward branches, this check uses the 50 // address of the target block that was calculated in (2). Both checks 51 // give a conservatively-correct range. 52 // 53 //===----------------------------------------------------------------------===// 54 55 #include "SystemZ.h" 56 #include "SystemZInstrInfo.h" 57 #include "SystemZTargetMachine.h" 58 #include "llvm/ADT/SmallVector.h" 59 #include "llvm/ADT/Statistic.h" 60 #include "llvm/ADT/StringRef.h" 61 #include "llvm/CodeGen/MachineBasicBlock.h" 62 #include "llvm/CodeGen/MachineFunction.h" 63 #include "llvm/CodeGen/MachineFunctionPass.h" 64 #include "llvm/CodeGen/MachineInstr.h" 65 #include "llvm/CodeGen/MachineInstrBuilder.h" 66 #include "llvm/IR/DebugLoc.h" 67 #include "llvm/Support/ErrorHandling.h" 68 #include <cassert> 69 #include <cstdint> 70 71 using namespace llvm; 72 73 #define DEBUG_TYPE "systemz-long-branch" 74 75 STATISTIC(LongBranches, "Number of long branches."); 76 77 namespace { 78 79 // Represents positional information about a basic block. 80 struct MBBInfo { 81 // The address that we currently assume the block has. 82 uint64_t Address = 0; 83 84 // The size of the block in bytes, excluding terminators. 85 // This value never changes. 86 uint64_t Size = 0; 87 88 // The minimum alignment of the block. 89 // This value never changes. 90 Align Alignment; 91 92 // The number of terminators in this block. This value never changes. 93 unsigned NumTerminators = 0; 94 95 MBBInfo() = default; 96 }; 97 98 // Represents the state of a block terminator. 99 struct TerminatorInfo { 100 // If this terminator is a relaxable branch, this points to the branch 101 // instruction, otherwise it is null. 102 MachineInstr *Branch = nullptr; 103 104 // The address that we currently assume the terminator has. 105 uint64_t Address = 0; 106 107 // The current size of the terminator in bytes. 108 uint64_t Size = 0; 109 110 // If Branch is nonnull, this is the number of the target block, 111 // otherwise it is unused. 112 unsigned TargetBlock = 0; 113 114 // If Branch is nonnull, this is the length of the longest relaxed form, 115 // otherwise it is zero. 116 unsigned ExtraRelaxSize = 0; 117 118 TerminatorInfo() = default; 119 }; 120 121 // Used to keep track of the current position while iterating over the blocks. 122 struct BlockPosition { 123 // The address that we assume this position has. 124 uint64_t Address = 0; 125 126 // The number of low bits in Address that are known to be the same 127 // as the runtime address. 128 unsigned KnownBits; 129 130 BlockPosition(unsigned InitialLogAlignment) 131 : KnownBits(InitialLogAlignment) {} 132 }; 133 134 class SystemZLongBranch : public MachineFunctionPass { 135 public: 136 static char ID; 137 138 SystemZLongBranch() : MachineFunctionPass(ID) { 139 initializeSystemZLongBranchPass(*PassRegistry::getPassRegistry()); 140 } 141 142 bool runOnMachineFunction(MachineFunction &F) override; 143 144 MachineFunctionProperties getRequiredProperties() const override { 145 return MachineFunctionProperties().set( 146 MachineFunctionProperties::Property::NoVRegs); 147 } 148 149 private: 150 void skipNonTerminators(BlockPosition &Position, MBBInfo &Block); 151 void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator, 152 bool AssumeRelaxed); 153 TerminatorInfo describeTerminator(MachineInstr &MI); 154 uint64_t initMBBInfo(); 155 bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address); 156 bool mustRelaxABranch(); 157 void setWorstCaseAddresses(); 158 void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode); 159 void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode); 160 void relaxBranch(TerminatorInfo &Terminator); 161 void relaxBranches(); 162 163 const SystemZInstrInfo *TII = nullptr; 164 MachineFunction *MF = nullptr; 165 SmallVector<MBBInfo, 16> MBBs; 166 SmallVector<TerminatorInfo, 16> Terminators; 167 }; 168 169 char SystemZLongBranch::ID = 0; 170 171 const uint64_t MaxBackwardRange = 0x10000; 172 const uint64_t MaxForwardRange = 0xfffe; 173 174 } // end anonymous namespace 175 176 INITIALIZE_PASS(SystemZLongBranch, DEBUG_TYPE, "SystemZ Long Branch", false, 177 false) 178 179 // Position describes the state immediately before Block. Update Block 180 // accordingly and move Position to the end of the block's non-terminator 181 // instructions. 182 void SystemZLongBranch::skipNonTerminators(BlockPosition &Position, 183 MBBInfo &Block) { 184 if (Log2(Block.Alignment) > Position.KnownBits) { 185 // When calculating the address of Block, we need to conservatively 186 // assume that Block had the worst possible misalignment. 187 Position.Address += 188 (Block.Alignment.value() - (uint64_t(1) << Position.KnownBits)); 189 Position.KnownBits = Log2(Block.Alignment); 190 } 191 192 // Align the addresses. 193 Position.Address = alignTo(Position.Address, Block.Alignment); 194 195 // Record the block's position. 196 Block.Address = Position.Address; 197 198 // Move past the non-terminators in the block. 199 Position.Address += Block.Size; 200 } 201 202 // Position describes the state immediately before Terminator. 203 // Update Terminator accordingly and move Position past it. 204 // Assume that Terminator will be relaxed if AssumeRelaxed. 205 void SystemZLongBranch::skipTerminator(BlockPosition &Position, 206 TerminatorInfo &Terminator, 207 bool AssumeRelaxed) { 208 Terminator.Address = Position.Address; 209 Position.Address += Terminator.Size; 210 if (AssumeRelaxed) 211 Position.Address += Terminator.ExtraRelaxSize; 212 } 213 214 static unsigned getInstSizeInBytes(const MachineInstr &MI, 215 const SystemZInstrInfo *TII) { 216 unsigned Size = TII->getInstSizeInBytes(MI); 217 assert((Size || 218 // These do not have a size: 219 MI.isDebugOrPseudoInstr() || MI.isPosition() || MI.isKill() || 220 MI.isImplicitDef() || MI.getOpcode() == TargetOpcode::MEMBARRIER || 221 // These have a size that may be zero: 222 MI.isInlineAsm() || MI.getOpcode() == SystemZ::STACKMAP || 223 MI.getOpcode() == SystemZ::PATCHPOINT || 224 // EH_SjLj_Setup is a dummy terminator instruction of size 0, 225 // It is used to handle the clobber register for builtin setjmp. 226 MI.getOpcode() == SystemZ::EH_SjLj_Setup) && 227 "Missing size value for instruction."); 228 return Size; 229 } 230 231 // Return a description of terminator instruction MI. 232 TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr &MI) { 233 TerminatorInfo Terminator; 234 Terminator.Size = getInstSizeInBytes(MI, TII); 235 if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) { 236 switch (MI.getOpcode()) { 237 case SystemZ::J: 238 // Relaxes to JG, which is 2 bytes longer. 239 Terminator.ExtraRelaxSize = 2; 240 break; 241 case SystemZ::BRC: 242 // Relaxes to BRCL, which is 2 bytes longer. 243 Terminator.ExtraRelaxSize = 2; 244 break; 245 case SystemZ::BRCT: 246 case SystemZ::BRCTG: 247 // Relaxes to A(G)HI and BRCL, which is 6 bytes longer. 248 Terminator.ExtraRelaxSize = 6; 249 break; 250 case SystemZ::BRCTH: 251 // Never needs to be relaxed. 252 Terminator.ExtraRelaxSize = 0; 253 break; 254 case SystemZ::CRJ: 255 case SystemZ::CLRJ: 256 // Relaxes to a C(L)R/BRCL sequence, which is 2 bytes longer. 257 Terminator.ExtraRelaxSize = 2; 258 break; 259 case SystemZ::CGRJ: 260 case SystemZ::CLGRJ: 261 // Relaxes to a C(L)GR/BRCL sequence, which is 4 bytes longer. 262 Terminator.ExtraRelaxSize = 4; 263 break; 264 case SystemZ::CIJ: 265 case SystemZ::CGIJ: 266 // Relaxes to a C(G)HI/BRCL sequence, which is 4 bytes longer. 267 Terminator.ExtraRelaxSize = 4; 268 break; 269 case SystemZ::CLIJ: 270 case SystemZ::CLGIJ: 271 // Relaxes to a CL(G)FI/BRCL sequence, which is 6 bytes longer. 272 Terminator.ExtraRelaxSize = 6; 273 break; 274 default: 275 llvm_unreachable("Unrecognized branch instruction"); 276 } 277 Terminator.Branch = &MI; 278 Terminator.TargetBlock = 279 TII->getBranchInfo(MI).getMBBTarget()->getNumber(); 280 } 281 return Terminator; 282 } 283 284 // Fill MBBs and Terminators, setting the addresses on the assumption 285 // that no branches need relaxation. Return the size of the function under 286 // this assumption. 287 uint64_t SystemZLongBranch::initMBBInfo() { 288 MF->RenumberBlocks(); 289 unsigned NumBlocks = MF->size(); 290 291 MBBs.clear(); 292 MBBs.resize(NumBlocks); 293 294 Terminators.clear(); 295 Terminators.reserve(NumBlocks); 296 297 BlockPosition Position(Log2(MF->getAlignment())); 298 for (unsigned I = 0; I < NumBlocks; ++I) { 299 MachineBasicBlock *MBB = MF->getBlockNumbered(I); 300 MBBInfo &Block = MBBs[I]; 301 302 // Record the alignment, for quick access. 303 Block.Alignment = MBB->getAlignment(); 304 305 // Calculate the size of the fixed part of the block. 306 MachineBasicBlock::iterator MI = MBB->begin(); 307 MachineBasicBlock::iterator End = MBB->end(); 308 while (MI != End && !MI->isTerminator()) { 309 Block.Size += getInstSizeInBytes(*MI, TII); 310 ++MI; 311 } 312 skipNonTerminators(Position, Block); 313 314 // Add the terminators. 315 while (MI != End) { 316 if (!MI->isDebugInstr()) { 317 assert(MI->isTerminator() && "Terminator followed by non-terminator"); 318 Terminators.push_back(describeTerminator(*MI)); 319 skipTerminator(Position, Terminators.back(), false); 320 ++Block.NumTerminators; 321 } 322 ++MI; 323 } 324 } 325 326 return Position.Address; 327 } 328 329 // Return true if, under current assumptions, Terminator would need to be 330 // relaxed if it were placed at address Address. 331 bool SystemZLongBranch::mustRelaxBranch(const TerminatorInfo &Terminator, 332 uint64_t Address) { 333 if (!Terminator.Branch || Terminator.ExtraRelaxSize == 0) 334 return false; 335 336 const MBBInfo &Target = MBBs[Terminator.TargetBlock]; 337 if (Address >= Target.Address) { 338 if (Address - Target.Address <= MaxBackwardRange) 339 return false; 340 } else { 341 if (Target.Address - Address <= MaxForwardRange) 342 return false; 343 } 344 345 return true; 346 } 347 348 // Return true if, under current assumptions, any terminator needs 349 // to be relaxed. 350 bool SystemZLongBranch::mustRelaxABranch() { 351 for (auto &Terminator : Terminators) 352 if (mustRelaxBranch(Terminator, Terminator.Address)) 353 return true; 354 return false; 355 } 356 357 // Set the address of each block on the assumption that all branches 358 // must be long. 359 void SystemZLongBranch::setWorstCaseAddresses() { 360 SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin(); 361 BlockPosition Position(Log2(MF->getAlignment())); 362 for (auto &Block : MBBs) { 363 skipNonTerminators(Position, Block); 364 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { 365 skipTerminator(Position, *TI, true); 366 ++TI; 367 } 368 } 369 } 370 371 // Split BRANCH ON COUNT MI into the addition given by AddOpcode followed 372 // by a BRCL on the result. 373 void SystemZLongBranch::splitBranchOnCount(MachineInstr *MI, 374 unsigned AddOpcode) { 375 MachineBasicBlock *MBB = MI->getParent(); 376 DebugLoc DL = MI->getDebugLoc(); 377 BuildMI(*MBB, MI, DL, TII->get(AddOpcode)) 378 .add(MI->getOperand(0)) 379 .add(MI->getOperand(1)) 380 .addImm(-1); 381 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 382 .addImm(SystemZ::CCMASK_ICMP) 383 .addImm(SystemZ::CCMASK_CMP_NE) 384 .add(MI->getOperand(2)); 385 // The implicit use of CC is a killing use. 386 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo()); 387 MI->eraseFromParent(); 388 } 389 390 // Split MI into the comparison given by CompareOpcode followed 391 // a BRCL on the result. 392 void SystemZLongBranch::splitCompareBranch(MachineInstr *MI, 393 unsigned CompareOpcode) { 394 MachineBasicBlock *MBB = MI->getParent(); 395 DebugLoc DL = MI->getDebugLoc(); 396 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode)) 397 .add(MI->getOperand(0)) 398 .add(MI->getOperand(1)); 399 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL)) 400 .addImm(SystemZ::CCMASK_ICMP) 401 .add(MI->getOperand(2)) 402 .add(MI->getOperand(3)); 403 // The implicit use of CC is a killing use. 404 BRCL->addRegisterKilled(SystemZ::CC, &TII->getRegisterInfo()); 405 MI->eraseFromParent(); 406 } 407 408 // Relax the branch described by Terminator. 409 void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) { 410 MachineInstr *Branch = Terminator.Branch; 411 switch (Branch->getOpcode()) { 412 case SystemZ::J: 413 Branch->setDesc(TII->get(SystemZ::JG)); 414 break; 415 case SystemZ::BRC: 416 Branch->setDesc(TII->get(SystemZ::BRCL)); 417 break; 418 case SystemZ::BRCT: 419 splitBranchOnCount(Branch, SystemZ::AHI); 420 break; 421 case SystemZ::BRCTG: 422 splitBranchOnCount(Branch, SystemZ::AGHI); 423 break; 424 case SystemZ::CRJ: 425 splitCompareBranch(Branch, SystemZ::CR); 426 break; 427 case SystemZ::CGRJ: 428 splitCompareBranch(Branch, SystemZ::CGR); 429 break; 430 case SystemZ::CIJ: 431 splitCompareBranch(Branch, SystemZ::CHI); 432 break; 433 case SystemZ::CGIJ: 434 splitCompareBranch(Branch, SystemZ::CGHI); 435 break; 436 case SystemZ::CLRJ: 437 splitCompareBranch(Branch, SystemZ::CLR); 438 break; 439 case SystemZ::CLGRJ: 440 splitCompareBranch(Branch, SystemZ::CLGR); 441 break; 442 case SystemZ::CLIJ: 443 splitCompareBranch(Branch, SystemZ::CLFI); 444 break; 445 case SystemZ::CLGIJ: 446 splitCompareBranch(Branch, SystemZ::CLGFI); 447 break; 448 default: 449 llvm_unreachable("Unrecognized branch"); 450 } 451 452 Terminator.Size += Terminator.ExtraRelaxSize; 453 Terminator.ExtraRelaxSize = 0; 454 Terminator.Branch = nullptr; 455 456 ++LongBranches; 457 } 458 459 // Run a shortening pass and relax any branches that need to be relaxed. 460 void SystemZLongBranch::relaxBranches() { 461 SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin(); 462 BlockPosition Position(Log2(MF->getAlignment())); 463 for (auto &Block : MBBs) { 464 skipNonTerminators(Position, Block); 465 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { 466 assert(Position.Address <= TI->Address && 467 "Addresses shouldn't go forwards"); 468 if (mustRelaxBranch(*TI, Position.Address)) 469 relaxBranch(*TI); 470 skipTerminator(Position, *TI, false); 471 ++TI; 472 } 473 } 474 } 475 476 bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) { 477 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo()); 478 MF = &F; 479 uint64_t Size = initMBBInfo(); 480 if (Size <= MaxForwardRange || !mustRelaxABranch()) 481 return false; 482 483 setWorstCaseAddresses(); 484 relaxBranches(); 485 return true; 486 } 487 488 FunctionPass *llvm::createSystemZLongBranchPass(SystemZTargetMachine &TM) { 489 return new SystemZLongBranch(); 490 } 491