1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Sparc implementation of TargetFrameLowering class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "SparcFrameLowering.h" 14 #include "SparcInstrInfo.h" 15 #include "SparcMachineFunctionInfo.h" 16 #include "SparcSubtarget.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineModuleInfo.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Target/TargetOptions.h" 24 25 using namespace llvm; 26 27 static cl::opt<bool> 28 DisableLeafProc("disable-sparc-leaf-proc", 29 cl::init(false), 30 cl::desc("Disable Sparc leaf procedure optimization."), 31 cl::Hidden); 32 33 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST) 34 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 35 ST.is64Bit() ? Align(16) : Align(8), 0, 36 ST.is64Bit() ? Align(16) : Align(8), 37 /*StackRealignable=*/false) {} 38 39 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF, 40 MachineBasicBlock &MBB, 41 MachineBasicBlock::iterator MBBI, 42 int NumBytes, 43 unsigned ADDrr, 44 unsigned ADDri) const { 45 46 DebugLoc dl; 47 const SparcInstrInfo &TII = 48 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); 49 50 if (NumBytes >= -4096 && NumBytes < 4096) { 51 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) 52 .addReg(SP::O6).addImm(NumBytes); 53 return; 54 } 55 56 // Emit this the hard way. This clobbers G1 which we always know is 57 // available here. 58 if (NumBytes >= 0) { 59 // Emit nonnegative numbers with sethi + or. 60 // sethi %hi(NumBytes), %g1 61 // or %g1, %lo(NumBytes), %g1 62 // add %sp, %g1, %sp 63 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) 64 .addImm(HI22(NumBytes)); 65 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) 66 .addReg(SP::G1).addImm(LO10(NumBytes)); 67 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) 68 .addReg(SP::O6).addReg(SP::G1); 69 return ; 70 } 71 72 // Emit negative numbers with sethi + xor. 73 // sethi %hix(NumBytes), %g1 74 // xor %g1, %lox(NumBytes), %g1 75 // add %sp, %g1, %sp 76 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) 77 .addImm(HIX22(NumBytes)); 78 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) 79 .addReg(SP::G1).addImm(LOX10(NumBytes)); 80 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) 81 .addReg(SP::O6).addReg(SP::G1); 82 } 83 84 void SparcFrameLowering::emitPrologue(MachineFunction &MF, 85 MachineBasicBlock &MBB) const { 86 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 87 88 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); 89 MachineFrameInfo &MFI = MF.getFrameInfo(); 90 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); 91 const SparcInstrInfo &TII = 92 *static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo()); 93 const SparcRegisterInfo &RegInfo = 94 *static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo()); 95 MachineBasicBlock::iterator MBBI = MBB.begin(); 96 // Debug location must be unknown since the first debug location is used 97 // to determine the end of the prologue. 98 DebugLoc dl; 99 100 // Get the number of bytes to allocate from the FrameInfo 101 int NumBytes = (int) MFI.getStackSize(); 102 103 unsigned SAVEri = SP::SAVEri; 104 unsigned SAVErr = SP::SAVErr; 105 if (FuncInfo->isLeafProc()) { 106 if (NumBytes == 0) 107 return; 108 SAVEri = SP::ADDri; 109 SAVErr = SP::ADDrr; 110 } 111 112 // The SPARC ABI is a bit odd in that it requires a reserved 92-byte 113 // (128 in v9) area in the user's stack, starting at %sp. Thus, the 114 // first part of the stack that can actually be used is located at 115 // %sp + 92. 116 // 117 // We therefore need to add that offset to the total stack size 118 // after all the stack objects are placed by 119 // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be 120 // aligned *after* the extra size is added, we need to disable 121 // calculateFrameObjectOffsets's built-in stack alignment, by having 122 // targetHandlesStackFrameRounding return true. 123 124 125 // Add the extra call frame stack size, if needed. (This is the same 126 // code as in PrologEpilogInserter, but also gets disabled by 127 // targetHandlesStackFrameRounding) 128 if (MFI.adjustsStack() && hasReservedCallFrame(MF)) 129 NumBytes += MFI.getMaxCallFrameSize(); 130 131 // Adds the SPARC subtarget-specific spill area to the stack 132 // size. Also ensures target-required alignment. 133 NumBytes = Subtarget.getAdjustedFrameSize(NumBytes); 134 135 // Finally, ensure that the size is sufficiently aligned for the 136 // data on the stack. 137 NumBytes = alignTo(NumBytes, MFI.getMaxAlign()); 138 139 // Update stack size with corrected value. 140 MFI.setStackSize(NumBytes); 141 142 emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri); 143 144 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); 145 146 // Emit ".cfi_def_cfa_register 30". 147 unsigned CFIIndex = 148 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP)); 149 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 150 .addCFIIndex(CFIIndex); 151 152 // Emit ".cfi_window_save". 153 CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr)); 154 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 155 .addCFIIndex(CFIIndex); 156 157 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); 158 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); 159 // Emit ".cfi_register 15, 31". 160 CFIIndex = MF.addFrameInst( 161 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); 162 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 163 .addCFIIndex(CFIIndex); 164 } 165 166 MachineBasicBlock::iterator SparcFrameLowering:: 167 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 168 MachineBasicBlock::iterator I) const { 169 if (!hasReservedCallFrame(MF)) { 170 MachineInstr &MI = *I; 171 int Size = MI.getOperand(0).getImm(); 172 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 173 Size = -Size; 174 175 if (Size) 176 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); 177 } 178 return MBB.erase(I); 179 } 180 181 182 void SparcFrameLowering::emitEpilogue(MachineFunction &MF, 183 MachineBasicBlock &MBB) const { 184 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 185 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 186 const SparcInstrInfo &TII = 187 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); 188 DebugLoc dl = MBBI->getDebugLoc(); 189 assert((MBBI->getOpcode() == SP::RETL || MBBI->getOpcode() == SP::TAIL_CALL || 190 MBBI->getOpcode() == SP::TAIL_CALLri) && 191 "Can only put epilog before 'retl' or 'tail_call' instruction!"); 192 if (!FuncInfo->isLeafProc()) { 193 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) 194 .addReg(SP::G0); 195 return; 196 } 197 MachineFrameInfo &MFI = MF.getFrameInfo(); 198 199 int NumBytes = (int) MFI.getStackSize(); 200 if (NumBytes != 0) 201 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); 202 203 // Preserve return address in %o7 204 if (MBBI->getOpcode() == SP::TAIL_CALL) { 205 MBB.addLiveIn(SP::O7); 206 BuildMI(MBB, MBBI, dl, TII.get(SP::ORrr), SP::G1) 207 .addReg(SP::G0) 208 .addReg(SP::O7); 209 BuildMI(MBB, MBBI, dl, TII.get(SP::ORrr), SP::O7) 210 .addReg(SP::G0) 211 .addReg(SP::G1); 212 } 213 } 214 215 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 216 // Reserve call frame if there are no variable sized objects on the stack. 217 return !MF.getFrameInfo().hasVarSizedObjects(); 218 } 219 220 // hasFPImpl - Return true if the specified function should have a dedicated 221 // frame pointer register. This is true if the function has variable sized 222 // allocas or if frame pointer elimination is disabled. 223 bool SparcFrameLowering::hasFPImpl(const MachineFunction &MF) const { 224 const MachineFrameInfo &MFI = MF.getFrameInfo(); 225 return MF.getTarget().Options.DisableFramePointerElim(MF) || 226 MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken(); 227 } 228 229 StackOffset 230 SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 231 Register &FrameReg) const { 232 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); 233 const MachineFrameInfo &MFI = MF.getFrameInfo(); 234 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 235 const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 236 bool isFixed = MFI.isFixedObjectIndex(FI); 237 238 // Addressable stack objects are accessed using neg. offsets from 239 // %fp, or positive offsets from %sp. 240 bool UseFP; 241 242 // Sparc uses FP-based references in general, even when "hasFP" is 243 // false. That function is rather a misnomer, because %fp is 244 // actually always available, unless isLeafProc. 245 if (FuncInfo->isLeafProc()) { 246 // If there's a leaf proc, all offsets need to be %sp-based, 247 // because we haven't caused %fp to actually point to our frame. 248 UseFP = false; 249 } else if (isFixed) { 250 // Otherwise, argument access should always use %fp. 251 UseFP = true; 252 } else { 253 // Finally, default to using %fp. 254 UseFP = true; 255 } 256 257 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) + 258 Subtarget.getStackPointerBias(); 259 260 if (UseFP) { 261 FrameReg = RegInfo->getFrameRegister(MF); 262 return StackOffset::getFixed(FrameOffset); 263 } else { 264 FrameReg = SP::O6; // %sp 265 return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize()); 266 } 267 } 268 269 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) 270 { 271 272 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) 273 if (MRI->isPhysRegUsed(reg)) 274 return false; 275 276 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg) 277 if (MRI->isPhysRegUsed(reg)) 278 return false; 279 280 return true; 281 } 282 283 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const 284 { 285 286 MachineRegisterInfo &MRI = MF.getRegInfo(); 287 MachineFrameInfo &MFI = MF.getFrameInfo(); 288 289 return !(MFI.hasCalls() // has calls 290 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed 291 || MRI.isPhysRegUsed(SP::O6) // %sp is used 292 || hasFP(MF) // need %fp 293 || MF.hasInlineAsm()); // has inline assembly 294 } 295 296 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { 297 MachineRegisterInfo &MRI = MF.getRegInfo(); 298 // Remap %i[0-7] to %o[0-7]. 299 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { 300 if (!MRI.isPhysRegUsed(reg)) 301 continue; 302 303 unsigned mapped_reg = reg - SP::I0 + SP::O0; 304 305 // Replace I register with O register. 306 MRI.replaceRegWith(reg, mapped_reg); 307 308 // Also replace register pair super-registers. 309 if ((reg - SP::I0) % 2 == 0) { 310 unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1; 311 unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1; 312 MRI.replaceRegWith(preg, mapped_preg); 313 } 314 } 315 316 // Rewrite MBB's Live-ins. 317 for (MachineBasicBlock &MBB : MF) { 318 for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) { 319 if (!MBB.isLiveIn(reg)) 320 continue; 321 MBB.removeLiveIn(reg); 322 MBB.addLiveIn(reg - SP::I0_I1 + SP::O0_O1); 323 } 324 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { 325 if (!MBB.isLiveIn(reg)) 326 continue; 327 MBB.removeLiveIn(reg); 328 MBB.addLiveIn(reg - SP::I0 + SP::O0); 329 } 330 } 331 332 assert(verifyLeafProcRegUse(&MRI)); 333 #ifdef EXPENSIVE_CHECKS 334 MF.verify(0, "After LeafProc Remapping"); 335 #endif 336 } 337 338 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF, 339 BitVector &SavedRegs, 340 RegScavenger *RS) const { 341 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 342 if (!DisableLeafProc && isLeafProc(MF)) { 343 SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>(); 344 MFI->setLeafProc(true); 345 346 remapRegsForLeafProc(MF); 347 } 348 349 } 350