1//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// RISC-V system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// CSR (control and status register read/write) instruction options. 18//===----------------------------------------------------------------------===// 19 20class SysReg<string name, bits<12> op> { 21 string Name = name; 22 bits<12> Encoding = op; 23 // FIXME: add these additional fields when needed. 24 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. 25 // Privilege Mode: User = 0, System = 1 or Machine = 3. 26 // bits<2> ReadWrite = op{11 - 10}; 27 // bits<2> XMode = op{9 - 8}; 28 // Check Extra field name and what bits 7-6 correspond to. 29 // bits<2> Extra = op{7 - 6}; 30 // Register number without the privilege bits. 31 // bits<6> Number = op{5 - 0}; 32 code FeaturesRequired = [{ {} }]; 33 bit isRV32Only = 0; 34 bit isAltName = 0; 35 bit isDeprecatedName = 0; 36} 37 38def SysRegsList : GenericTable { 39 let FilterClass = "SysReg"; 40 // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. 41 let Fields = [ 42 "Name", "Encoding", "FeaturesRequired", 43 "isRV32Only", "isAltName", "isDeprecatedName" 44 ]; 45 46 let PrimaryKey = [ "Encoding" ]; 47 let PrimaryKeyName = "lookupSysRegByEncoding"; 48 let PrimaryKeyReturnRange = true; 49} 50 51def SysRegEncodings : GenericEnum { 52 let FilterClass = "SysReg"; 53 let NameField = "Name"; 54 let ValueField = "Encoding"; 55} 56 57def lookupSysRegByName : SearchIndex { 58 let Table = SysRegsList; 59 let Key = [ "Name" ]; 60} 61 62// The following CSR encodings match those given in Tables 2.2, 63// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual 64// Volume II: Privileged Architecture. 65 66//===----------------------------------------------------------------------===// 67// User Floating-Point CSRs 68//===----------------------------------------------------------------------===// 69 70def SysRegFFLAGS : SysReg<"fflags", 0x001>; 71def SysRegFRM : SysReg<"frm", 0x002>; 72def SysRegFCSR : SysReg<"fcsr", 0x003>; 73 74//===----------------------------------------------------------------------===// 75// User Counter/Timers 76//===----------------------------------------------------------------------===// 77def CYCLE : SysReg<"cycle", 0xC00>; 78def TIME : SysReg<"time", 0xC01>; 79def INSTRET : SysReg<"instret", 0xC02>; 80 81// hpmcounter3-hpmcounter31 at 0xC03-0xC1F. 82foreach i = 3...31 in 83 def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>; 84 85let isRV32Only = 1 in { 86def CYCLEH : SysReg<"cycleh", 0xC80>; 87def TIMEH : SysReg<"timeh", 0xC81>; 88def INSTRETH : SysReg<"instreth", 0xC82>; 89 90// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F. 91foreach i = 3...31 in 92 def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>; 93} 94 95//===----------------------------------------------------------------------===// 96// Supervisor Trap Setup 97//===----------------------------------------------------------------------===// 98def : SysReg<"sstatus", 0x100>; 99def : SysReg<"sie", 0x104>; 100def : SysReg<"stvec", 0x105>; 101def : SysReg<"scounteren", 0x106>; 102def : SysReg<"stimecmp", 0x14D>; 103let isRV32Only = 1 in 104def : SysReg<"stimecmph", 0x15D>; 105 106//===----------------------------------------------------------------------===// 107// Supervisor Configuration 108//===----------------------------------------------------------------------===// 109 110def : SysReg<"senvcfg", 0x10A>; 111 112//===----------------------------------------------------------------------===// 113// Supervisor Trap Handling 114//===----------------------------------------------------------------------===// 115def : SysReg<"sscratch", 0x140>; 116def : SysReg<"sepc", 0x141>; 117def : SysReg<"scause", 0x142>; 118def : SysReg<"stval", 0x143>; 119let isDeprecatedName = 1 in 120def : SysReg<"sbadaddr", 0x143>; 121def : SysReg<"sip", 0x144>; 122 123//===----------------------------------------------------------------------===// 124// Supervisor Protection and Translation 125//===----------------------------------------------------------------------===// 126def : SysReg<"satp", 0x180>; 127let isDeprecatedName = 1 in 128def : SysReg<"sptbr", 0x180>; 129 130//===----------------------------------------------------------------------===// 131// Quality-of-Service(QoS) Identifiers (Ssqosid) 132//===----------------------------------------------------------------------===// 133def : SysReg<"srmcfg", 0x181>; 134 135//===----------------------------------------------------------------------===// 136// Debug/Trace Registers 137//===----------------------------------------------------------------------===// 138 139def : SysReg<"scontext", 0x5A8>; 140 141//===----------------------------------------------------------------------===// 142// Supervisor Count Overflow (defined in Sscofpmf) 143//===----------------------------------------------------------------------===// 144 145def : SysReg<"scountovf", 0xDA0>; 146 147//===----------------------------------------------------------------------===// 148// Hypervisor Trap Setup 149//===----------------------------------------------------------------------===// 150 151def : SysReg<"hstatus", 0x600>; 152def : SysReg<"hedeleg", 0x602>; 153def : SysReg<"hideleg", 0x603>; 154def : SysReg<"hie", 0x604>; 155def : SysReg<"hcounteren", 0x606>; 156def : SysReg<"hgeie", 0x607>; 157 158//===----------------------------------------------------------------------===// 159// Hypervisor Trap Handling 160//===----------------------------------------------------------------------===// 161 162def : SysReg<"htval", 0x643>; 163def : SysReg<"hip", 0x644>; 164def : SysReg<"hvip", 0x645>; 165def : SysReg<"htinst", 0x64A>; 166def : SysReg<"hgeip", 0xE12>; 167 168//===----------------------------------------------------------------------===// 169// Hypervisor Configuration 170//===----------------------------------------------------------------------===// 171 172def : SysReg<"henvcfg", 0x60A>; 173let isRV32Only = 1 in 174def : SysReg<"henvcfgh", 0x61A>; 175 176//===----------------------------------------------------------------------===// 177// Hypervisor Protection and Translation 178//===----------------------------------------------------------------------===// 179 180def : SysReg<"hgatp", 0x680>; 181 182//===----------------------------------------------------------------------===// 183// Debug/Trace Registers 184//===----------------------------------------------------------------------===// 185 186def : SysReg<"hcontext", 0x6A8>; 187 188//===----------------------------------------------------------------------===// 189// Hypervisor Counter/Timer Virtualization Registers 190//===----------------------------------------------------------------------===// 191 192def : SysReg<"htimedelta", 0x605>; 193let isRV32Only = 1 in 194def : SysReg<"htimedeltah", 0x615>; 195 196//===----------------------------------------------------------------------===// 197// Virtual Supervisor Registers 198//===----------------------------------------------------------------------===// 199 200def : SysReg<"vsstatus", 0x200>; 201def : SysReg<"vsie", 0x204>; 202def : SysReg<"vstvec", 0x205>; 203def : SysReg<"vsscratch", 0x240>; 204def : SysReg<"vsepc", 0x241>; 205def : SysReg<"vscause", 0x242>; 206def : SysReg<"vstval", 0x243>; 207def : SysReg<"vsip", 0x244>; 208def : SysReg<"vstimecmp", 0x24D>; 209let isRV32Only = 1 in 210def : SysReg<"vstimecmph", 0x25D>; 211def : SysReg<"vsatp", 0x280>; 212 213//===----------------------------------------------------------------------===// 214// Machine Information Registers 215//===----------------------------------------------------------------------===// 216 217def : SysReg<"mvendorid", 0xF11>; 218def : SysReg<"marchid", 0xF12>; 219def : SysReg<"mimpid", 0xF13>; 220def : SysReg<"mhartid", 0xF14>; 221def : SysReg<"mconfigptr", 0xF15>; 222 223//===----------------------------------------------------------------------===// 224// Machine Trap Setup 225//===----------------------------------------------------------------------===// 226def : SysReg<"mstatus", 0x300>; 227def : SysReg<"misa", 0x301>; 228def : SysReg<"medeleg", 0x302>; 229def : SysReg<"mideleg", 0x303>; 230def : SysReg<"mie", 0x304>; 231def : SysReg<"mtvec", 0x305>; 232def : SysReg<"mcounteren", 0x306>; 233let isRV32Only = 1 in 234def : SysReg<"mstatush", 0x310>; 235 236//===----------------------------------------------------------------------===// 237// Machine Trap Handling 238//===----------------------------------------------------------------------===// 239def : SysReg<"mscratch", 0x340>; 240def : SysReg<"mepc", 0x341>; 241def : SysReg<"mcause", 0x342>; 242def : SysReg<"mtval", 0x343>; 243let isDeprecatedName = 1 in 244def : SysReg<"mbadaddr", 0x343>; 245def : SysReg<"mip", 0x344>; 246def : SysReg<"mtinst", 0x34A>; 247def : SysReg<"mtval2", 0x34B>; 248 249//===----------------------------------------------------------------------===// 250// Machine Configuration 251//===----------------------------------------------------------------------===// 252 253def : SysReg<"menvcfg", 0x30A>; 254let isRV32Only = 1 in 255def : SysReg<"menvcfgh", 0x31A>; 256def : SysReg<"mseccfg", 0x747>; 257let isRV32Only = 1 in 258def : SysReg<"mseccfgh", 0x757>; 259 260//===----------------------------------------------------------------------===// 261// Machine Protection and Translation 262//===----------------------------------------------------------------------===// 263 264// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only. 265foreach i = 0...15 in { 266 let isRV32Only = !and(i, 1) in 267 def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>; 268} 269 270// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF. 271foreach i = 0...63 in 272 def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; 273 274//===----------------------------------------------------------------------===// 275// Machine Counter and Timers 276//===----------------------------------------------------------------------===// 277def : SysReg<"mcycle", 0xB00>; 278def : SysReg<"minstret", 0xB02>; 279 280// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F. 281foreach i = 3...31 in 282 def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>; 283 284let isRV32Only = 1 in { 285def: SysReg<"mcycleh", 0xB80>; 286def: SysReg<"minstreth", 0xB82>; 287 288// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F. 289foreach i = 3...31 in 290 def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>; 291} 292 293//===----------------------------------------------------------------------===// 294// Machine Counter Setup 295//===----------------------------------------------------------------------===// 296def : SysReg<"mcountinhibit", 0x320>; 297let isAltName = 1 in 298def : SysReg<"mucounteren", 0x320>; 299 300// mhpmevent3-mhpmevent31 at 0x323-0x33F. 301foreach i = 3...31 in 302 def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>; 303 304// mhpmevent3h-mhpmevent31h at 0x723-0x73F 305foreach i = 3...31 in { 306 let isRV32Only = 1 in 307 def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>; 308} 309 310//===----------------------------------------------------------------------===// 311// Supervisor Counter Setup 312//===----------------------------------------------------------------------===// 313def : SysReg<"scountinhibit", 0x120>; 314 315//===----------------------------------------------------------------------===// 316// Debug/ Trace Registers (shared with Debug Mode) 317//===----------------------------------------------------------------------===// 318def : SysReg<"tselect", 0x7A0>; 319def : SysReg<"tdata1", 0x7A1>; 320def : SysReg<"tdata2", 0x7A2>; 321def : SysReg<"tdata3", 0x7A3>; 322def : SysReg<"tinfo", 0x7A4>; 323def : SysReg<"tcontrol", 0x7A5>; 324def : SysReg<"mcontext", 0x7A8>; 325def : SysReg<"mscontext", 0x7AA>; 326 327//===----------------------------------------------------------------------===// 328// Debug Mode Registers 329//===----------------------------------------------------------------------===// 330def : SysReg<"dcsr", 0x7B0>; 331def : SysReg<"dpc", 0x7B1>; 332 333// "dscratch" is an alternative name for "dscratch0" which appeared in earlier 334// drafts of the RISC-V debug spec 335def : SysReg<"dscratch0", 0x7B2>; 336let isAltName = 1 in 337def : SysReg<"dscratch", 0x7B2>; 338def : SysReg<"dscratch1", 0x7B3>; 339 340//===----------------------------------------------------------------------===// 341// User Vector CSRs 342//===----------------------------------------------------------------------===// 343def : SysReg<"vstart", 0x008>; 344def : SysReg<"vxsat", 0x009>; 345def SysRegVXRM : SysReg<"vxrm", 0x00A>; 346def : SysReg<"vcsr", 0x00F>; 347def SysRegVL : SysReg<"vl", 0xC20>; 348def : SysReg<"vtype", 0xC21>; 349def SysRegVLENB: SysReg<"vlenb", 0xC22>; 350 351//===----------------------------------------------------------------------===// 352// Shadow Stack CSR 353//===----------------------------------------------------------------------===// 354def : SysReg<"ssp", 0x011>; 355 356//===----------------------------------------------------------------------===// 357// State Enable Extension (Smstateen) 358//===----------------------------------------------------------------------===// 359 360// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F, 361// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F, 362// and hstateen0h-hstateen3h at 0x61C-0x61F. 363foreach i = 0...3 in { 364 def : SysReg<"sstateen"#i, !add(0x10C, i)>; 365 def : SysReg<"mstateen"#i, !add(0x30C, i)>; 366 let isRV32Only = 1 in 367 def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>; 368 def : SysReg<"hstateen"#i, !add(0x60C, i)>; 369 let isRV32Only = 1 in 370 def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>; 371} 372 373//===----------------------------------------------- 374// Entropy Source CSR 375//===----------------------------------------------- 376 377def SEED : SysReg<"seed", 0x015>; 378 379//===----------------------------------------------- 380// Advanced Interrupt Architecture 381//===----------------------------------------------- 382 383// Machine-level CSRs 384def : SysReg<"miselect", 0x350>; 385def : SysReg<"mireg", 0x351>; 386foreach i = 2...3 in { 387 def : SysReg<"mireg"#i, !add(0x350, i)>; 388} 389foreach i = 4...6 in { 390 def : SysReg<"mireg"#i, !add(0x351, i)>; 391} 392def : SysReg<"mtopei", 0x35C>; 393def : SysReg<"mtopi", 0xFB0>; 394def : SysReg<"mvien", 0x308>; 395def : SysReg<"mvip", 0x309>; 396let isRV32Only = 1 in { 397def : SysReg<"midelegh", 0x313>; 398def : SysReg<"mieh", 0x314>; 399def : SysReg<"mvienh", 0x318>; 400def : SysReg<"mviph", 0x319>; 401def : SysReg<"miph", 0x354>; 402} // isRV32Only 403 404// Supervisor-level CSRs 405def : SysReg<"siselect", 0x150>; 406def : SysReg<"sireg", 0x151>; 407foreach i = 2...3 in { 408 def : SysReg<"sireg"#i, !add(0x150, i)>; 409} 410foreach i = 4...6 in { 411 def : SysReg<"sireg"#i, !add(0x151, i)>; 412} 413def : SysReg<"stopei", 0x15C>; 414def : SysReg<"stopi", 0xDB0>; 415let isRV32Only = 1 in { 416def : SysReg<"sieh", 0x114>; 417def : SysReg<"siph", 0x154>; 418} // isRV32Only 419 420// Hypervisor and VS CSRs 421def : SysReg<"hvien", 0x608>; 422def : SysReg<"hvictl", 0x609>; 423def : SysReg<"hviprio1", 0x646>; 424def : SysReg<"hviprio2", 0x647>; 425def : SysReg<"vsiselect", 0x250>; 426def : SysReg<"vsireg", 0x251>; 427foreach i = 2...3 in { 428 def : SysReg<"vsireg"#i, !add(0x250, i)>; 429} 430foreach i = 4...6 in { 431 def : SysReg<"vsireg"#i, !add(0x251, i)>; 432} 433def : SysReg<"vstopei", 0x25C>; 434def : SysReg<"vstopi", 0xEB0>; 435let isRV32Only = 1 in { 436def : SysReg<"hidelegh", 0x613>; 437def : SysReg<"hvienh", 0x618>; 438def : SysReg<"hviph", 0x655>; 439def : SysReg<"hviprio1h", 0x656>; 440def : SysReg<"hviprio2h", 0x657>; 441def : SysReg<"vsieh", 0x214>; 442def : SysReg<"vsiph", 0x254>; 443} // isRV32Only 444 445//===----------------------------------------------- 446// Jump Vector Table CSR 447//===----------------------------------------------- 448 449def : SysReg<"jvt", 0x017>; 450 451//===----------------------------------------------- 452// Resumable Non-Maskable Interrupts(Smrnmi) CSRs 453//===----------------------------------------------- 454def : SysReg<"mnscratch", 0x740>; 455def : SysReg<"mnepc", 0x741>; 456def : SysReg<"mncause", 0x742>; 457def : SysReg<"mnstatus", 0x744>; 458 459//===----------------------------------------------- 460// Control Transfer Records CSRs 461//===----------------------------------------------- 462def : SysReg<"sctrctl", 0x14e>; 463def : SysReg<"sctrstatus", 0x14f>; 464def : SysReg<"sctrdepth", 0x15f>; 465def : SysReg<"vsctrctl", 0x24e>; 466def : SysReg<"mctrctl", 0x34e>; 467