1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone enum definitions for the RISC-V target 10 // useful for the compiler back-end and the MC libraries. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVBaseInfo.h" 15 #include "llvm/MC/MCInst.h" 16 #include "llvm/MC/MCRegisterInfo.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/Support/raw_ostream.h" 19 #include "llvm/TargetParser/TargetParser.h" 20 #include "llvm/TargetParser/Triple.h" 21 22 namespace llvm { 23 24 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]; 25 26 namespace RISCVSysReg { 27 #define GET_SysRegsList_IMPL 28 #include "RISCVGenSearchableTables.inc" 29 } // namespace RISCVSysReg 30 31 namespace RISCVInsnOpcode { 32 #define GET_RISCVOpcodesList_IMPL 33 #include "RISCVGenSearchableTables.inc" 34 } // namespace RISCVInsnOpcode 35 36 namespace RISCVABI { 37 ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, 38 StringRef ABIName) { 39 auto TargetABI = getTargetABI(ABIName); 40 bool IsRV64 = TT.isArch64Bit(); 41 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE]; 42 43 if (!ABIName.empty() && TargetABI == ABI_Unknown) { 44 errs() 45 << "'" << ABIName 46 << "' is not a recognized ABI for this target (ignoring target-abi)\n"; 47 } else if (ABIName.starts_with("ilp32") && IsRV64) { 48 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " 49 "target-abi)\n"; 50 TargetABI = ABI_Unknown; 51 } else if (ABIName.starts_with("lp64") && !IsRV64) { 52 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " 53 "target-abi)\n"; 54 TargetABI = ABI_Unknown; 55 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E && 56 TargetABI != ABI_Unknown) { 57 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 58 errs() 59 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; 60 TargetABI = ABI_Unknown; 61 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E && 62 TargetABI != ABI_Unknown) { 63 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser 64 errs() 65 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n"; 66 TargetABI = ABI_Unknown; 67 } 68 69 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E || 70 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && 71 FeatureBits[RISCV::FeatureStdExtD]) 72 report_fatal_error("ILP32E cannot be used with the D ISA extension"); 73 74 if (TargetABI != ABI_Unknown) 75 return TargetABI; 76 77 // If no explicit ABI is given, try to compute the default ABI. 78 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); 79 if (!ISAInfo) 80 report_fatal_error(ISAInfo.takeError()); 81 return getTargetABI((*ISAInfo)->computeDefaultABI()); 82 } 83 84 ABI getTargetABI(StringRef ABIName) { 85 auto TargetABI = StringSwitch<ABI>(ABIName) 86 .Case("ilp32", ABI_ILP32) 87 .Case("ilp32f", ABI_ILP32F) 88 .Case("ilp32d", ABI_ILP32D) 89 .Case("ilp32e", ABI_ILP32E) 90 .Case("lp64", ABI_LP64) 91 .Case("lp64f", ABI_LP64F) 92 .Case("lp64d", ABI_LP64D) 93 .Case("lp64e", ABI_LP64E) 94 .Default(ABI_Unknown); 95 return TargetABI; 96 } 97 98 // To avoid the BP value clobbered by a function call, we need to choose a 99 // callee saved register to save the value. RV32E only has X8 and X9 as callee 100 // saved registers and X8 will be used as fp. So we choose X9 as bp. 101 MCRegister getBPReg() { return RISCV::X9; } 102 103 // Returns the register holding shadow call stack pointer. 104 MCRegister getSCSPReg() { return RISCV::X3; } 105 106 } // namespace RISCVABI 107 108 namespace RISCVFeatures { 109 110 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { 111 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) 112 report_fatal_error("RV64 target requires an RV64 CPU"); 113 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) 114 report_fatal_error("RV32 target requires an RV32 CPU"); 115 if (FeatureBits[RISCV::Feature32Bit] && 116 FeatureBits[RISCV::Feature64Bit]) 117 report_fatal_error("RV32 and RV64 can't be combined"); 118 } 119 120 llvm::Expected<std::unique_ptr<RISCVISAInfo>> 121 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { 122 unsigned XLen = IsRV64 ? 64 : 32; 123 std::vector<std::string> FeatureVector; 124 // Convert FeatureBitset to FeatureVector. 125 for (auto Feature : RISCVFeatureKV) { 126 if (FeatureBits[Feature.Value] && 127 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) 128 FeatureVector.push_back(std::string("+") + Feature.Key); 129 } 130 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector); 131 } 132 133 } // namespace RISCVFeatures 134 135 // Include the auto-generated portion of the compress emitter. 136 #define GEN_UNCOMPRESS_INSTR 137 #define GEN_COMPRESS_INSTR 138 #include "RISCVGenCompressInstEmitter.inc" 139 140 bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI, 141 const MCSubtargetInfo &STI) { 142 return compressInst(OutInst, MI, STI); 143 } 144 145 bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI, 146 const MCSubtargetInfo &STI) { 147 return uncompressInst(OutInst, MI, STI); 148 } 149 150 // Lookup table for fli.s for entries 2-31. 151 static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = { 152 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00}, 153 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00}, 154 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10}, 155 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01}, 156 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00}, 157 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11}, 158 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10}, 159 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00}, 160 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00}, 161 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10}, 162 }; 163 164 int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) { 165 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() || 166 &FPImm.getSemantics() == &APFloat::IEEEdouble() || 167 &FPImm.getSemantics() == &APFloat::IEEEhalf()) && 168 "Unexpected semantics"); 169 170 // Handle the minimum normalized value which is different for each type. 171 if (FPImm.isSmallestNormalized() && !FPImm.isNegative()) 172 return 1; 173 174 // Convert to single precision to use its lookup table. 175 bool LosesInfo; 176 APFloat::opStatus Status = FPImm.convert( 177 APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &LosesInfo); 178 if (Status != APFloat::opOK || LosesInfo) 179 return -1; 180 181 APInt Imm = FPImm.bitcastToAPInt(); 182 183 if (Imm.extractBitsAsZExtValue(21, 0) != 0) 184 return -1; 185 186 bool Sign = Imm.extractBitsAsZExtValue(1, 31); 187 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21); 188 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23); 189 190 auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa)); 191 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp || 192 EMI->second != Mantissa) 193 return -1; 194 195 // Table doesn't have entry 0 or 1. 196 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2; 197 198 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16. 199 if (Sign) { 200 if (Entry == 16) 201 return 0; 202 return -1; 203 } 204 205 return Entry; 206 } 207 208 float RISCVLoadFPImm::getFPImm(unsigned Imm) { 209 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate"); 210 211 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0. 212 uint32_t Sign = 0; 213 if (Imm == 0) { 214 Sign = 0b1; 215 Imm = 16; 216 } 217 218 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first; 219 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second; 220 221 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21; 222 return bit_cast<float>(I); 223 } 224 225 void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) { 226 OS << "{ra"; 227 if (SlistEncode > 4) { 228 OS << ", s0"; 229 if (SlistEncode == 15) 230 OS << "-s11"; 231 else if (SlistEncode > 5 && SlistEncode <= 14) 232 OS << "-s" << (SlistEncode - 5); 233 } 234 OS << "}"; 235 } 236 237 } // namespace llvm 238