1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwr11: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR11", "">; 56def DirectivePwrFuture 57 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 58 59// Specifies that the selected CPU supports 64-bit instructions, regardless of 60// whether we are in 32-bit or 64-bit mode. 61def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 62 "Enable 64-bit instructions">; 63def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 64def FeatureModernAIXAs 65 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 66 "AIX system assembler is modern enough to support new mnes">; 67def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 68 "Enable floating-point instructions">; 69 70// Specifies that we are in 64-bit mode or that we should use 64-bit registers 71// in 32-bit mode when possible. Requires Feature64Bit to be enabled. 72def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 73 "Enable 64-bit registers usage for ppc32 [beta]">; 74 75// Specify if we should store and manipulate i1 values in the individual 76// condition register bits. 77def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 78 "Use condition-register bits individually">; 79def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 80 "Enable classic FPU instructions", 81 [FeatureHardFloat]>; 82def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 83 "Enable Altivec instructions", 84 [FeatureFPU]>; 85def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 86 "Enable SPE instructions", 87 [FeatureHardFloat]>; 88def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 89 "Enable Embedded Floating-Point APU 2 instructions", 90 [FeatureSPE]>; 91def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 92 "Enable the MFOCRF instruction">; 93def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 94 "Enable the fsqrt instruction", 95 [FeatureFPU]>; 96def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 97 "Enable the fcpsgn instruction", 98 [FeatureFPU]>; 99def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 100 "Enable the fre instruction", 101 [FeatureFPU]>; 102def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 103 "Enable the fres instruction", 104 [FeatureFPU]>; 105def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 106 "Enable the frsqrte instruction", 107 [FeatureFPU]>; 108def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 109 "Enable the frsqrtes instruction", 110 [FeatureFPU]>; 111def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 112 "Assume higher precision reciprocal estimates">; 113def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 114 "Enable the stfiwx instruction", 115 [FeatureFPU]>; 116def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 117 "Enable the lfiwax instruction", 118 [FeatureFPU]>; 119def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 120 "Enable the fri[mnpz] instructions", 121 [FeatureFPU]>; 122def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 123 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 124 [FeatureFPU]>; 125def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 126 "Enable the isel instruction">; 127def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 128 "Enable the bpermd instruction">; 129def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 130 "Enable extended divide instructions">; 131def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 132 "Enable the ldbrx instruction">; 133def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 134 "Enable the cmpb instruction">; 135def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 136 "Enable icbt instruction">; 137def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 138 "Enable Book E instructions", 139 [FeatureICBT]>; 140def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 141 "Has only the msync instruction instead of sync", 142 [FeatureBookE]>; 143def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 144 "Enable E500/E500mc instructions">; 145def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true", 146 "Enable secure plt mode">; 147def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 148 "Enable PPC 4xx instructions">; 149def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 150 "Enable PPC 6xx instructions">; 151def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 152 "Enable VSX instructions", 153 [FeatureAltivec]>; 154def FeatureTwoConstNR : 155 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 156 "Requires two constant Newton-Raphson computation">; 157def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 158 "Enable POWER8 Altivec instructions", 159 [FeatureAltivec]>; 160def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 161 "Enable POWER8 Crypto instructions", 162 [FeatureP8Altivec]>; 163def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 164 "Enable POWER8 vector instructions", 165 [FeatureVSX, FeatureP8Altivec]>; 166def FeatureDirectMove : 167 SubtargetFeature<"direct-move", "HasDirectMove", "true", 168 "Enable Power8 direct move instructions", 169 [FeatureVSX]>; 170def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 171 "HasPartwordAtomics", "true", 172 "Enable l[bh]arx and st[bh]cx.">; 173def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics", 174 "HasQuadwordAtomics", "true", 175 "Enable lqarx and stqcx.">; 176def FeatureInvariantFunctionDescriptors : 177 SubtargetFeature<"invariant-function-descriptors", 178 "HasInvariantFunctionDescriptors", "true", 179 "Assume function descriptors are invariant">; 180def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 181 "Always use indirect calls">; 182def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 183 "Enable Hardware Transactional Memory instructions">; 184def FeatureMFTB : SubtargetFeature<"", "IsFeatureMFTB", "true", 185 "Implement mftb using the mfspr instruction">; 186def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 187 "Target supports instruction fusion">; 188def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 189 "HasAddiLoadFusion", "true", 190 "Power8 Addi-Load fusion", 191 [FeatureFusion]>; 192def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 193 "HasAddisLoadFusion", "true", 194 "Power8 Addis-Load fusion", 195 [FeatureFusion]>; 196def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 197 "Target supports store clustering", 198 [FeatureFusion]>; 199def FeatureArithAddFusion : 200 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true", 201 "Target supports Arithmetic Operations with Add fusion", 202 [FeatureFusion]>; 203def FeatureAddLogicalFusion : 204 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true", 205 "Target supports Add with Logical Operations fusion", 206 [FeatureFusion]>; 207def FeatureLogicalAddFusion : 208 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true", 209 "Target supports Logical with Add Operations fusion", 210 [FeatureFusion]>; 211def FeatureLogicalFusion : 212 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true", 213 "Target supports Logical Operations fusion", 214 [FeatureFusion]>; 215def FeatureSha3Fusion : 216 SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true", 217 "Target supports SHA3 assist fusion", 218 [FeatureFusion]>; 219def FeatureCompareFusion: 220 SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true", 221 "Target supports Comparison Operations fusion", 222 [FeatureFusion]>; 223def FeatureWideImmFusion: 224 SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true", 225 "Target supports Wide-Immediate fusion", 226 [FeatureFusion]>; 227def FeatureZeroMoveFusion: 228 SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true", 229 "Target supports move to SPR with branch fusion", 230 [FeatureFusion]>; 231def FeatureBack2BackFusion: 232 SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true", 233 "Target supports general back to back fusion", 234 [FeatureFusion]>; 235def FeatureUnalignedFloats : 236 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 237 "true", "CPU does not trap on unaligned FP access">; 238def FeaturePPCPreRASched: 239 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 240 "Use PowerPC pre-RA scheduling strategy">; 241def FeaturePPCPostRASched: 242 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 243 "Use PowerPC post-RA scheduling strategy">; 244def FeatureFloat128 : 245 SubtargetFeature<"float128", "HasFloat128", "true", 246 "Enable the __float128 data type for IEEE-754R Binary128.", 247 [FeatureVSX]>; 248def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 249 "POPCNTD_Fast", 250 "Enable the popcnt[dw] instructions">; 251// Note that for the a2 processor models we should not use popcnt[dw] by 252// default. These processors do support the instructions, but they're 253// microcoded, and the software emulation is about twice as fast. 254def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 255 "POPCNTD_Slow", 256 "Has slow popcnt[dw] instructions">; 257 258def DeprecatedDST : SubtargetFeature<"", "IsDeprecatedDST", "true", 259 "Treat vector data stream cache control instructions as deprecated">; 260 261def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06", 262 "true", 263 "Enable instructions in ISA 2.06.">; 264def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", 265 "true", 266 "Enable instructions in ISA 2.07.">; 267def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 268 "true", 269 "Enable instructions in ISA 3.0.", 270 [FeatureISA2_07]>; 271def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 272 "true", 273 "Enable instructions in ISA 3.1.", 274 [FeatureISA3_0]>; 275def FeatureISAFuture : SubtargetFeature<"isa-future-instructions", 276 "IsISAFuture", "true", 277 "Enable instructions for Future ISA.", 278 [FeatureISA3_1]>; 279def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 280 "Enable POWER9 Altivec instructions", 281 [FeatureISA3_0, FeatureP8Altivec]>; 282def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 283 "Enable POWER9 vector instructions", 284 [FeatureISA3_0, FeatureP8Vector, 285 FeatureP9Altivec]>; 286def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 287 "true", 288 "Enable POWER10 vector instructions", 289 [FeatureISA3_1, FeatureP9Vector]>; 290// A separate feature for this even though it is equivalent to P9Vector 291// because this is a feature of the implementation rather than the architecture 292// and may go away with future CPU's. 293def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 294 "VectorsUseTwoUnits", 295 "true", 296 "Vectors use two units">; 297def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 298 "true", 299 "Enable prefixed instructions", 300 [FeatureISA3_1]>; 301def FeaturePCRelativeMemops : 302 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 303 "Enable PC relative Memory Ops", 304 [FeatureISA3_0, FeaturePrefixInstrs]>; 305def FeaturePairedVectorMemops: 306 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 307 "32Byte load and store instructions", 308 [FeatureISA3_0]>; 309def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 310 "Enable MMA instructions", 311 [FeatureP8Vector, FeatureP9Altivec, 312 FeaturePairedVectorMemops]>; 313def FeatureROPProtect : 314 SubtargetFeature<"rop-protect", "HasROPProtect", "true", 315 "Add ROP protect">; 316 317def FeaturePrivileged : 318 SubtargetFeature<"privileged", "HasPrivileged", "true", 319 "Add privileged instructions">; 320 321// Specifies that local-exec TLS accesses in any function with this target 322// attribute should use the optimized TOC-free sequence (where the offset is an 323// immediate off of R13 for which the linker might add fix-up code if the 324// immediate is too large). 325// Clearly, this isn't really a feature of the subtarget, but is used as a 326// convenient way to affect code generation for individual functions. 327def FeatureAIXLocalExecTLS : 328 SubtargetFeature<"aix-small-local-exec-tls", "HasAIXSmallLocalExecTLS", "true", 329 "Produce a TOC-free local-exec TLS sequence for this function " 330 "for 64-bit AIX">; 331 332// Specifies that local-dynamic TLS accesses in any function with this target 333// attribute should use the optimized sequence (where the offset is an immediate 334// off the module-handle for which the linker might add fix-up code for if the 335// immediate is too large). 336def FeatureAIXLocalDynamicTLS : 337 SubtargetFeature<"aix-small-local-dynamic-tls", "HasAIXSmallLocalDynamicTLS", 338 "true", "Produce a faster local-dynamic TLS sequence for this " 339 "function for 64-bit AIX">; 340 341def FeatureAIXSharedLibTLSModelOpt : 342 SubtargetFeature<"aix-shared-lib-tls-model-opt", 343 "HasAIXShLibTLSModelOpt", "true", 344 "Tune TLS model at function level in shared library loaded " 345 "with the main program (for 64-bit AIX only)">; 346 347def FeaturePredictableSelectIsExpensive : 348 SubtargetFeature<"predictable-select-expensive", 349 "PredictableSelectIsExpensive", 350 "true", 351 "Prefer likely predicted branches over selects">; 352 353def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true", 354 "MFLR is a fast instruction">; 355 356// Since new processors generally contain a superset of features of those that 357// came before them, the idea is to make implementations of new processors 358// less error prone and easier to read. 359// Namely: 360// list<SubtargetFeature> P8InheritableFeatures = ... 361// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 362// [ features that Power8 does not support but inheritable ] 363// list<SubtargetFeature> FutureProcessorSpecificFeatures = 364// [ features that Power8 does not support and not inheritable ] 365// list<SubtargetFeature> FutureProcessorInheritableFeatures = 366// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 367// list<SubtargetFeature> FutureProcessorFeatures = 368// !listconcat(FutureProcessorInheritableFeatures, 369// FutureProcessorSpecificFeatures) 370 371// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 372// well as providing a single point of definition if the feature set will be 373// used elsewhere. 374def ProcessorFeatures { 375 // Power7 376 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 377 FeatureAltivec, 378 FeatureVSX, 379 FeatureMFOCRF, 380 FeatureFCPSGN, 381 FeatureFSqrt, 382 FeatureFRE, 383 FeatureFRES, 384 FeatureFRSQRTE, 385 FeatureFRSQRTES, 386 FeatureRecipPrec, 387 FeatureSTFIWX, 388 FeatureLFIWAX, 389 FeatureFPRND, 390 FeatureFPCVT, 391 FeatureISEL, 392 FeaturePOPCNTD, 393 FeatureCMPB, 394 FeatureLDBRX, 395 Feature64Bit, 396 /* Feature64BitRegs, */ 397 FeatureBPERMD, 398 FeatureExtDiv, 399 FeatureMFTB, 400 DeprecatedDST, 401 FeatureTwoConstNR, 402 FeatureUnalignedFloats, 403 FeatureISA2_06]; 404 list<SubtargetFeature> P7SpecificFeatures = []; 405 list<SubtargetFeature> P7Features = 406 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 407 408 // Power8 409 list<SubtargetFeature> P8AdditionalFeatures = 410 [DirectivePwr8, 411 FeatureP8Altivec, 412 FeatureP8Vector, 413 FeatureP8Crypto, 414 FeatureHTM, 415 FeatureDirectMove, 416 FeatureICBT, 417 FeaturePartwordAtomic, 418 FeatureQuadwordAtomic, 419 FeaturePredictableSelectIsExpensive, 420 FeatureISA2_07, 421 FeatureCRBits 422 ]; 423 424 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 425 FeatureAddisLoadFusion]; 426 list<SubtargetFeature> P8InheritableFeatures = 427 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 428 list<SubtargetFeature> P8Features = 429 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 430 431 // Power9 432 list<SubtargetFeature> P9AdditionalFeatures = 433 [DirectivePwr9, 434 FeatureP9Altivec, 435 FeatureP9Vector, 436 FeaturePPCPreRASched, 437 FeaturePPCPostRASched, 438 FeatureISA3_0, 439 FeaturePredictableSelectIsExpensive 440 ]; 441 442 // Some features are unique to Power9 and there is no reason to assume 443 // they will be part of any future CPUs. One example is the narrower 444 // dispatch for vector operations than scalar ones. For the time being, 445 // this list also includes scheduling-related features since we do not have 446 // enough info to create custom scheduling strategies for future CPUs. 447 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 448 list<SubtargetFeature> P9InheritableFeatures = 449 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 450 list<SubtargetFeature> P9Features = 451 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 452 453 // Power10 454 // For P10 CPU we assume that all of the existing features from Power9 455 // still exist with the exception of those we know are Power9 specific. 456 list<SubtargetFeature> FusionFeatures = [ 457 FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion, 458 FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion, 459 ]; 460 list<SubtargetFeature> P10AdditionalFeatures = 461 !listconcat(FusionFeatures, [ 462 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 463 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 464 FeaturePairedVectorMemops, FeatureFastMFLR]); 465 list<SubtargetFeature> P10SpecificFeatures = []; 466 list<SubtargetFeature> P10InheritableFeatures = 467 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 468 list<SubtargetFeature> P10Features = 469 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 470 471 // Power11 472 // For P11 CPU we assume that all the existing features from Power10 473 // still exist with the exception of those we know are Power10 specific. 474 list<SubtargetFeature> P11AdditionalFeatures = 475 [DirectivePwr11]; 476 list<SubtargetFeature> P11SpecificFeatures = 477 []; 478 list<SubtargetFeature> P11InheritableFeatures = 479 !listconcat(P10InheritableFeatures, P11AdditionalFeatures); 480 list<SubtargetFeature> P11Features = 481 !listconcat(P11InheritableFeatures, P11SpecificFeatures); 482 483 // Future 484 // For future CPU we assume that all of the existing features from Power11 485 // still exist with the exception of those we know are Power11 specific. 486 list<SubtargetFeature> FutureAdditionalFeatures = [FeatureISAFuture]; 487 list<SubtargetFeature> FutureSpecificFeatures = []; 488 list<SubtargetFeature> FutureInheritableFeatures = 489 !listconcat(P11InheritableFeatures, FutureAdditionalFeatures); 490 list<SubtargetFeature> FutureFeatures = 491 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 492} 493 494// Note: Future features to add when support is extended to more 495// recent ISA levels: 496// 497// DFP p6, p6x, p7 decimal floating-point instructions 498// POPCNTB p5 through p7 popcntb and related instructions 499 500//===----------------------------------------------------------------------===// 501// Classes used for relation maps. 502//===----------------------------------------------------------------------===// 503// RecFormRel - Filter class used to relate non-record-form instructions with 504// their record-form variants. 505class RecFormRel; 506 507// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 508// FMA instruction forms with their corresponding factor-killing forms. 509class AltVSXFMARel { 510 bit IsVSXFMAAlt = 0; 511} 512 513//===----------------------------------------------------------------------===// 514// Relation Map Definitions. 515//===----------------------------------------------------------------------===// 516 517def getRecordFormOpcode : InstrMapping { 518 let FilterClass = "RecFormRel"; 519 // Instructions with the same BaseName and Interpretation64Bit values 520 // form a row. 521 let RowFields = ["BaseName", "Interpretation64Bit"]; 522 // Instructions with the same RC value form a column. 523 let ColFields = ["RC"]; 524 // The key column are the non-record-form instructions. 525 let KeyCol = ["0"]; 526 // Value columns RC=1 527 let ValueCols = [["1"]]; 528} 529 530def getNonRecordFormOpcode : InstrMapping { 531 let FilterClass = "RecFormRel"; 532 // Instructions with the same BaseName and Interpretation64Bit values 533 // form a row. 534 let RowFields = ["BaseName", "Interpretation64Bit"]; 535 // Instructions with the same RC value form a column. 536 let ColFields = ["RC"]; 537 // The key column are the record-form instructions. 538 let KeyCol = ["1"]; 539 // Value columns are RC=0 540 let ValueCols = [["0"]]; 541} 542 543def getAltVSXFMAOpcode : InstrMapping { 544 let FilterClass = "AltVSXFMARel"; 545 // Instructions with the same BaseName value form a row. 546 let RowFields = ["BaseName"]; 547 // Instructions with the same IsVSXFMAAlt value form a column. 548 let ColFields = ["IsVSXFMAAlt"]; 549 // The key column are the (default) addend-killing instructions. 550 let KeyCol = ["0"]; 551 // Value columns IsVSXFMAAlt=1 552 let ValueCols = [["1"]]; 553} 554 555def get64BitInstrFromSignedExt32BitInstr : InstrMapping { 556 let FilterClass = "SExt32To64"; 557 // Instructions with the same opcode. 558 let RowFields = ["Inst"]; 559 // Instructions with the same Interpretation64Bit value form a column. 560 let ColFields = ["Interpretation64Bit"]; 561 // The key column are not the Interpretation64Bit-form instructions. 562 let KeyCol = ["0"]; 563 // Value columns are the Interpretation64Bit-form instructions. 564 let ValueCols = [["1"]]; 565} 566 567//===----------------------------------------------------------------------===// 568// Register File Description 569//===----------------------------------------------------------------------===// 570 571include "PPCRegisterInfo.td" 572include "PPCSchedule.td" 573include "GISel/PPCRegisterBanks.td" 574 575//===----------------------------------------------------------------------===// 576// PowerPC processors supported. 577// 578 579def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 580 FeatureMFTB]>; 581def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 582 FeatureFRES, FeatureFRSQRTE, 583 FeatureICBT, FeatureBookE, 584 FeatureMSYNC, FeatureMFTB]>; 585def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 586 FeatureFRES, FeatureFRSQRTE, 587 FeatureICBT, FeatureBookE, 588 FeatureMSYNC, FeatureMFTB]>; 589def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 590def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 591 FeatureMFTB]>; 592def : Processor<"603", G3Itineraries, [Directive603, 593 FeatureFRES, FeatureFRSQRTE, 594 FeatureMFTB]>; 595def : Processor<"603e", G3Itineraries, [Directive603, 596 FeatureFRES, FeatureFRSQRTE, 597 FeatureMFTB]>; 598def : Processor<"603ev", G3Itineraries, [Directive603, 599 FeatureFRES, FeatureFRSQRTE, 600 FeatureMFTB]>; 601def : Processor<"604", G3Itineraries, [Directive604, 602 FeatureFRES, FeatureFRSQRTE, 603 FeatureMFTB]>; 604def : Processor<"604e", G3Itineraries, [Directive604, 605 FeatureFRES, FeatureFRSQRTE, 606 FeatureMFTB]>; 607def : Processor<"620", G3Itineraries, [Directive620, 608 FeatureFRES, FeatureFRSQRTE, 609 FeatureMFTB]>; 610def : Processor<"750", G4Itineraries, [Directive750, 611 FeatureFRES, FeatureFRSQRTE, 612 FeatureMFTB]>; 613def : Processor<"g3", G3Itineraries, [Directive750, 614 FeatureFRES, FeatureFRSQRTE, 615 FeatureMFTB]>; 616def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 617 FeatureFRES, FeatureFRSQRTE, 618 FeatureMFTB]>; 619def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 620 FeatureFRES, FeatureFRSQRTE, 621 FeatureMFTB]>; 622def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 623 FeatureFRES, FeatureFRSQRTE, 624 FeatureMFTB]>; 625def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 626 FeatureFRES, FeatureFRSQRTE, 627 FeatureMFTB]>; 628 629def : ProcessorModel<"970", G5Model, 630 [Directive970, FeatureAltivec, 631 FeatureMFOCRF, FeatureFSqrt, 632 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 633 Feature64Bit /*, Feature64BitRegs */, 634 FeatureMFTB]>; 635def : ProcessorModel<"g5", G5Model, 636 [Directive970, FeatureAltivec, 637 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 638 FeatureFRES, FeatureFRSQRTE, 639 Feature64Bit /*, Feature64BitRegs */, 640 FeatureMFTB, DeprecatedDST]>; 641def : ProcessorModel<"e500", PPCE500Model, 642 [DirectiveE500, 643 FeatureICBT, FeatureBookE, 644 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 645def : ProcessorModel<"e500mc", PPCE500mcModel, 646 [DirectiveE500mc, 647 FeatureSTFIWX, FeatureICBT, FeatureBookE, 648 FeatureISEL, FeatureMFTB]>; 649def : ProcessorModel<"e5500", PPCE5500Model, 650 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 651 FeatureSTFIWX, FeatureICBT, FeatureBookE, 652 FeatureISEL, FeatureMFTB]>; 653def : ProcessorModel<"a2", PPCA2Model, 654 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 655 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 656 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 657 FeatureSTFIWX, FeatureLFIWAX, 658 FeatureFPRND, FeatureFPCVT, FeatureISEL, 659 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 660 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB, 661 FeatureISA2_06]>; 662def : ProcessorModel<"pwr3", G5Model, 663 [DirectivePwr3, FeatureAltivec, 664 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 665 FeatureSTFIWX, Feature64Bit]>; 666def : ProcessorModel<"pwr4", G5Model, 667 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 668 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 669 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 670def : ProcessorModel<"pwr5", G5Model, 671 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 672 FeatureFSqrt, FeatureFRE, FeatureFRES, 673 FeatureFRSQRTE, FeatureFRSQRTES, 674 FeatureSTFIWX, Feature64Bit, 675 FeatureMFTB, DeprecatedDST]>; 676def : ProcessorModel<"pwr5x", G5Model, 677 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 678 FeatureFSqrt, FeatureFRE, FeatureFRES, 679 FeatureFRSQRTE, FeatureFRSQRTES, 680 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 681 FeatureMFTB, DeprecatedDST]>; 682def : ProcessorModel<"pwr6", G5Model, 683 [DirectivePwr6, FeatureAltivec, 684 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 685 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 686 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 687 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 688 FeatureMFTB, DeprecatedDST]>; 689def : ProcessorModel<"pwr6x", G5Model, 690 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 691 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 692 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 693 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 694 FeatureFPRND, Feature64Bit, 695 FeatureMFTB, DeprecatedDST]>; 696def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 697def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 698def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 699def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>; 700def : ProcessorModel<"pwr11", P10Model, ProcessorFeatures.P11Features>; 701// No scheduler model for future CPU. 702def : ProcessorModel<"future", NoSchedModel, 703 ProcessorFeatures.FutureFeatures>; 704def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 705 FeatureMFTB]>; 706def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 707 FeatureMFTB]>; 708def : ProcessorModel<"ppc64", G5Model, 709 [Directive64, FeatureAltivec, 710 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 711 FeatureFRSQRTE, FeatureSTFIWX, 712 Feature64Bit /*, Feature64BitRegs */, 713 FeatureMFTB]>; 714def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 715 716//===----------------------------------------------------------------------===// 717// Calling Conventions 718//===----------------------------------------------------------------------===// 719 720include "PPCCallingConv.td" 721 722def PPCInstrInfo : InstrInfo { 723 let isLittleEndianEncoding = 1; 724} 725 726def PPCAsmWriter : AsmWriter { 727 string AsmWriterClassName = "InstPrinter"; 728 int PassSubtarget = 1; 729 int Variant = 0; 730 bit isMCAsmWriter = 1; 731} 732 733def PPCAsmParser : AsmParser { 734 let ShouldEmitMatchRegisterName = 1; 735 let AllowDuplicateRegisterNames = 1; 736} 737 738def PPCAsmParserVariant : AsmParserVariant { 739 int Variant = 0; 740 741 // We do not use hard coded registers in asm strings. However, some 742 // InstAlias definitions use immediate literals. Set RegisterPrefix 743 // so that those are not misinterpreted as registers. 744 string RegisterPrefix = "%"; 745 string BreakCharacters = "."; 746} 747 748def PPC : Target { 749 // Information about the instructions. 750 let InstructionSet = PPCInstrInfo; 751 752 let AssemblyWriters = [PPCAsmWriter]; 753 let AssemblyParsers = [PPCAsmParser]; 754 let AssemblyParserVariants = [PPCAsmParserVariant]; 755 let AllowRegisterRenaming = 1; 756} 757 758//===----------------------------------------------------------------------===// 759// Pfm Counters 760//===----------------------------------------------------------------------===// 761 762include "PPCPfmCounters.td" 763