xref: /llvm-project/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td (revision cbd3f252e3ff2115497c771590f69f1c989b402e) 
1//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Declarations that describe the PTX register file
11//===----------------------------------------------------------------------===//
12
13class NVPTXReg<string n> : Register<n> {
14  let Namespace = "NVPTX";
15}
16
17class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
18     : RegisterClass <"NVPTX", regTypes, alignment, regList>;
19
20//===----------------------------------------------------------------------===//
21//  Registers
22//===----------------------------------------------------------------------===//
23
24// Special Registers used as stack pointer
25def VRFrame32         : NVPTXReg<"%SP">;
26def VRFrame64         : NVPTXReg<"%SP">;
27def VRFrameLocal32    : NVPTXReg<"%SPL">;
28def VRFrameLocal64    : NVPTXReg<"%SPL">;
29
30// Special Registers used as the stack
31def VRDepot  : NVPTXReg<"%Depot">;
32
33// We use virtual registers, but define a few physical registers here to keep
34// SDAG and the MachineInstr layers happy.
35foreach i = 0...4 in {
36  def P#i  : NVPTXReg<"%p"#i>;  // Predicate
37  def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
38  def R#i  : NVPTXReg<"%r"#i>;  // 32-bit
39  def RL#i : NVPTXReg<"%rd"#i>; // 64-bit
40  def RQ#i : NVPTXReg<"%rq"#i>; // 128-bit
41  def H#i  : NVPTXReg<"%h"#i>;  // 16-bit float
42  def HH#i : NVPTXReg<"%hh"#i>; // 2x16-bit float
43  def F#i  : NVPTXReg<"%f"#i>;  // 32-bit float
44  def FL#i : NVPTXReg<"%fd"#i>; // 64-bit float
45
46  // Arguments
47  def ia#i : NVPTXReg<"%ia"#i>;
48  def la#i : NVPTXReg<"%la"#i>;
49  def fa#i : NVPTXReg<"%fa"#i>;
50  def da#i : NVPTXReg<"%da"#i>;
51}
52
53foreach i = 0...31 in {
54  def ENVREG#i : NVPTXReg<"%envreg"#i>;
55}
56
57//===----------------------------------------------------------------------===//
58//  Register classes
59//===----------------------------------------------------------------------===//
60def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;
61def Int16Regs : NVPTXRegClass<[i16, f16, bf16], 16, (add (sequence "RS%u", 0, 4))>;
62def Int32Regs : NVPTXRegClass<[i32, v2f16, v2bf16, v2i16, v4i8], 32,
63                              (add (sequence "R%u", 0, 4),
64                              VRFrame32, VRFrameLocal32)>;
65def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4), VRFrame64, VRFrameLocal64)>;
66// 128-bit regs are not defined as general regs in NVPTX. They are used for inlineASM only.
67def Int128Regs : NVPTXRegClass<[i128], 128, (add (sequence "RQ%u", 0, 4))>;
68def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
69def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>;
70def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>;
71def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>;
72def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>;
73def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>;
74
75// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
76def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame32, VRFrameLocal32, VRDepot,
77                                            (sequence "ENVREG%u", 0, 31))>;
78