1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class prints an Mips MCInst to a .s file. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsInstPrinter.h" 14 #include "Mips.h" 15 #include "llvm/ADT/StringExtras.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrInfo.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/MCSymbol.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/raw_ostream.h" 23 using namespace llvm; 24 25 #define DEBUG_TYPE "asm-printer" 26 27 #define PRINT_ALIAS_INSTR 28 #include "MipsGenAsmWriter.inc" 29 30 template<unsigned R> 31 static bool isReg(const MCInst &MI, unsigned OpNo) { 32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 33 return MI.getOperand(OpNo).getReg() == R; 34 } 35 36 const char* Mips::MipsFCCToString(Mips::CondCode CC) { 37 switch (CC) { 38 case FCOND_F: 39 case FCOND_T: return "f"; 40 case FCOND_UN: 41 case FCOND_OR: return "un"; 42 case FCOND_OEQ: 43 case FCOND_UNE: return "eq"; 44 case FCOND_UEQ: 45 case FCOND_ONE: return "ueq"; 46 case FCOND_OLT: 47 case FCOND_UGE: return "olt"; 48 case FCOND_ULT: 49 case FCOND_OGE: return "ult"; 50 case FCOND_OLE: 51 case FCOND_UGT: return "ole"; 52 case FCOND_ULE: 53 case FCOND_OGT: return "ule"; 54 case FCOND_SF: 55 case FCOND_ST: return "sf"; 56 case FCOND_NGLE: 57 case FCOND_GLE: return "ngle"; 58 case FCOND_SEQ: 59 case FCOND_SNE: return "seq"; 60 case FCOND_NGL: 61 case FCOND_GL: return "ngl"; 62 case FCOND_LT: 63 case FCOND_NLT: return "lt"; 64 case FCOND_NGE: 65 case FCOND_GE: return "nge"; 66 case FCOND_LE: 67 case FCOND_NLE: return "le"; 68 case FCOND_NGT: 69 case FCOND_GT: return "ngt"; 70 } 71 llvm_unreachable("Impossible condition code!"); 72 } 73 74 void MipsInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { 75 markup(OS, Markup::Register) 76 << '$' << StringRef(getRegisterName(Reg)).lower(); 77 } 78 79 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, 80 StringRef Annot, const MCSubtargetInfo &STI, 81 raw_ostream &O) { 82 switch (MI->getOpcode()) { 83 default: 84 break; 85 case Mips::RDHWR: 86 case Mips::RDHWR64: 87 O << "\t.set\tpush\n"; 88 O << "\t.set\tmips32r2\n"; 89 break; 90 case Mips::Save16: 91 O << "\tsave\t"; 92 printSaveRestore(MI, STI, O); 93 O << " # 16 bit inst\n"; 94 return; 95 case Mips::SaveX16: 96 O << "\tsave\t"; 97 printSaveRestore(MI, STI, O); 98 O << "\n"; 99 return; 100 case Mips::Restore16: 101 O << "\trestore\t"; 102 printSaveRestore(MI, STI, O); 103 O << " # 16 bit inst\n"; 104 return; 105 case Mips::RestoreX16: 106 O << "\trestore\t"; 107 printSaveRestore(MI, STI, O); 108 O << "\n"; 109 return; 110 } 111 112 // Try to print any aliases first. 113 if (!printAliasInstr(MI, Address, STI, O) && 114 !printAlias(*MI, Address, STI, O)) 115 printInstruction(MI, Address, STI, O); 116 printAnnotation(O, Annot); 117 118 switch (MI->getOpcode()) { 119 default: 120 break; 121 case Mips::RDHWR: 122 case Mips::RDHWR64: 123 O << "\n\t.set\tpop"; 124 } 125 } 126 127 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 128 const MCSubtargetInfo &STI, raw_ostream &O) { 129 const MCOperand &Op = MI->getOperand(OpNo); 130 if (Op.isReg()) { 131 printRegName(O, Op.getReg()); 132 return; 133 } 134 135 if (Op.isImm()) { 136 markup(O, Markup::Immediate) << formatImm(Op.getImm()); 137 return; 138 } 139 140 assert(Op.isExpr() && "unknown operand kind in printOperand"); 141 Op.getExpr()->print(O, &MAI, true); 142 } 143 144 void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo, 145 const MCSubtargetInfo &STI, 146 raw_ostream &O) { 147 const MCOperand &Op = MI->getOperand(OpNo); 148 if (!Op.isImm()) 149 return printOperand(MI, OpNo, STI, O); 150 151 if (PrintBranchImmAsAddress) 152 markup(O, Markup::Immediate) << formatHex(Op.getImm()); 153 else 154 markup(O, Markup::Immediate) << formatImm(Op.getImm()); 155 } 156 157 void MipsInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, 158 unsigned OpNo, 159 const MCSubtargetInfo &STI, 160 raw_ostream &O) { 161 const MCOperand &Op = MI->getOperand(OpNo); 162 if (!Op.isImm()) 163 return printOperand(MI, OpNo, STI, O); 164 165 if (PrintBranchImmAsAddress) { 166 uint64_t Target = Address + Op.getImm(); 167 if (STI.hasFeature(Mips::FeatureMips32)) 168 Target &= 0xffffffff; 169 else if (STI.hasFeature(Mips::FeatureMips16)) 170 Target &= 0xffff; 171 markup(O, Markup::Immediate) << formatHex(Target); 172 } else { 173 markup(O, Markup::Immediate) << formatImm(Op.getImm()); 174 } 175 } 176 177 template <unsigned Bits, unsigned Offset> 178 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, 179 const MCSubtargetInfo &STI, raw_ostream &O) { 180 const MCOperand &MO = MI->getOperand(opNum); 181 if (MO.isImm()) { 182 uint64_t Imm = MO.getImm(); 183 Imm -= Offset; 184 Imm &= (1 << Bits) - 1; 185 Imm += Offset; 186 markup(O, Markup::Immediate) << formatImm(Imm); 187 return; 188 } 189 190 printOperand(MI, opNum, STI, O); 191 } 192 193 void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum, 194 const MCSubtargetInfo &STI, 195 raw_ostream &O) { 196 // Load/Store memory operands -- imm($reg) 197 // If PIC target the target is loaded as the 198 // pattern lw $25,%call16($28) 199 200 // opNum can be invalid if instruction had reglist as operand. 201 // MemOperand is always last operand of instruction (base + offset). 202 switch (MI->getOpcode()) { 203 default: 204 break; 205 case Mips::SWM32_MM: 206 case Mips::LWM32_MM: 207 case Mips::SWM16_MM: 208 case Mips::SWM16_MMR6: 209 case Mips::LWM16_MM: 210 case Mips::LWM16_MMR6: 211 opNum = MI->getNumOperands() - 2; 212 break; 213 } 214 215 WithMarkup M = markup(O, Markup::Memory); 216 printOperand(MI, opNum + 1, STI, O); 217 O << "("; 218 printOperand(MI, opNum, STI, O); 219 O << ")"; 220 } 221 222 void MipsInstPrinter::printMemOperandEA(const MCInst *MI, int opNum, 223 const MCSubtargetInfo &STI, 224 raw_ostream &O) { 225 // when using stack locations for not load/store instructions 226 // print the same way as all normal 3 operand instructions. 227 printOperand(MI, opNum, STI, O); 228 O << ", "; 229 printOperand(MI, opNum + 1, STI, O); 230 } 231 232 void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, 233 const MCSubtargetInfo & /* STI */, 234 raw_ostream &O) { 235 const MCOperand &MO = MI->getOperand(opNum); 236 O << MipsFCCToString((Mips::CondCode)MO.getImm()); 237 } 238 239 void MipsInstPrinter:: 240 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) { 241 llvm_unreachable("TODO"); 242 } 243 244 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, 245 uint64_t Address, unsigned OpNo, 246 const MCSubtargetInfo &STI, raw_ostream &OS, 247 bool IsBranch) { 248 OS << "\t" << Str << "\t"; 249 if (IsBranch) 250 printBranchOperand(&MI, Address, OpNo, STI, OS); 251 else 252 printOperand(&MI, OpNo, STI, OS); 253 return true; 254 } 255 256 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, 257 uint64_t Address, unsigned OpNo0, 258 unsigned OpNo1, const MCSubtargetInfo &STI, 259 raw_ostream &OS, bool IsBranch) { 260 printAlias(Str, MI, Address, OpNo0, STI, OS, IsBranch); 261 OS << ", "; 262 if (IsBranch) 263 printBranchOperand(&MI, Address, OpNo1, STI, OS); 264 else 265 printOperand(&MI, OpNo1, STI, OS); 266 return true; 267 } 268 269 bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address, 270 const MCSubtargetInfo &STI, raw_ostream &OS) { 271 switch (MI.getOpcode()) { 272 case Mips::BEQ: 273 case Mips::BEQ_MM: 274 // beq $zero, $zero, $L2 => b $L2 275 // beq $r0, $zero, $L2 => beqz $r0, $L2 276 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && 277 printAlias("b", MI, Address, 2, STI, OS, true)) || 278 (isReg<Mips::ZERO>(MI, 1) && 279 printAlias("beqz", MI, Address, 0, 2, STI, OS, true)); 280 case Mips::BEQ64: 281 // beq $r0, $zero, $L2 => beqz $r0, $L2 282 return isReg<Mips::ZERO_64>(MI, 1) && 283 printAlias("beqz", MI, Address, 0, 2, STI, OS, true); 284 case Mips::BNE: 285 case Mips::BNE_MM: 286 // bne $r0, $zero, $L2 => bnez $r0, $L2 287 return isReg<Mips::ZERO>(MI, 1) && 288 printAlias("bnez", MI, Address, 0, 2, STI, OS, true); 289 case Mips::BNE64: 290 // bne $r0, $zero, $L2 => bnez $r0, $L2 291 return isReg<Mips::ZERO_64>(MI, 1) && 292 printAlias("bnez", MI, Address, 0, 2, STI, OS, true); 293 case Mips::BGEZAL: 294 // bgezal $zero, $L1 => bal $L1 295 return isReg<Mips::ZERO>(MI, 0) && 296 printAlias("bal", MI, Address, 1, STI, OS, true); 297 case Mips::BC1T: 298 // bc1t $fcc0, $L1 => bc1t $L1 299 return isReg<Mips::FCC0>(MI, 0) && 300 printAlias("bc1t", MI, Address, 1, STI, OS, true); 301 case Mips::BC1F: 302 // bc1f $fcc0, $L1 => bc1f $L1 303 return isReg<Mips::FCC0>(MI, 0) && 304 printAlias("bc1f", MI, Address, 1, STI, OS, true); 305 case Mips::JALR: 306 // jalr $zero, $r1 => jr $r1 307 // jalr $ra, $r1 => jalr $r1 308 return (isReg<Mips::ZERO>(MI, 0) && 309 printAlias("jr", MI, Address, 1, STI, OS)) || 310 (isReg<Mips::RA>(MI, 0) && 311 printAlias("jalr", MI, Address, 1, STI, OS)); 312 case Mips::JALR64: 313 // jalr $zero, $r1 => jr $r1 314 // jalr $ra, $r1 => jalr $r1 315 return (isReg<Mips::ZERO_64>(MI, 0) && 316 printAlias("jr", MI, Address, 1, STI, OS)) || 317 (isReg<Mips::RA_64>(MI, 0) && 318 printAlias("jalr", MI, Address, 1, STI, OS)); 319 case Mips::NOR: 320 case Mips::NOR_MM: 321 case Mips::NOR_MMR6: 322 // nor $r0, $r1, $zero => not $r0, $r1 323 return isReg<Mips::ZERO>(MI, 2) && 324 printAlias("not", MI, Address, 0, 1, STI, OS); 325 case Mips::NOR64: 326 // nor $r0, $r1, $zero => not $r0, $r1 327 return isReg<Mips::ZERO_64>(MI, 2) && 328 printAlias("not", MI, Address, 0, 1, STI, OS); 329 case Mips::OR: 330 case Mips::ADDu: 331 // or $r0, $r1, $zero => move $r0, $r1 332 // addu $r0, $r1, $zero => move $r0, $r1 333 return isReg<Mips::ZERO>(MI, 2) && 334 printAlias("move", MI, Address, 0, 1, STI, OS); 335 default: 336 return false; 337 } 338 } 339 340 void MipsInstPrinter::printSaveRestore(const MCInst *MI, 341 const MCSubtargetInfo &STI, 342 raw_ostream &O) { 343 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 344 if (i != 0) O << ", "; 345 if (MI->getOperand(i).isReg()) 346 printRegName(O, MI->getOperand(i).getReg()); 347 else 348 printUImm<16>(MI, i, STI, O); 349 } 350 } 351 352 void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum, 353 const MCSubtargetInfo & /* STI */, 354 raw_ostream &O) { 355 // - 2 because register List is always first operand of instruction and it is 356 // always followed by memory operand (base + offset). 357 for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) { 358 if (i != opNum) 359 O << ", "; 360 printRegName(O, MI->getOperand(i).getReg()); 361 } 362 } 363