1//===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the MSP430 instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "MSP430InstrFormats.td" 14 15//===----------------------------------------------------------------------===// 16// Type Constraints. 17//===----------------------------------------------------------------------===// 18class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; 19class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; 20 21//===----------------------------------------------------------------------===// 22// Type Profiles. 23//===----------------------------------------------------------------------===// 24def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 25def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, 26 SDTCisVT<1, i16>]>; 27def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 28def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 29 SDTCisPtrTy<0>]>; 30def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 31def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, 32 SDTCisVT<1, i8>]>; 33def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 34 SDTCisSameAs<1, 2>, 35 SDTCisVT<3, i8>]>; 36def SDT_MSP430DAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisInt<0>]>; 39 40//===----------------------------------------------------------------------===// 41// MSP430 Specific Node Definitions. 42//===----------------------------------------------------------------------===// 43def MSP430retglue : SDNode<"MSP430ISD::RET_GLUE", SDTNone, 44 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 45def MSP430retiglue : SDNode<"MSP430ISD::RETI_GLUE", SDTNone, 46 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 47 48def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>; 49def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>; 50def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>; 51def MSP430rrcl : SDNode<"MSP430ISD::RRCL", SDTIntUnaryOp, []>; 52 53def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; 55def MSP430callseq_start : 56 SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart, 57 [SDNPHasChain, SDNPOutGlue]>; 58def MSP430callseq_end : 59 SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd, 60 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 61def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; 62def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutGlue]>; 63def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, 64 [SDNPHasChain, SDNPInGlue]>; 65def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, 66 [SDNPInGlue]>; 67def MSP430dadd : SDNode<"MSP430ISD::DADD", SDT_MSP430DAdd, []>; 68 69//===----------------------------------------------------------------------===// 70// MSP430 Operand Definitions. 71//===----------------------------------------------------------------------===// 72 73def MemAsmOperand : AsmOperandClass { 74 let Name = "Mem"; 75} 76 77// Address operands 78def memsrc : Operand<i16> { 79 let PrintMethod = "printSrcMemOperand"; 80 let MIOperandInfo = (ops GR16, i16imm); 81 let ParserMatchClass = MemAsmOperand; 82 let EncoderMethod = "getMemOpValue"; 83 let DecoderMethod = "DecodeMemOperand"; 84} 85 86def memdst : Operand<i16> { 87 let PrintMethod = "printSrcMemOperand"; 88 let MIOperandInfo = (ops GR16, i16imm); 89 let ParserMatchClass = MemAsmOperand; 90 let EncoderMethod = "getMemOpValue"; 91 let DecoderMethod = "DecodeMemOperand"; 92} 93 94def IndRegAsmOperand : AsmOperandClass { 95 let Name = "IndReg"; 96 let RenderMethod = "addRegOperands"; 97} 98 99def indreg : Operand<i16> { 100 let PrintMethod = "printIndRegOperand"; 101 let MIOperandInfo = (ops GR16); 102 let ParserMatchClass = IndRegAsmOperand; 103 let DecoderMethod = "DecodeGR16RegisterClass"; 104} 105 106def PostIndRegAsmOperand : AsmOperandClass { 107 let Name = "PostIndReg"; 108 let RenderMethod = "addRegOperands"; 109} 110 111def postreg : Operand<i16> { 112 let PrintMethod = "printPostIndRegOperand"; 113 let MIOperandInfo = (ops GR16); 114 let ParserMatchClass = PostIndRegAsmOperand; 115 let DecoderMethod = "DecodeGR16RegisterClass"; 116} 117 118// Short jump targets have OtherVT type and are printed as pcrel imm values. 119def jmptarget : Operand<OtherVT> { 120 let PrintMethod = "printPCRelImmOperand"; 121 let EncoderMethod = "getPCRelImmOpValue"; 122} 123 124// Operand for printing out a condition code. 125def cc : Operand<i8> { 126 let PrintMethod = "printCCOperand"; 127 let EncoderMethod = "getCCOpValue"; 128} 129 130def CGImmAsmOperand : AsmOperandClass { 131 let Name = "CGImm"; 132 let RenderMethod = "addImmOperands"; 133} 134 135def cg8imm : Operand<i8>, 136 ImmLeaf<i8, [{return Imm == 0 || Imm == 1 || Imm == 2 || 137 Imm == 4 || Imm == 8 || Imm == -1;}]> { 138 let ParserMatchClass = CGImmAsmOperand; 139 let EncoderMethod = "getCGImmOpValue"; 140 let DecoderMethod = "DecodeCGImm"; 141} 142 143def cg16imm : Operand<i16>, 144 ImmLeaf<i16, [{return Imm == 0 || Imm == 1 || Imm == 2 || 145 Imm == 4 || Imm == 8 || Imm == -1;}]> { 146 let ParserMatchClass = CGImmAsmOperand; 147 let EncoderMethod = "getCGImmOpValue"; 148 let DecoderMethod = "DecodeCGImm"; 149} 150 151//===----------------------------------------------------------------------===// 152// MSP430 Complex Pattern Definitions. 153//===----------------------------------------------------------------------===// 154 155def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>; 156 157//===----------------------------------------------------------------------===// 158// Pattern Fragments 159def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 160def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>; 161def bic : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, (not node:$rhs))>; 162def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 163 return N->hasOneUse(); 164}]>; 165//===----------------------------------------------------------------------===// 166// Instruction list.. 167 168// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into 169// a stack adjustment and the codegen must know that they may modify the stack 170// pointer before prolog-epilog rewriting occurs. 171// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 172// sub / add which can clobber SR. 173let isCodeGenOnly = 1, Defs = [SP, SR], Uses = [SP] in { 174def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), 175 "#ADJCALLSTACKDOWN $amt1 $amt2", 176 [(MSP430callseq_start timm:$amt1, timm:$amt2)]>; 177def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), 178 "#ADJCALLSTACKUP $amt1 $amt2", 179 [(MSP430callseq_end timm:$amt1, timm:$amt2)]>; 180} 181 182let isCodeGenOnly = 1, Defs = [SR], Uses = [SP] in { 183def ADDframe : Pseudo<(outs GR16:$dst), (ins i16imm:$base, i16imm:$offset), 184 "# ADDframe PSEUDO", []>; 185} 186 187let isCodeGenOnly = 1, usesCustomInserter = 1 in { 188 let Uses = [SR] in { 189 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc), 190 "# Select8 PSEUDO", 191 [(set GR8:$dst, 192 (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>; 193 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc), 194 "# Select16 PSEUDO", 195 [(set GR16:$dst, 196 (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>; 197 } 198 let Defs = [SR] in { 199 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 200 "# Shl8 PSEUDO", 201 [(set GR8:$dst, (shl GR8:$src, GR8:$cnt))]>; 202 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 203 "# Shl16 PSEUDO", 204 [(set GR16:$dst, (shl GR16:$src, GR8:$cnt))]>; 205 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 206 "# Sra8 PSEUDO", 207 [(set GR8:$dst, (sra GR8:$src, GR8:$cnt))]>; 208 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 209 "# Sra16 PSEUDO", 210 [(set GR16:$dst, (sra GR16:$src, GR8:$cnt))]>; 211 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), 212 "# Srl8 PSEUDO", 213 [(set GR8:$dst, (srl GR8:$src, GR8:$cnt))]>; 214 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), 215 "# Srl16 PSEUDO", 216 [(set GR16:$dst, (srl GR16:$src, GR8:$cnt))]>; 217 def Rrcl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src), "", 218 [(set GR8:$dst, (MSP430rrcl GR8:$src))]>; 219 def Rrcl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src), "", 220 [(set GR16:$dst, (MSP430rrcl GR16:$src))]>; 221 } 222} 223 224//===----------------------------------------------------------------------===// 225// Control Flow Instructions... 226// 227 228let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 229 def RET : IForm16<0b0100, DstReg, SrcPostInc, 2, 230 (outs), (ins), "ret", [(MSP430retglue)]> { 231 let DecoderNamespace = "Delta"; 232 let rs = 1; 233 let rd = 0; 234 } 235 def RETI : IIForm16<0b110, SrcReg, 2, 236 (outs), (ins), "reti", [(MSP430retiglue)]> { 237 let rs = 0; 238 } 239} 240 241let isBranch = 1, isTerminator = 1 in { 242 243// FIXME: expand opcode & cond field for branches! 244 245// Direct branch 246let isBarrier = 1 in { 247 // Short branch 248 def JMP : CJForm<(outs), (ins jmptarget:$dst), 249 "jmp\t$dst", 250 [(br bb:$dst)]> { 251 let cond = 0b111; 252 } 253 let isIndirectBranch = 1, rd = 0 in { 254 // Long branches 255 def Bi : I16ri<0b0100, (outs), (ins i16imm:$imm), 256 "br\t$imm", 257 [(brind tblockaddress:$imm)]>; 258 def Br : I16rr<0b0100, (outs), (ins GR16:$rs), 259 "br\t$rs", 260 [(brind GR16:$rs)]>; 261 def Bm : I16rm<0b0100, (outs), (ins memsrc:$src), 262 "br\t$src", 263 [(brind (load addr:$src))]>; 264 } 265} 266 267// Conditional branches 268let Uses = [SR] in 269 def JCC : CJForm<(outs), (ins jmptarget:$dst, cc:$cond), 270 "j$cond\t$dst", 271 [(MSP430brcc bb:$dst, imm:$cond)]>; 272} // isBranch, isTerminator 273 274//===----------------------------------------------------------------------===// 275// Call Instructions... 276// 277// All calls clobber the non-callee saved registers. SPW is marked as 278// a use to prevent stack-pointer assignments that appear immediately 279// before calls from potentially appearing dead. Uses for argument 280// registers are added manually. 281let isCall = 1, 282 Defs = [R11, R12, R13, R14, R15, SR], 283 Uses = [SP] in { 284 def CALLi : II16i<0b101, 285 (outs), (ins i16imm:$imm), 286 "call\t$imm", [(MSP430call imm:$imm)]>; 287 def CALLr : II16r<0b101, 288 (outs), (ins GR16:$rs), 289 "call\t$rs", [(MSP430call GR16:$rs)]>; 290 def CALLm : II16m<0b101, 291 (outs), (ins memsrc:$src), 292 "call\t$src", [(MSP430call (load addr:$src))]>; 293 def CALLn : II16n<0b101, (outs), (ins indreg:$rs), "call\t$rs", []>; 294 def CALLp : II16p<0b101, (outs), (ins postreg:$rs), "call\t$rs", []>; 295} 296 297//===----------------------------------------------------------------------===// 298// Miscellaneous Instructions... 299// 300let Defs = [SP], Uses = [SP], hasSideEffects = 0 in { 301let mayLoad = 1 in 302def POP16r : IForm16<0b0100, DstReg, SrcPostInc, 2, 303 (outs GR16:$rd), (ins), "pop\t$rd", []> { 304 let DecoderNamespace = "Delta"; 305 let rs = 1; 306} 307 308let mayStore = 1 in { 309def PUSH8r : II8r<0b100, (outs), (ins GR8:$rs), "push.b\t$rs", []>; 310def PUSH16r : II16r<0b100, (outs), (ins GR16:$rs), "push\t$rs", []>; 311def PUSH16c : II16c<0b100, (outs), (ins cg16imm:$imm), "push\t$imm", []>; 312def PUSH16i : II16i<0b100, (outs), (ins i16imm:$imm), "push\t$imm", []>; 313} 314} 315 316//===----------------------------------------------------------------------===// 317// Move Instructions 318 319let hasSideEffects = 0 in { 320def MOV8rr : I8rr<0b0100, 321 (outs GR8:$rd), (ins GR8:$rs), 322 "mov.b\t{$rs, $rd}", 323 []>; 324def MOV16rr : I16rr<0b0100, 325 (outs GR16:$rd), (ins GR16:$rs), 326 "mov\t{$rs, $rd}", 327 []>; 328} 329 330let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 331def MOV8rc : I8rc<0b0100, 332 (outs GR8:$rd), (ins cg8imm:$imm), 333 "mov.b\t$imm, $rd", 334 [(set GR8:$rd, cg8imm:$imm)]>; 335def MOV16rc : I16rc<0b0100, 336 (outs GR16:$rd), (ins cg16imm:$imm), 337 "mov\t$imm, $rd", 338 [(set GR16:$rd, cg16imm:$imm)]>; 339def MOV8ri : I8ri<0b0100, 340 (outs GR8:$rd), (ins i8imm:$imm), 341 "mov.b\t{$imm, $rd}", 342 [(set GR8:$rd, imm:$imm)]>; 343def MOV16ri : I16ri<0b0100, 344 (outs GR16:$rd), (ins i16imm:$imm), 345 "mov\t{$imm, $rd}", 346 [(set GR16:$rd, imm:$imm)]>; 347} 348 349let canFoldAsLoad = 1, isReMaterializable = 1 in { 350def MOV8rm : I8rm<0b0100, 351 (outs GR8:$rd), (ins memsrc:$src), 352 "mov.b\t{$src, $rd}", 353 [(set GR8:$rd, (load addr:$src))]>; 354def MOV16rm : I16rm<0b0100, 355 (outs GR16:$rd), (ins memsrc:$src), 356 "mov\t{$src, $rd}", 357 [(set GR16:$rd, (load addr:$src))]>; 358def MOV8rn : I8rn<0b0100, 359 (outs GR8:$rd), (ins indreg:$rs), 360 "mov.b\t{$rs, $rd}", 361 [(set GR8:$rd, (load addr:$rs))]>; 362def MOV16rn : I16rn<0b0100, 363 (outs GR16:$rd), (ins indreg:$rs), 364 "mov\t{$rs, $rd}", 365 [(set GR16:$rd, (load addr:$rs))]>; 366} 367 368let isCodeGenOnly = 1 in { 369def MOVZX16rr8 : I8rr<0b0100, 370 (outs GR16:$rd), (ins GR8:$rs), 371 "mov.b\t{$rs, $rd}", 372 [(set GR16:$rd, (zext GR8:$rs))]>; 373def MOVZX16rm8 : I8rm<0b0100, 374 (outs GR16:$rd), (ins memsrc:$src), 375 "mov.b\t{$src, $rd}", 376 [(set GR16:$rd, (zextloadi16i8 addr:$src))]>; 377} 378 379let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$rs = $wb" in { 380def MOV8rp : I8rp<0b0100, 381 (outs GR8:$rd, GR16:$wb), (ins postreg:$rs), 382 "mov.b\t{$rs, $rd}", []>; 383def MOV16rp : I16rp<0b0100, 384 (outs GR16:$rd, GR16:$wb), (ins postreg:$rs), 385 "mov\t{$rs, $rd}", []>; 386} 387 388// Any instruction that defines a 8-bit result leaves the high half of the 389// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may 390// be copying from a truncate, but any other 8-bit operation will zero-extend 391// up to 16 bits. 392def def8 : PatLeaf<(i8 GR8:$src), [{ 393 return N->getOpcode() != ISD::TRUNCATE && 394 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 395 N->getOpcode() != ISD::CopyFromReg; 396}]>; 397 398// In the case of a 8-bit def that is known to implicitly zero-extend, 399// we can use a SUBREG_TO_REG. 400def : Pat<(i16 (zext def8:$src)), 401 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; 402 403def MOV8mc : I8mc<0b0100, 404 (outs), (ins memdst:$dst, cg8imm:$imm), 405 "mov.b\t{$imm, $dst}", 406 [(store (i8 cg8imm:$imm), addr:$dst)]>; 407def MOV16mc : I16mc<0b0100, 408 (outs), (ins memdst:$dst, cg16imm:$imm), 409 "mov\t{$imm, $dst}", 410 [(store (i16 cg16imm:$imm), addr:$dst)]>; 411 412def MOV8mi : I8mi<0b0100, 413 (outs), (ins memdst:$dst, i8imm:$imm), 414 "mov.b\t{$imm, $dst}", 415 [(store (i8 imm:$imm), addr:$dst)]>; 416def MOV16mi : I16mi<0b0100, 417 (outs), (ins memdst:$dst, i16imm:$imm), 418 "mov\t{$imm, $dst}", 419 [(store (i16 imm:$imm), addr:$dst)]>; 420 421def MOV8mr : I8mr<0b0100, 422 (outs), (ins memdst:$dst, GR8:$rs), 423 "mov.b\t{$rs, $dst}", 424 [(store GR8:$rs, addr:$dst)]>; 425def MOV16mr : I16mr<0b0100, 426 (outs), (ins memdst:$dst, GR16:$rs), 427 "mov\t{$rs, $dst}", 428 [(store GR16:$rs, addr:$dst)]>; 429 430def MOV8mm : I8mm<0b0100, 431 (outs), (ins memdst:$dst, memsrc:$src), 432 "mov.b\t{$src, $dst}", 433 [(store (i8 (load addr:$src)), addr:$dst)]>; 434def MOV16mm : I16mm<0b0100, 435 (outs), (ins memdst:$dst, memsrc:$src), 436 "mov\t{$src, $dst}", 437 [(store (i16 (load addr:$src)), addr:$dst)]>; 438 439def MOV8mn : I8mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs), 440 "mov.b\t{$rs, $dst}", []>; 441def MOV16mn : I16mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs), 442 "mov\t{$rs, $dst}", []>; 443 444//===----------------------------------------------------------------------===// 445// Arithmetic Instructions 446 447multiclass Arith<bits<4> opcode, string asmstring, SDPatternOperator node, 448 bit commutes, list<Register> uses> { 449 let Defs = [SR], Uses = uses in { 450 let Constraints = "$src2 = $rd" in { 451 let isCommutable = commutes in { 452 def 8rr : I8rr<opcode, (outs GR8:$rd), (ins GR8:$src2, GR8:$rs), 453 !strconcat(asmstring, ".b\t$rs, $rd"), 454 [(set GR8:$rd, (node GR8:$src2, GR8:$rs))]>; 455 def 16rr : I16rr<opcode, (outs GR16:$rd), (ins GR16:$src2, GR16:$rs), 456 !strconcat(asmstring, "\t$rs, $rd"), 457 [(set GR16:$rd, (node GR16:$src2, GR16:$rs))]>; 458 } 459 def 8rm : I8rm<opcode, (outs GR8:$rd), (ins GR8:$src2, memsrc:$src), 460 !strconcat(asmstring, ".b\t$src, $rd"), 461 [(set GR8:$rd, (node GR8:$src2, (load addr:$src)))]>; 462 def 16rm : I16rm<opcode, (outs GR16:$rd), (ins GR16:$src2, memsrc:$src), 463 !strconcat(asmstring, "\t$src, $rd"), 464 [(set GR16:$rd, (node GR16:$src2, (load addr:$src)))]>; 465 def 8rn : I8rn<opcode, (outs GR8:$rd), (ins GR8:$src2, indreg:$rs), 466 !strconcat(asmstring, ".b\t$rs, $rd"), []>; 467 def 16rn : I16rn<opcode, (outs GR16:$rd), (ins GR16:$src2, indreg:$rs), 468 !strconcat(asmstring, "\t$rs, $rd"), []>; 469 let mayLoad = 1, 470 hasExtraDefRegAllocReq = 1, 471 Constraints = "$rs = $wb, $src2 = $rd" in { 472 def 8rp : I8rp<opcode, (outs GR8:$rd, GR16:$wb), (ins GR8:$src2, postreg:$rs), 473 !strconcat(asmstring, ".b\t$rs, $rd"), []>; 474 def 16rp : I16rp<opcode, (outs GR16:$rd, GR16:$wb), (ins GR16:$src2, postreg:$rs), 475 !strconcat(asmstring, "\t$rs, $rd"), []>; 476 } 477 def 8rc : I8rc<opcode, (outs GR8:$rd), (ins GR8:$src2, cg8imm:$imm), 478 !strconcat(asmstring, ".b\t$imm, $rd"), 479 [(set GR8:$rd, (node GR8:$src2, cg8imm:$imm))]>; 480 def 16rc : I16rc<opcode, (outs GR16:$rd), (ins GR16:$src2, cg16imm:$imm), 481 !strconcat(asmstring, "\t$imm, $rd"), 482 [(set GR16:$rd, (node GR16:$src2, cg16imm:$imm))]>; 483 def 8ri : I8ri<opcode, (outs GR8:$rd), (ins GR8:$src2, i8imm:$imm), 484 !strconcat(asmstring, ".b\t$imm, $rd"), 485 [(set GR8:$rd, (node GR8:$src2, imm:$imm))]>; 486 def 16ri : I16ri<opcode, (outs GR16:$rd), (ins GR16:$src2, i16imm:$imm), 487 !strconcat(asmstring, "\t$imm, $rd"), 488 [(set GR16:$rd, (node GR16:$src2, imm:$imm))]>; 489 } 490 def 8mr : I8mr<opcode, (outs), (ins memdst:$dst, GR8:$rs), 491 !strconcat(asmstring, ".b\t$rs, $dst"), 492 [(store (node (load addr:$dst), GR8:$rs), addr:$dst)]>; 493 def 16mr : I16mr<opcode, (outs), (ins memdst:$dst, GR16:$rs), 494 !strconcat(asmstring, "\t$rs, $dst"), 495 [(store (node (load addr:$dst), GR16:$rs), addr:$dst)]>; 496 def 8mc : I8mc<opcode, (outs), (ins memdst:$dst, cg8imm:$imm), 497 !strconcat(asmstring, ".b\t$imm, $dst"), 498 [(store (node (load addr:$dst), (i8 cg8imm:$imm)), addr:$dst)]>; 499 def 16mc : I16mc<opcode, (outs), (ins memdst:$dst, cg16imm:$imm), 500 !strconcat(asmstring, "\t$imm, $dst"), 501 [(store (node (load addr:$dst), (i16 cg16imm:$imm)), addr:$dst)]>; 502 def 8mi : I8mi<opcode, (outs), (ins memdst:$dst, i8imm:$imm), 503 !strconcat(asmstring, ".b\t$imm, $dst"), 504 [(store (node (load addr:$dst), (i8 imm:$imm)), addr:$dst)]>; 505 def 16mi : I16mi<opcode, (outs), (ins memdst:$dst, i16imm:$imm), 506 !strconcat(asmstring, "\t$imm, $dst"), 507 [(store (node (load addr:$dst), (i16 imm:$imm)), addr:$dst)]>; 508 def 8mm : I8mm<opcode, (outs), (ins memdst:$dst, memsrc:$src), 509 !strconcat(asmstring, ".b\t$src, $dst"), 510 [(store (node (load addr:$dst), 511 (i8 (load addr:$src))), addr:$dst)]>; 512 def 16mm : I16mm<opcode, (outs), (ins memdst:$dst, memsrc:$src), 513 !strconcat(asmstring, "\t$src, $dst"), 514 [(store (node (load addr:$dst), 515 (i16 (load addr:$src))), addr:$dst)]>; 516 def 8mn : I8mn<opcode, (outs), (ins memdst:$dst, indreg:$rs), 517 !strconcat(asmstring, ".b\t$rs, $dst"), []>; 518 def 16mn : I16mn<opcode, (outs), (ins memdst:$dst, indreg:$rs), 519 !strconcat(asmstring, "\t$rs, $dst"), []>; 520 def 8mp : I8mp<opcode, (outs), (ins memdst:$dst, postreg:$rs), 521 !strconcat(asmstring, ".b\t$rs, $dst"), []>; 522 def 16mp : I16mp<opcode, (outs), (ins memdst:$dst, postreg:$rs), 523 !strconcat(asmstring, "\t$rs, $dst"), []>; 524 } 525} 526 527defm ADD : Arith<0b0101, "add", add, 1, []>; 528defm ADDC : Arith<0b0110, "addc", adde, 1, [SR]>; 529defm AND : Arith<0b1111, "and", and, 1, []>; 530defm BIS : Arith<0b1101, "bis", or, 1, []>; 531defm BIC : Arith<0b1100, "bic", bic, 0, []>; 532defm XOR : Arith<0b1110, "xor", xor, 1, []>; 533defm SUB : Arith<0b1000, "sub", sub, 0, []>; 534defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>; 535defm DADD : Arith<0b1010, "dadd", MSP430dadd, 1, [SR]>; 536 537def ADC8r : InstAlias<"adc.b\t$dst", (ADDC8rc GR8:$dst, 0)>; 538def ADC16r : InstAlias<"adc\t$dst", (ADDC16rc GR16:$dst, 0)>; 539def ADC8m : InstAlias<"adc.b\t$dst", (ADDC8mc memdst:$dst, 0)>; 540def ADC16m : InstAlias<"adc\t$dst", (ADDC16mc memdst:$dst, 0)>; 541 542def DADC8r : InstAlias<"dadc.b\t$dst", (DADD8rc GR8:$dst, 0)>; 543def DADC16r : InstAlias<"dadc\t$dst", (DADD16rc GR16:$dst, 0)>; 544def DADC8m : InstAlias<"dadc.b\t$dst", (DADD8mc memdst:$dst, 0)>; 545def DADC16m : InstAlias<"dadc\t$dst", (DADD16mc memdst:$dst, 0)>; 546 547def DEC8r : InstAlias<"dec.b\t$dst", (SUB8rc GR8:$dst, 1)>; 548def DEC16r : InstAlias<"dec\t$dst", (SUB16rc GR16:$dst, 1)>; 549def DEC8m : InstAlias<"dec.b\t$dst", (SUB8mc memdst:$dst, 1)>; 550def DEC16m : InstAlias<"dec\t$dst", (SUB16mc memdst:$dst, 1)>; 551 552def DECD8r : InstAlias<"decd.b\t$dst", (SUB8rc GR8:$dst, 2)>; 553def DECD16r : InstAlias<"decd\t$dst", (SUB16rc GR16:$dst, 2)>; 554def DECD8m : InstAlias<"decd.b\t$dst", (SUB8mc memdst:$dst, 2)>; 555def DECD16m : InstAlias<"decd\t$dst", (SUB16mc memdst:$dst, 2)>; 556 557def INC8r : InstAlias<"inc.b\t$dst", (ADD8rc GR8:$dst, 1)>; 558def INC16r : InstAlias<"inc\t$dst", (ADD16rc GR16:$dst, 1)>; 559def INC8m : InstAlias<"inc.b\t$dst", (ADD8mc memdst:$dst, 1)>; 560def INC16m : InstAlias<"inc\t$dst", (ADD16mc memdst:$dst, 1)>; 561 562def INCD8r : InstAlias<"incd.b\t$dst", (ADD8rc GR8:$dst, 2)>; 563def INCD16r : InstAlias<"incd\t$dst", (ADD16rc GR16:$dst, 2)>; 564def INCD8m : InstAlias<"incd.b\t$dst", (ADD8mc memdst:$dst, 2)>; 565def INCD16m : InstAlias<"incd\t$dst", (ADD16mc memdst:$dst, 2)>; 566 567def SBC8r : InstAlias<"sbc.b\t$dst", (SUBC8rc GR8:$dst, 0)>; 568def SBC16r : InstAlias<"sbc\t$dst", (SUBC16rc GR16:$dst, 0)>; 569def SBC8m : InstAlias<"sbc.b\t$dst", (SUBC8mc memdst:$dst, 0)>; 570def SBC16m : InstAlias<"sbc\t$dst", (SUBC16mc memdst:$dst, 0)>; 571 572def INV8r : InstAlias<"inv.b\t$dst", (XOR8rc GR8:$dst, -1)>; 573def INV16r : InstAlias<"inv\t$dst", (XOR16rc GR16:$dst, -1)>; 574def INV8m : InstAlias<"inv.b\t$dst", (XOR8mc memdst:$dst, -1)>; 575def INV16m : InstAlias<"inv\t$dst", (XOR16mc memdst:$dst, -1)>; 576 577// printAliasInstr() doesn't check $dst operands are actually equal 578// for RLA and RLC aliases below, so disable printing aliases. 579 580def RLA8r : InstAlias<"rla.b\t$dst", (ADD8rr GR8:$dst, GR8:$dst), 0>; 581def RLA16r : InstAlias<"rla\t$dst", (ADD16rr GR16:$dst, GR16:$dst), 0>; 582def RLA8m : InstAlias<"rla.b\t$dst", (ADD8mm memdst:$dst, memdst:$dst), 0>; 583def RLA16m : InstAlias<"rla\t$dst", (ADD16mm memdst:$dst, memdst:$dst), 0>; 584 585def RLC8r : InstAlias<"rlc.b\t$dst", (ADDC8rr GR8:$dst, GR8:$dst), 0>; 586def RLC16r : InstAlias<"rlc\t$dst", (ADDC16rr GR16:$dst, GR16:$dst), 0>; 587def RLC8m : InstAlias<"rlc.b\t$dst", (ADDC8mm memdst:$dst, memdst:$dst), 0>; 588def RLC16m : InstAlias<"rlc\t$dst", (ADDC16mm memdst:$dst, memdst:$dst), 0>; 589 590def DINT : InstAlias<"dint", (BIC16rc SR, 8)>; 591def EINT : InstAlias<"eint", (BIS16rc SR, 8)>; 592 593def NOP : InstAlias<"nop", (MOV16rc CG, 0)>; 594 595def CLR8r : InstAlias<"clr.b\t$dst", (MOV8rc GR8:$dst, 0)>; 596def CLR16r : InstAlias<"clr\t$dst", (MOV16rc GR16:$dst, 0)>; 597def CLR8m : InstAlias<"clr.b\t$dst", (MOV8mc memdst:$dst, 0)>; 598def CLR16m : InstAlias<"clr\t$dst", (MOV16mc memdst:$dst, 0)>; 599 600def CLRC : InstAlias<"clrc", (BIC16rc SR, 1)>; 601def CLRN : InstAlias<"clrn", (BIC16rc SR, 4)>; 602def CLRZ : InstAlias<"clrz", (BIC16rc SR, 2)>; 603def SETC : InstAlias<"setc", (BIS16rc SR, 1)>; 604def SETN : InstAlias<"setn", (BIS16rc SR, 4)>; 605def SETZ : InstAlias<"setz", (BIS16rc SR, 2)>; 606 607def : Pat<(MSP430rla GR8:$dst), (ADD8rr $dst, $dst)>; 608def : Pat<(MSP430rla GR16:$dst), (ADD16rr $dst, $dst)>; 609 610// Format-II (Single Operand) Instruction 611// Register mode 612let Constraints = "$rs = $rd" in { 613 614let Defs = [SR] in { 615def RRA8r : II8r<0b010, 616 (outs GR8:$rd), (ins GR8:$rs), 617 "rra.b\t$rd", 618 [(set GR8:$rd, (MSP430rra GR8:$rs))]>; 619def RRA16r : II16r<0b010, 620 (outs GR16:$rd), (ins GR16:$rs), 621 "rra\t$rd", 622 [(set GR16:$rd, (MSP430rra GR16:$rs))]>; 623 624let Uses = [SR] in { 625def RRC8r : II8r<0b000, 626 (outs GR8:$rd), (ins GR8:$rs), 627 "rrc.b\t$rd", 628 [(set GR8:$rd, (MSP430rrc GR8:$rs))]>; 629def RRC16r : II16r<0b000, 630 (outs GR16:$rd), (ins GR16:$rs), 631 "rrc\t$rd", 632 [(set GR16:$rd, (MSP430rrc GR16:$rs))]>; 633} // Uses = [SR] 634 635def SEXT16r : II16r<0b011, 636 (outs GR16:$rd), (ins GR16:$rs), 637 "sxt\t$rd", 638 [(set GR16:$rd, (sext_inreg GR16:$rs, i8))]>; 639 640} // Defs = [SR] 641 642let isCodeGenOnly = 1 in 643def ZEXT16r : I8rr<0b0100, 644 (outs GR16:$rd), (ins GR16:$rs), 645 "mov.b\t{$rs, $rd}", 646 [(set GR16:$rd, (zext (trunc GR16:$rs)))]>; 647 648def SWPB16r : II16r<0b001, 649 (outs GR16:$rd), (ins GR16:$rs), 650 "swpb\t$rd", 651 [(set GR16:$rd, (bswap GR16:$rs))]>; 652 653} // Constraints = "$src = $dst" 654 655// Indexed, indirect register and indirect autoincrement modes 656let Defs = [SR] in { 657def RRA8m : II8m<0b010, 658 (outs), (ins memsrc:$src), 659 "rra.b\t$src", 660 [(store (MSP430rra (i8 (load addr:$src))), addr:$src)]>; 661def RRA16m : II16m<0b010, 662 (outs), (ins memsrc:$src), 663 "rra\t$src", 664 [(store (MSP430rra (i16 (load addr:$src))), addr:$src)]>; 665 666def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>; 667def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>; 668def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>; 669def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>; 670 671let Uses = [SR] in { 672def RRC8m : II8m<0b000, 673 (outs), (ins memsrc:$src), 674 "rrc.b\t$src", 675 [(store (MSP430rrc (i8 (load addr:$src))), addr:$src)]>; 676def RRC16m : II16m<0b000, 677 (outs), (ins memsrc:$src), 678 "rrc\t$src", 679 [(store (MSP430rrc (i16 (load addr:$src))), addr:$src)]>; 680 681def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>; 682def RRC16n : II16n<0b000, (outs), (ins indreg:$rs), "rrc\t$rs", []>; 683def RRC8p : II8p<0b000, (outs), (ins postreg:$rs), "rrc.b\t$rs", []>; 684def RRC16p : II16p<0b000, (outs), (ins postreg:$rs), "rrc\t$rs", []>; 685 686} // Uses = [SR] 687 688def SEXT16m : II16m<0b011, 689 (outs), (ins memsrc:$src), 690 "sxt\t$src", 691 [(store (sext_inreg (extloadi16i8 addr:$src), i8), 692 addr:$src)]>; 693def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs", []>; 694def SEXT16p : II16p<0b011, (outs), (ins postreg:$rs), "sxt\t$rs", []>; 695 696} // Defs = [SR] 697 698def SWPB16m : II16m<0b001, 699 (outs), (ins memsrc:$src), 700 "swpb\t$src", 701 [(store (bswap (i16 (load addr:$src))), addr:$src)]>; 702def SWPB16n : II16n<0b001, (outs), (ins indreg:$rs), "swpb\t$rs", []>; 703def SWPB16p : II16p<0b001, (outs), (ins postreg:$rs), "swpb\t$rs", []>; 704 705// Integer comparisons 706let Defs = [SR] in { 707def CMP8rr : I8rr<0b1001, 708 (outs), (ins GR8:$rd, GR8:$rs), 709 "cmp.b\t$rs, $rd", 710 [(MSP430cmp GR8:$rd, GR8:$rs)]>; 711def CMP16rr : I16rr<0b1001, 712 (outs), (ins GR16:$rd, GR16:$rs), 713 "cmp\t$rs, $rd", 714 [(MSP430cmp GR16:$rd, GR16:$rs)]>; 715 716def CMP8rc : I8rc<0b1001, 717 (outs), (ins GR8:$rd, cg8imm:$imm), 718 "cmp.b\t$imm, $rd", 719 [(MSP430cmp GR8:$rd, cg8imm:$imm)]>; 720def CMP16rc : I16rc<0b1001, 721 (outs), (ins GR16:$rd, cg16imm:$imm), 722 "cmp\t$imm, $rd", 723 [(MSP430cmp GR16:$rd, cg16imm:$imm)]>; 724 725def CMP8ri : I8ri<0b1001, 726 (outs), (ins GR8:$rd, i8imm:$imm), 727 "cmp.b\t$imm, $rd", 728 [(MSP430cmp GR8:$rd, imm:$imm)]>; 729def CMP16ri : I16ri<0b1001, 730 (outs), (ins GR16:$rd, i16imm:$imm), 731 "cmp\t$imm, $rd", 732 [(MSP430cmp GR16:$rd, imm:$imm)]>; 733 734def CMP8mc : I8mc<0b1001, 735 (outs), (ins memsrc:$dst, cg8imm:$imm), 736 "cmp.b\t$imm, $dst", 737 [(MSP430cmp (load addr:$dst), (i8 cg8imm:$imm))]>; 738def CMP16mc : I16mc<0b1001, 739 (outs), (ins memsrc:$dst, cg16imm:$imm), 740 "cmp\t$imm, $dst", 741 [(MSP430cmp (load addr:$dst), (i16 cg16imm:$imm))]>; 742 743def CMP8mi : I8mi<0b1001, 744 (outs), (ins memsrc:$dst, i8imm:$imm), 745 "cmp.b\t$imm, $dst", 746 [(MSP430cmp (load addr:$dst), 747 (i8 imm:$imm))]>; 748def CMP16mi : I16mi<0b1001, 749 (outs), (ins memsrc:$dst, i16imm:$imm), 750 "cmp\t$imm, $dst", 751 [(MSP430cmp (load addr:$dst), 752 (i16 imm:$imm))]>; 753 754def CMP8rm : I8rm<0b1001, 755 (outs), (ins GR8:$rd, memsrc:$src), 756 "cmp.b\t$src, $rd", 757 [(MSP430cmp GR8:$rd, (load addr:$src))]>; 758def CMP16rm : I16rm<0b1001, 759 (outs), (ins GR16:$rd, memsrc:$src), 760 "cmp\t$src, $rd", 761 [(MSP430cmp GR16:$rd, (load addr:$src))]>; 762 763def CMP8rn : I8rn<0b1001, 764 (outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>; 765def CMP16rn : I16rn<0b1001, 766 (outs), (ins GR16:$rd, indreg:$rs), "cmp\t$rs, $rd", []>; 767 768def CMP8rp : I8rp<0b1001, 769 (outs), (ins GR8:$rd, postreg:$rs), "cmp.b\t$rs, $rd", []>; 770def CMP16rp : I16rp<0b1001, 771 (outs), (ins GR16:$rd, postreg:$rs), "cmp\t$rs, $rd", []>; 772 773def CMP8mr : I8mr<0b1001, 774 (outs), (ins memsrc:$dst, GR8:$rs), 775 "cmp.b\t$rs, $dst", 776 [(MSP430cmp (load addr:$dst), GR8:$rs)]>; 777def CMP16mr : I16mr<0b1001, 778 (outs), (ins memsrc:$dst, GR16:$rs), 779 "cmp\t$rs, $dst", 780 [(MSP430cmp (load addr:$dst), GR16:$rs)]>; 781def CMP8mm : I8mm<0b1001, 782 (outs), (ins memdst:$dst, memsrc:$src), 783 "cmp.b\t$src, $dst", 784 [(MSP430cmp (load addr:$dst), (i8 (load addr:$src)))]>; 785def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src), 786 "cmp\t$src, $dst", 787 [(MSP430cmp (load addr:$dst), (i16 (load addr:$src)))]>; 788 789def CMP8mn : I8mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs), 790 "cmp.b\t$rs, $dst", []>; 791def CMP16mn : I16mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs), 792 "cmp\t$rs, $dst", []>; 793 794def CMP8mp : I8mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs), 795 "cmp.b\t$rs, $dst", []>; 796def CMP16mp : I16mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs), 797 "cmp\t$rs, $dst", []>; 798 799// BIT TESTS, just sets condition codes 800// Note that the C condition is set differently than when using CMP. 801let isCommutable = 1 in { 802def BIT8rr : I8rr<0b1011, 803 (outs), (ins GR8:$rd, GR8:$rs), 804 "bit.b\t$rs, $rd", 805 [(MSP430cmp (and_su GR8:$rd, GR8:$rs), 0)]>; 806def BIT16rr : I16rr<0b1011, 807 (outs), (ins GR16:$rd, GR16:$rs), 808 "bit\t$rs, $rd", 809 [(MSP430cmp (and_su GR16:$rd, GR16:$rs), 0)]>; 810} 811def BIT8rc : I8rc<0b1011, 812 (outs), (ins GR8:$rd, cg8imm:$imm), 813 "bit.b\t$imm, $rd", 814 [(MSP430cmp (and_su GR8:$rd, cg8imm:$imm), 0)]>; 815def BIT16rc : I16rc<0b1011, 816 (outs), (ins GR16:$rd, cg16imm:$imm), 817 "bit\t$imm, $rd", 818 [(MSP430cmp (and_su GR16:$rd, cg16imm:$imm), 0)]>; 819 820def BIT8ri : I8ri<0b1011, 821 (outs), (ins GR8:$rd, i8imm:$imm), 822 "bit.b\t$imm, $rd", 823 [(MSP430cmp (and_su GR8:$rd, imm:$imm), 0)]>; 824def BIT16ri : I16ri<0b1011, 825 (outs), (ins GR16:$rd, i16imm:$imm), 826 "bit\t$imm, $rd", 827 [(MSP430cmp (and_su GR16:$rd, imm:$imm), 0)]>; 828 829def BIT8rm : I8rm<0b1011, 830 (outs), (ins GR8:$rd, memdst:$src), 831 "bit.b\t$src, $rd", 832 [(MSP430cmp (and_su GR8:$rd, (load addr:$src)), 0)]>; 833def BIT16rm : I16rm<0b1011, 834 (outs), (ins GR16:$rd, memdst:$src), 835 "bit\t$src, $rd", 836 [(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0)]>; 837 838def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs), 839 "bit.b\t$rs, $rd", []>; 840def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs), 841 "bit\t$rs, $rd", []>; 842 843def BIT8rp : I8rp<0b1011, (outs), (ins GR8:$rd, postreg:$rs), 844 "bit.b\t$rs, $rd", []>; 845def BIT16rp : I16rp<0b1011, (outs), (ins GR16:$rd, postreg:$rs), 846 "bit\t$rs, $rd", []>; 847 848def BIT8mr : I8mr<0b1011, 849 (outs), (ins memsrc:$dst, GR8:$rs), 850 "bit.b\t$rs, $dst", 851 [(MSP430cmp (and_su (load addr:$dst), GR8:$rs), 0)]>; 852def BIT16mr : I16mr<0b1011, 853 (outs), (ins memsrc:$dst, GR16:$rs), 854 "bit\t$rs, $dst", 855 [(MSP430cmp (and_su (load addr:$dst), GR16:$rs), 0)]>; 856 857def BIT8mc : I8mc<0b1011, 858 (outs), (ins memsrc:$dst, cg8imm:$imm), 859 "bit.b\t$imm, $dst", 860 [(MSP430cmp (and_su (load addr:$dst), (i8 cg8imm:$imm)), 0)]>; 861def BIT16mc : I16mc<0b1011, 862 (outs), (ins memdst:$dst, cg16imm:$imm), 863 "bit\t$imm, $dst", 864 [(MSP430cmp (and_su (load addr:$dst), (i16 cg16imm:$imm)), 0)]>; 865 866def BIT8mi : I8mi<0b1011, 867 (outs), (ins memsrc:$dst, i8imm:$imm), 868 "bit.b\t$imm, $dst", 869 [(MSP430cmp (and_su (load addr:$dst), (i8 imm:$imm)), 0)]>; 870def BIT16mi : I16mi<0b1011, 871 (outs), (ins memsrc:$dst, i16imm:$imm), 872 "bit\t$imm, $dst", 873 [(MSP430cmp (and_su (load addr:$dst), (i16 imm:$imm)), 0)]>; 874 875def BIT8mm : I8mm<0b1011, 876 (outs), (ins memsrc:$dst, memsrc:$src), 877 "bit.b\t$src, $dst", 878 [(MSP430cmp (and_su (i8 (load addr:$dst)), 879 (load addr:$src)), 880 0)]>; 881def BIT16mm : I16mm<0b1011, 882 (outs), (ins memsrc:$dst, memsrc:$src), 883 "bit\t$src, $dst", 884 [(MSP430cmp (and_su (i16 (load addr:$dst)), 885 (load addr:$src)), 886 0)]>; 887def BIT8mn : I8mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs), 888 "bit.b\t$rs, $dst", []>; 889def BIT16mn : I16mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs), 890 "bit\t$rs, $dst", []>; 891 892def BIT8mp : I8mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs), 893 "bit.b\t$rs, $dst", []>; 894def BIT16mp : I16mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs), 895 "bit\t$rs, $dst", []>; 896 897} // Defs = [SR] 898 899def TST8r : InstAlias<"tst.b\t$dst", (CMP8rc GR8:$dst, 0)>; 900def TST16r : InstAlias<"tst\t$dst", (CMP16rc GR16:$dst, 0)>; 901def TST8m : InstAlias<"tst.b\t$dst", (CMP8mc memdst:$dst, 0)>; 902def TST16m : InstAlias<"tst\t$dst", (CMP16mc memdst:$dst, 0)>; 903 904//===----------------------------------------------------------------------===// 905// Non-Instruction Patterns 906 907// extload 908def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 909 910// anyext 911def : Pat<(i16 (anyext GR8:$src)), 912 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; 913 914// truncs 915def : Pat<(i8 (trunc GR16:$src)), 916 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>; 917 918// GlobalAddress, ExternalSymbol 919def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>; 920def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>; 921def : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>; 922 923def : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)), 924 (ADD16ri GR16:$src, tglobaladdr:$src2)>; 925def : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)), 926 (ADD16ri GR16:$src, texternalsym:$src2)>; 927def : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)), 928 (ADD16ri GR16:$src, tblockaddress:$src2)>; 929 930def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst), 931 (MOV16mi addr:$dst, tglobaladdr:$src)>; 932def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst), 933 (MOV16mi addr:$dst, texternalsym:$src)>; 934def : Pat<(store (i16 (MSP430Wrapper tblockaddress:$src)), addr:$dst), 935 (MOV16mi addr:$dst, tblockaddress:$src)>; 936 937// calls 938def : Pat<(MSP430call (i16 tglobaladdr:$dst)), 939 (CALLi tglobaladdr:$dst)>; 940def : Pat<(MSP430call (i16 texternalsym:$dst)), 941 (CALLi texternalsym:$dst)>; 942 943// add and sub always produce carry 944def : Pat<(addc GR16:$src, GR16:$src2), 945 (ADD16rr GR16:$src, GR16:$src2)>; 946def : Pat<(addc GR16:$src, (load addr:$src2)), 947 (ADD16rm GR16:$src, addr:$src2)>; 948def : Pat<(addc GR16:$src, imm:$src2), 949 (ADD16ri GR16:$src, imm:$src2)>; 950def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst), 951 (ADD16mr addr:$dst, GR16:$src)>; 952def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 953 (ADD16mm addr:$dst, addr:$src)>; 954 955def : Pat<(addc GR8:$src, GR8:$src2), 956 (ADD8rr GR8:$src, GR8:$src2)>; 957def : Pat<(addc GR8:$src, (load addr:$src2)), 958 (ADD8rm GR8:$src, addr:$src2)>; 959def : Pat<(addc GR8:$src, imm:$src2), 960 (ADD8ri GR8:$src, imm:$src2)>; 961def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst), 962 (ADD8mr addr:$dst, GR8:$src)>; 963def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 964 (ADD8mm addr:$dst, addr:$src)>; 965 966def : Pat<(subc GR16:$src, GR16:$src2), 967 (SUB16rr GR16:$src, GR16:$src2)>; 968def : Pat<(subc GR16:$src, (load addr:$src2)), 969 (SUB16rm GR16:$src, addr:$src2)>; 970def : Pat<(subc GR16:$src, imm:$src2), 971 (SUB16ri GR16:$src, imm:$src2)>; 972def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst), 973 (SUB16mr addr:$dst, GR16:$src)>; 974def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), 975 (SUB16mm addr:$dst, addr:$src)>; 976 977def : Pat<(subc GR8:$src, GR8:$src2), 978 (SUB8rr GR8:$src, GR8:$src2)>; 979def : Pat<(subc GR8:$src, (load addr:$src2)), 980 (SUB8rm GR8:$src, addr:$src2)>; 981def : Pat<(subc GR8:$src, imm:$src2), 982 (SUB8ri GR8:$src, imm:$src2)>; 983def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst), 984 (SUB8mr addr:$dst, GR8:$src)>; 985def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), 986 (SUB8mm addr:$dst, addr:$src)>; 987 988// peephole patterns 989def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>; 990def : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0), 991 (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit), 992 (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>; 993