1//===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/TableGen/SearchableTable.td" 10 11//===----------------------------------------------------------------------===// 12// Declarations that describe the ARM system-registers 13//===----------------------------------------------------------------------===// 14 15// M-Class System Registers. 16// 'Mask' bits create unique keys for searches. 17// 18class MClassSysReg<bits<1> UniqMask1, 19 bits<1> UniqMask2, 20 bits<1> UniqMask3, 21 bits<12> Enc12, 22 string name> { 23 string Name; 24 bits<13> M1Encoding12; 25 bits<10> M2M3Encoding8; 26 bits<12> Encoding; 27 28 let Name = name; 29 30 let M1Encoding12{12} = UniqMask1; 31 let M1Encoding12{11-00} = Enc12; 32 let Encoding = Enc12; 33 34 let M2M3Encoding8{9} = UniqMask2; 35 let M2M3Encoding8{8} = UniqMask3; 36 let M2M3Encoding8{7-0} = Enc12{7-0}; 37 code Requires = [{ {} }]; 38} 39 40def MClassSysRegsList : GenericTable { 41 let FilterClass = "MClassSysReg"; 42 let Fields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding", 43 "Requires"]; 44} 45 46def lookupMClassSysRegByName : SearchIndex { 47 let Table = MClassSysRegsList; 48 let Key = ["Name"]; 49} 50 51def lookupMClassSysRegByM1Encoding12 : SearchIndex { 52 let Table = MClassSysRegsList; 53 let Key = ["M1Encoding12"]; 54} 55 56def lookupMClassSysRegByM2M3Encoding8 : SearchIndex { 57 let Table = MClassSysRegsList; 58 let Key = ["M2M3Encoding8"]; 59} 60 61// [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr. 62// Mask1 Mask2 Mask3 Enc12, Name 63let Requires = [{ {ARM::FeatureDSP} }] in { 64def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">; 65def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">; 66def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">; 67def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">; 68def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">; 69def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">; 70def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">; 71def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">; 72} 73 74def : MClassSysReg<0, 0, 1, 0x800, "apsr">; 75def : MClassSysReg<1, 1, 0, 0x800, "apsr_nzcvq">; 76def : MClassSysReg<0, 0, 1, 0x801, "iapsr">; 77def : MClassSysReg<1, 1, 0, 0x801, "iapsr_nzcvq">; 78def : MClassSysReg<0, 0, 1, 0x802, "eapsr">; 79def : MClassSysReg<1, 1, 0, 0x802, "eapsr_nzcvq">; 80def : MClassSysReg<0, 0, 1, 0x803, "xpsr">; 81def : MClassSysReg<1, 1, 0, 0x803, "xpsr_nzcvq">; 82 83def : MClassSysReg<0, 0, 1, 0x805, "ipsr">; 84def : MClassSysReg<0, 0, 1, 0x806, "epsr">; 85def : MClassSysReg<0, 0, 1, 0x807, "iepsr">; 86def : MClassSysReg<0, 0, 1, 0x808, "msp">; 87def : MClassSysReg<0, 0, 1, 0x809, "psp">; 88 89let Requires = [{ {ARM::HasV8MBaselineOps} }] in { 90def : MClassSysReg<0, 0, 1, 0x80a, "msplim">; 91def : MClassSysReg<0, 0, 1, 0x80b, "psplim">; 92} 93 94def : MClassSysReg<0, 0, 1, 0x810, "primask">; 95 96let Requires = [{ {ARM::HasV7Ops} }] in { 97def : MClassSysReg<0, 0, 1, 0x811, "basepri">; 98def : MClassSysReg<0, 0, 1, 0x812, "basepri_max">; 99def : MClassSysReg<0, 0, 1, 0x813, "faultmask">; 100} 101 102def : MClassSysReg<0, 0, 1, 0x814, "control">; 103 104let Requires = [{ {ARM::Feature8MSecExt} }] in { 105def : MClassSysReg<0, 0, 1, 0x888, "msp_ns">; 106def : MClassSysReg<0, 0, 1, 0x889, "psp_ns">; 107} 108 109let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in { 110def : MClassSysReg<0, 0, 1, 0x88a, "msplim_ns">; 111def : MClassSysReg<0, 0, 1, 0x88b, "psplim_ns">; 112} 113 114def : MClassSysReg<0, 0, 1, 0x890, "primask_ns">; 115 116let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in { 117def : MClassSysReg<0, 0, 1, 0x891, "basepri_ns">; 118def : MClassSysReg<0, 0, 1, 0x893, "faultmask_ns">; 119} 120 121let Requires = [{ {ARM::Feature8MSecExt} }] in { 122def : MClassSysReg<0, 0, 1, 0x894, "control_ns">; 123def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">; 124} 125 126let Requires = [{ {ARM::FeaturePACBTI} }] in { 127def : MClassSysReg<0, 0, 1, 0x820, "pac_key_p_0">; 128def : MClassSysReg<0, 0, 1, 0x821, "pac_key_p_1">; 129def : MClassSysReg<0, 0, 1, 0x822, "pac_key_p_2">; 130def : MClassSysReg<0, 0, 1, 0x823, "pac_key_p_3">; 131def : MClassSysReg<0, 0, 1, 0x824, "pac_key_u_0">; 132def : MClassSysReg<0, 0, 1, 0x825, "pac_key_u_1">; 133def : MClassSysReg<0, 0, 1, 0x826, "pac_key_u_2">; 134def : MClassSysReg<0, 0, 1, 0x827, "pac_key_u_3">; 135def : MClassSysReg<0, 0, 1, 0x8a0, "pac_key_p_0_ns">; 136def : MClassSysReg<0, 0, 1, 0x8a1, "pac_key_p_1_ns">; 137def : MClassSysReg<0, 0, 1, 0x8a2, "pac_key_p_2_ns">; 138def : MClassSysReg<0, 0, 1, 0x8a3, "pac_key_p_3_ns">; 139def : MClassSysReg<0, 0, 1, 0x8a4, "pac_key_u_0_ns">; 140def : MClassSysReg<0, 0, 1, 0x8a5, "pac_key_u_1_ns">; 141def : MClassSysReg<0, 0, 1, 0x8a6, "pac_key_u_2_ns">; 142def : MClassSysReg<0, 0, 1, 0x8a7, "pac_key_u_3_ns">; 143} 144 145// Banked Registers 146// 147class BankedReg<string name, bits<8> enc> { 148 string Name; 149 bits<8> Encoding; 150 let Name = name; 151 let Encoding = enc; 152} 153 154def BankedRegsList : GenericTable { 155 let FilterClass = "BankedReg"; 156 let Fields = ["Name", "Encoding"]; 157 158 let PrimaryKey = ["Encoding"]; 159 let PrimaryKeyName = "lookupBankedRegByEncoding"; 160} 161 162def lookupBankedRegByName : SearchIndex { 163 let Table = BankedRegsList; 164 let Key = ["Name"]; 165} 166 167 168// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM 169// and bit 5 is R. 170def : BankedReg<"r8_usr", 0x00>; 171def : BankedReg<"r9_usr", 0x01>; 172def : BankedReg<"r10_usr", 0x02>; 173def : BankedReg<"r11_usr", 0x03>; 174def : BankedReg<"r12_usr", 0x04>; 175def : BankedReg<"sp_usr", 0x05>; 176def : BankedReg<"lr_usr", 0x06>; 177def : BankedReg<"r8_fiq", 0x08>; 178def : BankedReg<"r9_fiq", 0x09>; 179def : BankedReg<"r10_fiq", 0x0a>; 180def : BankedReg<"r11_fiq", 0x0b>; 181def : BankedReg<"r12_fiq", 0x0c>; 182def : BankedReg<"sp_fiq", 0x0d>; 183def : BankedReg<"lr_fiq", 0x0e>; 184def : BankedReg<"lr_irq", 0x10>; 185def : BankedReg<"sp_irq", 0x11>; 186def : BankedReg<"lr_svc", 0x12>; 187def : BankedReg<"sp_svc", 0x13>; 188def : BankedReg<"lr_abt", 0x14>; 189def : BankedReg<"sp_abt", 0x15>; 190def : BankedReg<"lr_und", 0x16>; 191def : BankedReg<"sp_und", 0x17>; 192def : BankedReg<"lr_mon", 0x1c>; 193def : BankedReg<"sp_mon", 0x1d>; 194def : BankedReg<"elr_hyp", 0x1e>; 195def : BankedReg<"sp_hyp", 0x1f>; 196def : BankedReg<"spsr_fiq", 0x2e>; 197def : BankedReg<"spsr_irq", 0x30>; 198def : BankedReg<"spsr_svc", 0x32>; 199def : BankedReg<"spsr_abt", 0x34>; 200def : BankedReg<"spsr_und", 0x36>; 201def : BankedReg<"spsr_mon", 0x3c>; 202def : BankedReg<"spsr_hyp", 0x3e>; 203