1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// This file provides AMDGPU specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AMDGPUMCTargetDesc.h" 15 #include "AMDGPUELFStreamer.h" 16 #include "AMDGPUInstPrinter.h" 17 #include "AMDGPUMCAsmInfo.h" 18 #include "AMDGPUTargetStreamer.h" 19 #include "R600InstPrinter.h" 20 #include "R600MCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "llvm/MC/MCAsmBackend.h" 23 #include "llvm/MC/MCCodeEmitter.h" 24 #include "llvm/MC/MCELFStreamer.h" 25 #include "llvm/MC/MCInstPrinter.h" 26 #include "llvm/MC/MCInstrAnalysis.h" 27 #include "llvm/MC/MCInstrDesc.h" 28 #include "llvm/MC/MCInstrInfo.h" 29 #include "llvm/MC/MCObjectWriter.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCStreamer.h" 32 #include "llvm/MC/MCSubtargetInfo.h" 33 #include "llvm/MC/TargetRegistry.h" 34 35 using namespace llvm; 36 37 #define GET_INSTRINFO_MC_DESC 38 #define ENABLE_INSTR_PREDICATE_VERIFIER 39 #include "AMDGPUGenInstrInfo.inc" 40 41 #define GET_SUBTARGETINFO_MC_DESC 42 #include "AMDGPUGenSubtargetInfo.inc" 43 44 #define NoSchedModel NoSchedModelR600 45 #define GET_SUBTARGETINFO_MC_DESC 46 #include "R600GenSubtargetInfo.inc" 47 #undef NoSchedModelR600 48 49 #define GET_REGINFO_MC_DESC 50 #include "AMDGPUGenRegisterInfo.inc" 51 52 #define GET_REGINFO_MC_DESC 53 #include "R600GenRegisterInfo.inc" 54 55 static MCInstrInfo *createAMDGPUMCInstrInfo() { 56 MCInstrInfo *X = new MCInstrInfo(); 57 InitAMDGPUMCInstrInfo(X); 58 return X; 59 } 60 61 static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) { 62 MCRegisterInfo *X = new MCRegisterInfo(); 63 if (TT.getArch() == Triple::r600) 64 InitR600MCRegisterInfo(X, 0); 65 else 66 InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG); 67 return X; 68 } 69 70 MCRegisterInfo *llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour) { 71 MCRegisterInfo *X = new MCRegisterInfo(); 72 InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour, DwarfFlavour); 73 return X; 74 } 75 76 static MCSubtargetInfo * 77 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 78 if (TT.getArch() == Triple::r600) 79 return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 80 81 MCSubtargetInfo *STI = 82 createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 83 84 // FIXME: We should error for the default target. 85 if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) && 86 !STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) { 87 // If there is no default wave size it must be a generation before gfx10, 88 // these have FeatureWavefrontSize64 in their definition already. For gfx10+ 89 // set wave32 as a default. 90 STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI) 91 ? AMDGPU::FeatureWavefrontSize32 92 : AMDGPU::FeatureWavefrontSize64); 93 } 94 95 return STI; 96 } 97 98 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T, 99 unsigned SyntaxVariant, 100 const MCAsmInfo &MAI, 101 const MCInstrInfo &MII, 102 const MCRegisterInfo &MRI) { 103 if (T.getArch() == Triple::r600) 104 return new R600InstPrinter(MAI, MII, MRI); 105 return new AMDGPUInstPrinter(MAI, MII, MRI); 106 } 107 108 static MCTargetStreamer * 109 createAMDGPUAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, 110 MCInstPrinter *InstPrint) { 111 return new AMDGPUTargetAsmStreamer(S, OS); 112 } 113 114 static MCTargetStreamer * createAMDGPUObjectTargetStreamer( 115 MCStreamer &S, 116 const MCSubtargetInfo &STI) { 117 return new AMDGPUTargetELFStreamer(S, STI); 118 } 119 120 static MCTargetStreamer *createAMDGPUNullTargetStreamer(MCStreamer &S) { 121 return new AMDGPUTargetStreamer(S); 122 } 123 124 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, 125 std::unique_ptr<MCAsmBackend> &&MAB, 126 std::unique_ptr<MCObjectWriter> &&OW, 127 std::unique_ptr<MCCodeEmitter> &&Emitter) { 128 return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW), 129 std::move(Emitter)); 130 } 131 132 namespace { 133 134 class AMDGPUMCInstrAnalysis : public MCInstrAnalysis { 135 public: 136 explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info) 137 : MCInstrAnalysis(Info) {} 138 139 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 140 uint64_t &Target) const override { 141 if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() || 142 Info->get(Inst.getOpcode()).operands()[0].OperandType != 143 MCOI::OPERAND_PCREL) 144 return false; 145 146 int64_t Imm = Inst.getOperand(0).getImm(); 147 // Our branches take a simm16. 148 Target = SignExtend64<16>(Imm) * 4 + Addr + Size; 149 return true; 150 } 151 }; 152 153 } // end anonymous namespace 154 155 static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) { 156 return new AMDGPUMCInstrAnalysis(Info); 157 } 158 159 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC() { 160 161 TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo); 162 TargetRegistry::RegisterMCInstrInfo(getTheR600Target(), 163 createR600MCInstrInfo); 164 for (Target *T : {&getTheR600Target(), &getTheGCNTarget()}) { 165 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T); 166 167 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo); 168 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo); 169 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter); 170 TargetRegistry::RegisterMCInstrAnalysis(*T, createAMDGPUMCInstrAnalysis); 171 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend); 172 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); 173 } 174 175 // R600 specific registration 176 TargetRegistry::RegisterMCCodeEmitter(getTheR600Target(), 177 createR600MCCodeEmitter); 178 TargetRegistry::RegisterObjectTargetStreamer( 179 getTheR600Target(), createAMDGPUObjectTargetStreamer); 180 181 // GCN specific registration 182 TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(), 183 createAMDGPUMCCodeEmitter); 184 185 TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(), 186 createAMDGPUAsmTargetStreamer); 187 TargetRegistry::RegisterObjectTargetStreamer( 188 getTheGCNTarget(), createAMDGPUObjectTargetStreamer); 189 TargetRegistry::RegisterNullTargetStreamer(getTheGCNTarget(), 190 createAMDGPUNullTargetStreamer); 191 } 192