1//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// AArch64 system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// Features that, for the compiler, only enable system operands and PStates 18//===----------------------------------------------------------------------===// 19 20def HasCCPP : Predicate<"Subtarget->hasCCPP()">, 21 AssemblerPredicateWithAll<(all_of FeatureCCPP), "ccpp">; 22 23def HasPAN : Predicate<"Subtarget->hasPAN()">, 24 AssemblerPredicateWithAll<(all_of FeaturePAN), 25 "ARM v8.1 Privileged Access-Never extension">; 26 27def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, 28 AssemblerPredicateWithAll<(all_of FeaturePsUAO), 29 "ARM v8.2 UAO PState extension (psuao)">; 30 31def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">, 32 AssemblerPredicateWithAll<(all_of FeaturePAN_RWV), 33 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">; 34 35def HasCONTEXTIDREL2 36 : Predicate<"Subtarget->hasCONTEXTIDREL2()">, 37 AssemblerPredicateWithAll<(all_of FeatureCONTEXTIDREL2), 38 "Target contains CONTEXTIDR_EL2 RW operand">; 39 40//===----------------------------------------------------------------------===// 41// AT (address translate) instruction options. 42//===----------------------------------------------------------------------===// 43 44class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm, 45 bits<3> op2> { 46 string Name = name; 47 bits<14> Encoding; 48 let Encoding{13-11} = op1; 49 let Encoding{10-7} = crn; 50 let Encoding{6-3} = crm; 51 let Encoding{2-0} = op2; 52 code Requires = [{ {} }]; 53} 54 55def ATValues : GenericEnum { 56 let FilterClass = "AT"; 57 let NameField = "Name"; 58 let ValueField = "Encoding"; 59} 60 61def ATsList : GenericTable { 62 let FilterClass = "AT"; 63 let Fields = ["Name", "Encoding", "Requires"]; 64 65 let PrimaryKey = ["Encoding"]; 66 let PrimaryKeyName = "lookupATByEncoding"; 67} 68 69def lookupATByName : SearchIndex { 70 let Table = ATsList; 71 let Key = ["Name"]; 72} 73 74def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>; 75def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>; 76def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>; 77def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>; 78def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>; 79def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>; 80def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>; 81def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>; 82def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>; 83def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>; 84def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>; 85def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>; 86 87let Requires = [{ {AArch64::FeaturePAN_RWV} }] in { 88def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; 89def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; 90} 91 92// v8.9a/v9.4a FEAT_ATS1A 93def : AT<"S1E1A", 0b000, 0b0111, 0b1001, 0b010>; 94def : AT<"S1E2A", 0b100, 0b0111, 0b1001, 0b010>; 95def : AT<"S1E3A", 0b110, 0b0111, 0b1001, 0b010>; 96 97//===----------------------------------------------------------------------===// 98// DMB/DSB (data barrier) instruction options. 99//===----------------------------------------------------------------------===// 100 101class DB<string name, bits<4> encoding> { 102 string Name = name; 103 bits<4> Encoding = encoding; 104} 105 106def DBValues : GenericEnum { 107 let FilterClass = "DB"; 108 let NameField = "Name"; 109 let ValueField = "Encoding"; 110} 111 112def DBsList : GenericTable { 113 let FilterClass = "DB"; 114 let Fields = ["Name", "Encoding"]; 115 116 let PrimaryKey = ["Encoding"]; 117 let PrimaryKeyName = "lookupDBByEncoding"; 118} 119 120def lookupDBByName : SearchIndex { 121 let Table = DBsList; 122 let Key = ["Name"]; 123} 124 125def : DB<"oshld", 0x1>; 126def : DB<"oshst", 0x2>; 127def : DB<"osh", 0x3>; 128def : DB<"nshld", 0x5>; 129def : DB<"nshst", 0x6>; 130def : DB<"nsh", 0x7>; 131def : DB<"ishld", 0x9>; 132def : DB<"ishst", 0xa>; 133def : DB<"ish", 0xb>; 134def : DB<"ld", 0xd>; 135def : DB<"st", 0xe>; 136def : DB<"sy", 0xf>; 137 138class DBnXS<string name, bits<4> encoding, bits<5> immValue> { 139 string Name = name; 140 bits<4> Encoding = encoding; 141 bits<5> ImmValue = immValue; 142 code Requires = [{ {AArch64::FeatureXS} }]; 143} 144 145def DBnXSValues : GenericEnum { 146 let FilterClass = "DBnXS"; 147 let NameField = "Name"; 148 let ValueField = "Encoding"; 149} 150 151def DBnXSsList : GenericTable { 152 let FilterClass = "DBnXS"; 153 let Fields = ["Name", "Encoding", "ImmValue", "Requires"]; 154 155 let PrimaryKey = ["Encoding"]; 156 let PrimaryKeyName = "lookupDBnXSByEncoding"; 157} 158 159def lookupDBnXSByName : SearchIndex { 160 let Table = DBnXSsList; 161 let Key = ["Name"]; 162} 163 164def lookupDBnXSByImmValue : SearchIndex { 165 let Table = DBnXSsList; 166 let Key = ["ImmValue"]; 167} 168 169def : DBnXS<"oshnxs", 0x3, 0x10>; 170def : DBnXS<"nshnxs", 0x7, 0x14>; 171def : DBnXS<"ishnxs", 0xb, 0x18>; 172def : DBnXS<"synxs", 0xf, 0x1c>; 173 174//===----------------------------------------------------------------------===// 175// DC (data cache maintenance) instruction options. 176//===----------------------------------------------------------------------===// 177 178class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm, 179 bits<3> op2> { 180 string Name = name; 181 bits<14> Encoding; 182 let Encoding{13-11} = op1; 183 let Encoding{10-7} = crn; 184 let Encoding{6-3} = crm; 185 let Encoding{2-0} = op2; 186 code Requires = [{ {} }]; 187} 188 189def DCValues : GenericEnum { 190 let FilterClass = "DC"; 191 let NameField = "Name"; 192 let ValueField = "Encoding"; 193} 194 195def DCsList : GenericTable { 196 let FilterClass = "DC"; 197 let Fields = ["Name", "Encoding", "Requires"]; 198 199 let PrimaryKey = ["Encoding"]; 200 let PrimaryKeyName = "lookupDCByEncoding"; 201} 202 203def lookupDCByName : SearchIndex { 204 let Table = DCsList; 205 let Key = ["Name"]; 206} 207 208def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>; 209def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>; 210def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>; 211def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>; 212def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>; 213def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>; 214def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; 215def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; 216 217let Requires = [{ {AArch64::FeatureCCPP} }] in 218def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; 219 220let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in 221def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>; 222 223let Requires = [{ {AArch64::FeatureMTE} }] in { 224def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>; 225def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>; 226def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>; 227def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; 228def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>; 229def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>; 230def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>; 231def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; 232def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>; 233def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>; 234def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>; 235def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>; 236def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; 237def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>; 238def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>; 239def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>; 240def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; 241def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>; 242} 243 244let Requires = [{ {AArch64::FeatureMEC} }] in { 245def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>; 246def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>; 247} 248 249let Requires = [{ {AArch64::FeatureRME} }] in { 250def : DC<"CIGDPAPA", 0b110, 0b0111, 0b1110, 0b101>; 251def : DC<"CIPAPA", 0b110, 0b0111, 0b1110, 0b001>; 252} 253 254let Requires = [{ {AArch64::FeatureOCCMO} }] in { 255// Outer cacheable CMO (FEAT_OCCMO) 256def : DC<"CIVAOC", 0b011, 0b0111, 0b1111, 0b000>; 257def : DC<"CVAOC", 0b011, 0b0111, 0b1011, 0b000>; 258} 259 260let Requires = [{ {AArch64::FeatureOCCMO, AArch64::FeatureMTE} }] in { 261def : DC<"CIGDVAOC", 0b011, 0b0111, 0b1111, 0b111>; 262def : DC<"CGDVAOC", 0b011, 0b0111, 0b1011, 0b111>; 263} 264 265//===----------------------------------------------------------------------===// 266// IC (instruction cache maintenance) instruction options. 267//===----------------------------------------------------------------------===// 268 269class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, 270 bit needsreg> { 271 string Name = name; 272 bits<14> Encoding; 273 let Encoding{13-11} = op1; 274 let Encoding{10-7} = crn; 275 let Encoding{6-3} = crm; 276 let Encoding{2-0} = op2; 277 bit NeedsReg = needsreg; 278} 279 280def ICValues : GenericEnum { 281 let FilterClass = "IC"; 282 let NameField = "Name"; 283 let ValueField = "Encoding"; 284} 285 286def ICsList : GenericTable { 287 let FilterClass = "IC"; 288 let Fields = ["Name", "Encoding", "NeedsReg"]; 289 290 let PrimaryKey = ["Encoding"]; 291 let PrimaryKeyName = "lookupICByEncoding"; 292} 293 294def lookupICByName : SearchIndex { 295 let Table = ICsList; 296 let Key = ["Name"]; 297} 298 299def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>; 300def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>; 301def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>; 302 303//===----------------------------------------------------------------------===// 304// ISB (instruction-fetch barrier) instruction options. 305//===----------------------------------------------------------------------===// 306 307class ISB<string name, bits<4> encoding> { 308 string Name = name; 309 bits<4> Encoding; 310 let Encoding = encoding; 311} 312 313def ISBValues : GenericEnum { 314 let FilterClass = "ISB"; 315 let NameField = "Name"; 316 let ValueField = "Encoding"; 317} 318 319def ISBsList : GenericTable { 320 let FilterClass = "ISB"; 321 let Fields = ["Name", "Encoding"]; 322 323 let PrimaryKey = ["Encoding"]; 324 let PrimaryKeyName = "lookupISBByEncoding"; 325} 326 327def lookupISBByName : SearchIndex { 328 let Table = ISBsList; 329 let Key = ["Name"]; 330} 331 332def : ISB<"sy", 0xf>; 333 334//===----------------------------------------------------------------------===// 335// TSB (Trace synchronization barrier) instruction options. 336//===----------------------------------------------------------------------===// 337 338class TSB<string name, bits<4> encoding> { 339 string Name = name; 340 bits<4> Encoding; 341 let Encoding = encoding; 342 343 code Requires = [{ {AArch64::FeatureTRACEV8_4} }]; 344} 345 346def TSBValues : GenericEnum { 347 let FilterClass = "TSB"; 348 let NameField = "Name"; 349 let ValueField = "Encoding"; 350} 351 352def TSBsList : GenericTable { 353 let FilterClass = "TSB"; 354 let Fields = ["Name", "Encoding", "Requires"]; 355 356 let PrimaryKey = ["Encoding"]; 357 let PrimaryKeyName = "lookupTSBByEncoding"; 358} 359 360def lookupTSBByName : SearchIndex { 361 let Table = TSBsList; 362 let Key = ["Name"]; 363} 364 365def : TSB<"csync", 0>; 366 367//===----------------------------------------------------------------------===// 368// PRFM (prefetch) instruction options. 369//===----------------------------------------------------------------------===// 370 371class PRFM<string type, bits<2> type_encoding, 372 string target, bits<2> target_encoding, 373 string policy, bits<1> policy_encoding> { 374 string Name = type # target # policy; 375 bits<5> Encoding; 376 let Encoding{4-3} = type_encoding; 377 let Encoding{2-1} = target_encoding; 378 let Encoding{0} = policy_encoding; 379 380 code Requires = [{ {} }]; 381} 382 383def PRFMValues : GenericEnum { 384 let FilterClass = "PRFM"; 385 let NameField = "Name"; 386 let ValueField = "Encoding"; 387} 388 389def PRFMsList : GenericTable { 390 let FilterClass = "PRFM"; 391 let Fields = ["Name", "Encoding", "Requires"]; 392 393 let PrimaryKey = ["Encoding"]; 394 let PrimaryKeyName = "lookupPRFMByEncoding"; 395} 396 397def lookupPRFMByName : SearchIndex { 398 let Table = PRFMsList; 399 let Key = ["Name"]; 400} 401 402def : PRFM<"pld", 0b00, "l1", 0b00, "keep", 0b0>; 403def : PRFM<"pld", 0b00, "l1", 0b00, "strm", 0b1>; 404def : PRFM<"pld", 0b00, "l2", 0b01, "keep", 0b0>; 405def : PRFM<"pld", 0b00, "l2", 0b01, "strm", 0b1>; 406def : PRFM<"pld", 0b00, "l3", 0b10, "keep", 0b0>; 407def : PRFM<"pld", 0b00, "l3", 0b10, "strm", 0b1>; 408let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 409def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>; 410def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>; 411} 412def : PRFM<"pli", 0b01, "l1", 0b00, "keep", 0b0>; 413def : PRFM<"pli", 0b01, "l1", 0b00, "strm", 0b1>; 414def : PRFM<"pli", 0b01, "l2", 0b01, "keep", 0b0>; 415def : PRFM<"pli", 0b01, "l2", 0b01, "strm", 0b1>; 416def : PRFM<"pli", 0b01, "l3", 0b10, "keep", 0b0>; 417def : PRFM<"pli", 0b01, "l3", 0b10, "strm", 0b1>; 418let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 419def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>; 420def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>; 421} 422def : PRFM<"pst", 0b10, "l1", 0b00, "keep", 0b0>; 423def : PRFM<"pst", 0b10, "l1", 0b00, "strm", 0b1>; 424def : PRFM<"pst", 0b10, "l2", 0b01, "keep", 0b0>; 425def : PRFM<"pst", 0b10, "l2", 0b01, "strm", 0b1>; 426def : PRFM<"pst", 0b10, "l3", 0b10, "keep", 0b0>; 427def : PRFM<"pst", 0b10, "l3", 0b10, "strm", 0b1>; 428let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { 429def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>; 430def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>; 431} 432 433//===----------------------------------------------------------------------===// 434// SVE Prefetch instruction options. 435//===----------------------------------------------------------------------===// 436 437class SVEPRFM<string name, bits<4> encoding> { 438 string Name = name; 439 bits<4> Encoding; 440 let Encoding = encoding; 441 code Requires = [{ {} }]; 442} 443 444def SVEPRFMValues : GenericEnum { 445 let FilterClass = "SVEPRFM"; 446 let NameField = "Name"; 447 let ValueField = "Encoding"; 448} 449 450def SVEPRFMsList : GenericTable { 451 let FilterClass = "SVEPRFM"; 452 let Fields = ["Name", "Encoding", "Requires"]; 453 454 let PrimaryKey = ["Encoding"]; 455 let PrimaryKeyName = "lookupSVEPRFMByEncoding"; 456} 457 458def lookupSVEPRFMByName : SearchIndex { 459 let Table = SVEPRFMsList; 460 let Key = ["Name"]; 461} 462 463let Requires = [{ {AArch64::FeatureSVE} }] in { 464def : SVEPRFM<"pldl1keep", 0x00>; 465def : SVEPRFM<"pldl1strm", 0x01>; 466def : SVEPRFM<"pldl2keep", 0x02>; 467def : SVEPRFM<"pldl2strm", 0x03>; 468def : SVEPRFM<"pldl3keep", 0x04>; 469def : SVEPRFM<"pldl3strm", 0x05>; 470def : SVEPRFM<"pstl1keep", 0x08>; 471def : SVEPRFM<"pstl1strm", 0x09>; 472def : SVEPRFM<"pstl2keep", 0x0a>; 473def : SVEPRFM<"pstl2strm", 0x0b>; 474def : SVEPRFM<"pstl3keep", 0x0c>; 475def : SVEPRFM<"pstl3strm", 0x0d>; 476} 477 478//===----------------------------------------------------------------------===// 479// RPRFM (prefetch) instruction options. 480//===----------------------------------------------------------------------===// 481 482class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> { 483 string Name = name; 484 bits<6> Encoding; 485 let Encoding{0} = type_encoding; 486 let Encoding{5-1} = policy_encoding; 487 code Requires = [{ {} }]; 488} 489 490def RPRFMValues : GenericEnum { 491 let FilterClass = "RPRFM"; 492 let NameField = "Name"; 493 let ValueField = "Encoding"; 494} 495 496def RPRFMsList : GenericTable { 497 let FilterClass = "RPRFM"; 498 let Fields = ["Name", "Encoding", "Requires"]; 499} 500 501def lookupRPRFMByName : SearchIndex { 502 let Table = RPRFMsList; 503 let Key = ["Name"]; 504} 505 506def lookupRPRFMByEncoding : SearchIndex { 507 let Table = RPRFMsList; 508 let Key = ["Encoding"]; 509} 510 511def : RPRFM<"pldkeep", 0b0, 0b00000>; 512def : RPRFM<"pstkeep", 0b1, 0b00000>; 513def : RPRFM<"pldstrm", 0b0, 0b00010>; 514def : RPRFM<"pststrm", 0b1, 0b00010>; 515 516//===----------------------------------------------------------------------===// 517// SVE Predicate patterns 518//===----------------------------------------------------------------------===// 519 520class SVEPREDPAT<string name, bits<5> encoding> { 521 string Name = name; 522 bits<5> Encoding; 523 let Encoding = encoding; 524} 525 526def SVEPREDPATValues : GenericEnum { 527 let FilterClass = "SVEPREDPAT"; 528 let NameField = "Name"; 529 let ValueField = "Encoding"; 530} 531 532def SVEPREDPATsList : GenericTable { 533 let FilterClass = "SVEPREDPAT"; 534 let Fields = ["Name", "Encoding"]; 535 536 let PrimaryKey = ["Encoding"]; 537 let PrimaryKeyName = "lookupSVEPREDPATByEncoding"; 538} 539 540def lookupSVEPREDPATByName : SearchIndex { 541 let Table = SVEPREDPATsList; 542 let Key = ["Name"]; 543} 544 545def : SVEPREDPAT<"pow2", 0x00>; 546def : SVEPREDPAT<"vl1", 0x01>; 547def : SVEPREDPAT<"vl2", 0x02>; 548def : SVEPREDPAT<"vl3", 0x03>; 549def : SVEPREDPAT<"vl4", 0x04>; 550def : SVEPREDPAT<"vl5", 0x05>; 551def : SVEPREDPAT<"vl6", 0x06>; 552def : SVEPREDPAT<"vl7", 0x07>; 553def : SVEPREDPAT<"vl8", 0x08>; 554def : SVEPREDPAT<"vl16", 0x09>; 555def : SVEPREDPAT<"vl32", 0x0a>; 556def : SVEPREDPAT<"vl64", 0x0b>; 557def : SVEPREDPAT<"vl128", 0x0c>; 558def : SVEPREDPAT<"vl256", 0x0d>; 559def : SVEPREDPAT<"mul4", 0x1d>; 560def : SVEPREDPAT<"mul3", 0x1e>; 561def : SVEPREDPAT<"all", 0x1f>; 562 563//===----------------------------------------------------------------------===// 564// SVE Predicate-as-counter patterns 565//===----------------------------------------------------------------------===// 566 567class SVEVECLENSPECIFIER<string name, bits<1> encoding> { 568 string Name = name; 569 bits<1> Encoding; 570 let Encoding = encoding; 571} 572 573def SVEVECLENSPECIFIERValues : GenericEnum { 574 let FilterClass = "SVEVECLENSPECIFIER"; 575 let NameField = "Name"; 576 let ValueField = "Encoding"; 577} 578 579def SVEVECLENSPECIFIERsList : GenericTable { 580 let FilterClass = "SVEVECLENSPECIFIER"; 581 let Fields = ["Name", "Encoding"]; 582 583 let PrimaryKey = ["Encoding"]; 584 let PrimaryKeyName = "lookupSVEVECLENSPECIFIERByEncoding"; 585} 586 587def lookupSVEVECLENSPECIFIERByName : SearchIndex { 588 let Table = SVEVECLENSPECIFIERsList; 589 let Key = ["Name"]; 590} 591 592def : SVEVECLENSPECIFIER<"vlx2", 0x0>; 593def : SVEVECLENSPECIFIER<"vlx4", 0x1>; 594 595//===----------------------------------------------------------------------===// 596// Exact FP Immediates. 597// 598// These definitions are used to create a lookup table with FP Immediates that 599// is used for a few instructions that only accept a limited set of exact FP 600// immediates values. 601//===----------------------------------------------------------------------===// 602class ExactFPImm<string name, string repr, bits<4> enum > { 603 string Name = name; 604 bits<4> Enum = enum; 605 string Repr = repr; 606} 607 608def ExactFPImmValues : GenericEnum { 609 let FilterClass = "ExactFPImm"; 610 let NameField = "Name"; 611 let ValueField = "Enum"; 612} 613 614def ExactFPImmsList : GenericTable { 615 let FilterClass = "ExactFPImm"; 616 let Fields = ["Enum", "Repr"]; 617} 618 619def lookupExactFPImmByEnum : SearchIndex { 620 let Table = ExactFPImmsList; 621 let Key = ["Enum"]; 622} 623 624def : ExactFPImm<"zero", "0.0", 0x0>; 625def : ExactFPImm<"half", "0.5", 0x1>; 626def : ExactFPImm<"one", "1.0", 0x2>; 627def : ExactFPImm<"two", "2.0", 0x3>; 628 629//===----------------------------------------------------------------------===// 630// PState instruction options. 631//===----------------------------------------------------------------------===// 632 633class PStateImm0_15<string name, bits<3> op1, bits<3> op2> { 634 string Name = name; 635 bits<6> Encoding; 636 let Encoding{5-3} = op1; 637 let Encoding{2-0} = op2; 638 code Requires = [{ {} }]; 639} 640 641def PStateImm0_15Values : GenericEnum { 642 let FilterClass = "PStateImm0_15"; 643 let NameField = "Name"; 644 let ValueField = "Encoding"; 645} 646 647def PStateImm0_15sList : GenericTable { 648 let FilterClass = "PStateImm0_15"; 649 let Fields = ["Name", "Encoding", "Requires"]; 650 651 let PrimaryKey = ["Encoding"]; 652 let PrimaryKeyName = "lookupPStateImm0_15ByEncoding"; 653} 654 655def lookupPStateImm0_15ByName : SearchIndex { 656 let Table = PStateImm0_15sList; 657 let Key = ["Name"]; 658} 659 660class PStateImm0_1<string name, bits<3> op1, bits<3> op2, bits<3> crm_high> { 661 string Name = name; 662 bits<9> Encoding; 663 let Encoding{8-6} = crm_high; 664 let Encoding{5-3} = op1; 665 let Encoding{2-0} = op2; 666 code Requires = [{ {} }]; 667} 668 669def PStateImm0_1Values : GenericEnum { 670 let FilterClass = "PStateImm0_1"; 671 let NameField = "Name"; 672 let ValueField = "Encoding"; 673} 674 675def PStateImm0_1sList : GenericTable { 676 let FilterClass = "PStateImm0_1"; 677 let Fields = ["Name", "Encoding", "Requires"]; 678 679 let PrimaryKey = ["Encoding"]; 680 let PrimaryKeyName = "lookupPStateImm0_1ByEncoding"; 681} 682 683def lookupPStateImm0_1ByName : SearchIndex { 684 let Table = PStateImm0_1sList; 685 let Key = ["Name"]; 686} 687 688// Name, Op1, Op2 689def : PStateImm0_15<"SPSel", 0b000, 0b101>; 690def : PStateImm0_15<"DAIFSet", 0b011, 0b110>; 691def : PStateImm0_15<"DAIFClr", 0b011, 0b111>; 692// v8.1a "Privileged Access Never" extension-specific PStates 693let Requires = [{ {AArch64::FeaturePAN} }] in 694def : PStateImm0_15<"PAN", 0b000, 0b100>; 695 696// v8.2a "User Access Override" extension-specific PStates 697let Requires = [{ {AArch64::FeaturePsUAO} }] in 698def : PStateImm0_15<"UAO", 0b000, 0b011>; 699// v8.4a timing insensitivity of data processing instructions 700let Requires = [{ {AArch64::FeatureDIT} }] in 701def : PStateImm0_15<"DIT", 0b011, 0b010>; 702// v8.5a Spectre Mitigation 703let Requires = [{ {AArch64::FeatureSSBS} }] in 704def : PStateImm0_15<"SSBS", 0b011, 0b001>; 705// v8.5a Memory Tagging Extension 706let Requires = [{ {AArch64::FeatureMTE} }] in 707def : PStateImm0_15<"TCO", 0b011, 0b100>; 708// v8.8a Non-Maskable Interrupts 709let Requires = [{ {AArch64::FeatureNMI} }] in 710def : PStateImm0_1<"ALLINT", 0b001, 0b000, 0b000>; 711// v9.4a Exception-based event profiling 712// Name, Op1, Op2, Crm_high 713def : PStateImm0_1<"PM", 0b001, 0b000, 0b001>; 714 715//===----------------------------------------------------------------------===// 716// SVCR instruction options. 717//===----------------------------------------------------------------------===// 718 719class SVCR<string name, bits<3> encoding> { 720 string Name = name; 721 bits<3> Encoding; 722 let Encoding = encoding; 723 code Requires = [{ {} }]; 724} 725 726def SVCRValues : GenericEnum { 727 let FilterClass = "SVCR"; 728 let NameField = "Name"; 729 let ValueField = "Encoding"; 730} 731 732def SVCRsList : GenericTable { 733 let FilterClass = "SVCR"; 734 let Fields = ["Name", "Encoding", "Requires"]; 735 736 let PrimaryKey = ["Encoding"]; 737 let PrimaryKeyName = "lookupSVCRByEncoding"; 738} 739 740def lookupSVCRByName : SearchIndex { 741 let Table = SVCRsList; 742 let Key = ["Name"]; 743} 744 745let Requires = [{ {AArch64::FeatureSME} }] in { 746def : SVCR<"SVCRSM", 0b001>; 747def : SVCR<"SVCRZA", 0b010>; 748def : SVCR<"SVCRSMZA", 0b011>; 749} 750 751//===----------------------------------------------------------------------===// 752// PSB instruction options. 753//===----------------------------------------------------------------------===// 754 755class PSB<string name, bits<5> encoding> { 756 string Name = name; 757 bits<5> Encoding; 758 let Encoding = encoding; 759} 760 761def PSBValues : GenericEnum { 762 let FilterClass = "PSB"; 763 let NameField = "Name"; 764 let ValueField = "Encoding"; 765} 766 767def PSBsList : GenericTable { 768 let FilterClass = "PSB"; 769 let Fields = ["Name", "Encoding"]; 770 771 let PrimaryKey = ["Encoding"]; 772 let PrimaryKeyName = "lookupPSBByEncoding"; 773} 774 775def lookupPSBByName : SearchIndex { 776 let Table = PSBsList; 777 let Key = ["Name"]; 778} 779 780def : PSB<"csync", 0x11>; 781 782//===----------------------------------------------------------------------===// 783// BTI instruction options. 784//===----------------------------------------------------------------------===// 785 786class BTI<string name, bits<3> encoding> { 787 string Name = name; 788 bits<3> Encoding; 789 let Encoding = encoding; 790} 791 792def BTIValues : GenericEnum { 793 let FilterClass = "BTI"; 794 let NameField = "Name"; 795 let ValueField = "Encoding"; 796} 797 798def BTIsList : GenericTable { 799 let FilterClass = "BTI"; 800 let Fields = ["Name", "Encoding"]; 801 802 let PrimaryKey = ["Encoding"]; 803 let PrimaryKeyName = "lookupBTIByEncoding"; 804} 805 806def lookupBTIByName : SearchIndex { 807 let Table = BTIsList; 808 let Key = ["Name"]; 809} 810 811def : BTI<"c", 0b010>; 812def : BTI<"j", 0b100>; 813def : BTI<"jc", 0b110>; 814 815//===----------------------------------------------------------------------===// 816// TLBI (translation lookaside buffer invalidate) instruction options. 817//===----------------------------------------------------------------------===// 818 819class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm, 820 bits<3> op2, bit needsreg> { 821 string Name = name; 822 bits<14> Encoding; 823 let Encoding{13-11} = op1; 824 let Encoding{10-7} = crn; 825 let Encoding{6-3} = crm; 826 let Encoding{2-0} = op2; 827 bit NeedsReg = needsreg; 828 list<string> Requires = []; 829 list<string> ExtraRequires = []; 830 code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }]; 831} 832 833def TLBITable : GenericTable { 834 let FilterClass = "TLBIEntry"; 835 let CppTypeName = "TLBI"; 836 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"]; 837 838 let PrimaryKey = ["Encoding"]; 839 let PrimaryKeyName = "lookupTLBIByEncoding"; 840} 841 842def lookupTLBIByName : SearchIndex { 843 let Table = TLBITable; 844 let Key = ["Name"]; 845} 846 847multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, 848 bits<3> op2, bit needsreg = 1> { 849 def : TLBIEntry<name, op1, crn, crm, op2, needsreg>; 850 def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> { 851 let Encoding{7} = 1; 852 let ExtraRequires = ["AArch64::FeatureXS"]; 853 } 854} 855 856defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>; 857defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>; 858defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>; 859defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>; 860defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>; 861defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>; 862defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>; 863defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>; 864defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>; 865defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>; 866defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>; 867defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>; 868defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>; 869defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>; 870defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>; 871defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>; 872defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>; 873defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>; 874defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>; 875defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>; 876defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>; 877defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>; 878defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>; 879defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>; 880defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>; 881defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>; 882defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>; 883defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>; 884defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>; 885defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; 886defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; 887defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; 888 889// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI) 890let Requires = ["AArch64::FeatureTLB_RMI"] in { 891// Armv8.4-A Outer Sharable TLB Maintenance instructions: 892// op1 CRn CRm op2 893defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; 894defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; 895defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>; 896defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>; 897defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>; 898defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>; 899defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>; 900defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>; 901defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>; 902defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>; 903defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>; 904defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>; 905defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>; 906defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>; 907defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>; 908defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>; 909 910// Armv8.4-A TLB Range Maintenance instructions: 911// op1 CRn CRm op2 912defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>; 913defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>; 914defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>; 915defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>; 916defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>; 917defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>; 918defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>; 919defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>; 920defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>; 921defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>; 922defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>; 923defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>; 924defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>; 925defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>; 926defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>; 927defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>; 928defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>; 929defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>; 930defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>; 931defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>; 932defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>; 933defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>; 934defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>; 935defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>; 936defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>; 937defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>; 938defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; 939defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; 940defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; 941defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; 942} //FeatureTLB_RMI 943 944// Armv9-A Realm Management Extention TLBI Instructions 945let Requires = ["AArch64::FeatureRME"] in { 946defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>; 947defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>; 948defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>; 949defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>; 950} 951 952// Armv9.5-A TLBI VMALL for Dirty State 953let Requires = ["AArch64::FeatureTLBIW"] in { 954// op1, CRn, CRm, op2, needsreg 955defm : TLBI<"VMALLWS2E1", 0b100, 0b1000, 0b0110, 0b010, 0>; 956defm : TLBI<"VMALLWS2E1IS", 0b100, 0b1000, 0b0010, 0b010, 0>; 957defm : TLBI<"VMALLWS2E1OS", 0b100, 0b1000, 0b0101, 0b010, 0>; 958} 959 960//===----------------------------------------------------------------------===// 961// MRS/MSR (system register read/write) instruction options. 962//===----------------------------------------------------------------------===// 963 964class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 965 bits<3> op2> { 966 string Name = name; 967 bits<16> Encoding; 968 let Encoding{15-14} = op0; 969 let Encoding{13-11} = op1; 970 let Encoding{10-7} = crn; 971 let Encoding{6-3} = crm; 972 let Encoding{2-0} = op2; 973 bit Readable = ?; 974 bit Writeable = ?; 975 code Requires = [{ {} }]; 976} 977 978def SysRegValues : GenericEnum { 979 let FilterClass = "SysReg"; 980 let NameField = "Name"; 981 let ValueField = "Encoding"; 982} 983 984def SysRegsList : GenericTable { 985 let FilterClass = "SysReg"; 986 let Fields = ["Name", "Encoding", "Readable", "Writeable", "Requires"]; 987 988 let PrimaryKey = ["Encoding"]; 989 let PrimaryKeyName = "lookupSysRegByEncoding"; 990 let PrimaryKeyReturnRange = true; 991} 992 993def lookupSysRegByName : SearchIndex { 994 let Table = SysRegsList; 995 let Key = ["Name"]; 996} 997 998class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 999 bits<3> op2> 1000 : SysReg<name, op0, op1, crn, crm, op2> { 1001 let Readable = 1; 1002 let Writeable = 1; 1003} 1004 1005class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 1006 bits<3> op2> 1007 : SysReg<name, op0, op1, crn, crm, op2> { 1008 let Readable = 1; 1009 let Writeable = 0; 1010} 1011 1012class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 1013 bits<3> op2> 1014 : SysReg<name, op0, op1, crn, crm, op2> { 1015 let Readable = 0; 1016 let Writeable = 1; 1017} 1018 1019//===---------------------- 1020// Read-only regs 1021//===---------------------- 1022 1023// Op0 Op1 CRn CRm Op2 1024def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; 1025def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 1026def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; 1027def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; 1028def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 1029def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; 1030def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; 1031def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; 1032def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; 1033def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; 1034 1035//v8.3 CCIDX - extending the CCsIDr number of sets 1036def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { 1037 let Requires = [{ {AArch64::FeatureCCIDX} }]; 1038} 1039def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; 1040def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; 1041def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>; 1042def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>; 1043def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>; 1044def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>; 1045def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>; 1046def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>; 1047def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> { 1048 let Requires = [{ {AArch64::FeatureSpecRestrict} }]; 1049} 1050def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; 1051def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>; 1052def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; 1053def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; 1054def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; 1055def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>; 1056def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>; 1057def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>; 1058def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>; 1059def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; 1060def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>; 1061def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>; 1062def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>; 1063def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> { 1064 let Requires = [{ {AArch64::HasV8_2aOps} }]; 1065} 1066def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>; 1067def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; 1068def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>; 1069def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; 1070def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; 1071def : ROSysReg<"ID_AA64DFR2_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b010>; 1072def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; 1073def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; 1074def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; 1075def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; 1076def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>; 1077def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>; 1078def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; 1079def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; 1080def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>; 1081def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>; 1082def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>; 1083def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; 1084def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; 1085def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; 1086def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; 1087def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; 1088def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; 1089def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; 1090def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 1091def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 1092def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; 1093def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>; 1094 1095// Trace registers 1096// Op0 Op1 CRn CRm Op2 1097def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; 1098def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; 1099def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; 1100def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; 1101def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; 1102def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>; 1103def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>; 1104def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>; 1105def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>; 1106def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>; 1107def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>; 1108def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>; 1109def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>; 1110def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; 1111def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>; 1112def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>; 1113def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>; 1114def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>; 1115def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>; 1116def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>; 1117def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; 1118def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>; 1119def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>; 1120def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>; 1121def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>; 1122def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>; 1123def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>; 1124def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>; 1125def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>; 1126def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>; 1127def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>; 1128def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>; 1129def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>; 1130def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>; 1131def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; 1132def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>; 1133 1134// GICv3 registers 1135// Op0 Op1 CRn CRm Op2 1136def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>; 1137def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>; 1138def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>; 1139def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; 1140def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; 1141def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; 1142def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; 1143def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; 1144 1145// SVE control registers 1146// Op0 Op1 CRn CRm Op2 1147let Requires = [{ {AArch64::FeatureSVE} }] in { 1148def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; 1149} 1150 1151// v8.1a "Limited Ordering Regions" extension-specific system register 1152// Op0 Op1 CRn CRm Op2 1153let Requires = [{ {AArch64::FeatureLOR} }] in 1154def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; 1155 1156// v8.2a "RAS extension" registers 1157// Op0 Op1 CRn CRm Op2 1158let Requires = [{ {AArch64::FeatureRAS} }] in { 1159def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>; 1160def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>; 1161} 1162 1163// v8.5a "random number" registers 1164// Op0 Op1 CRn CRm Op2 1165let Requires = [{ {AArch64::FeatureRandGen} }] in { 1166def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>; 1167def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>; 1168} 1169 1170// v8.5a Software Context Number registers 1171let Requires = [{ {AArch64::FeatureSpecRestrict} }] in { 1172def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>; 1173def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>; 1174def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>; 1175def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>; 1176def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>; 1177} 1178 1179// v9a Realm Management Extension registers 1180let Requires = [{ {AArch64::FeatureRME} }] in { 1181def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>; 1182def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>; 1183} 1184// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter 1185// is unconditional so this register has to be too. 1186def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>; 1187 1188// v9a Memory Encryption Contexts Extension registers 1189let Requires = [{ {AArch64::FeatureMEC} }] in { 1190def : ROSysReg<"MECIDR_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b111>; 1191def : RWSysReg<"MECID_P0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b000>; 1192def : RWSysReg<"MECID_A0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b001>; 1193def : RWSysReg<"MECID_P1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b010>; 1194def : RWSysReg<"MECID_A1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b011>; 1195def : RWSysReg<"VMECID_P_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b000>; 1196def : RWSysReg<"VMECID_A_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b001>; 1197def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>; 1198} 1199 1200// v9-a Scalable Matrix Extension (SME) registers 1201// Op0 Op1 CRn CRm Op2 1202let Requires = [{ {AArch64::FeatureSME} }] in { 1203def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>; 1204} 1205 1206//===---------------------- 1207// Write-only regs 1208//===---------------------- 1209 1210// Op0 Op1 CRn CRm Op2 1211def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; 1212def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>; 1213def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>; 1214 1215// Trace Registers 1216// Op0 Op1 CRn CRm Op2 1217def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>; 1218def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>; 1219 1220// GICv3 registers 1221// Op0 Op1 CRn CRm Op2 1222def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>; 1223def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>; 1224def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>; 1225def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>; 1226def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>; 1227def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>; 1228 1229//===---------------------- 1230// Read-write regs 1231//===---------------------- 1232 1233// Op0 Op1 CRn CRm Op2 1234def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; 1235def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; 1236def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; 1237def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>; 1238def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>; 1239def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; 1240def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; 1241def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; 1242foreach n = 0-15 in { 1243 defvar nb = !cast<bits<4>>(n); 1244 // Op0 Op1 CRn CRm Op2 1245 def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>; 1246 def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>; 1247 def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>; 1248 def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>; 1249} 1250// Op0 Op1 CRn CRm Op2 1251def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; 1252def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; 1253def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; 1254def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>; 1255def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>; 1256def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>; 1257def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>; 1258def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>; 1259def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>; 1260def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>; 1261def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>; 1262def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>; 1263def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>; 1264def : RWSysReg<"ACTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b001>; 1265def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>; 1266def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>; 1267def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>; 1268def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> { 1269 let Requires = [{ {AArch64::FeatureHCX} }]; 1270} 1271def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>; 1272def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>; 1273def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>; 1274def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>; 1275def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>; 1276def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>; 1277def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; 1278def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; 1279def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; 1280def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; 1281 1282let Requires = [{ {AArch64::FeatureEL2VMSA} }] in { 1283def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>; 1284def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; 1285} 1286 1287def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; 1288def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; 1289def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; 1290def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; 1291def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; 1292def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; 1293def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; 1294def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>; 1295def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>; 1296def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>; 1297def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>; 1298def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>; 1299def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>; 1300def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>; 1301def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; 1302def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>; 1303def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>; 1304def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>; 1305def : ROSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>; 1306def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; 1307def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; 1308def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; 1309def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; 1310let Requires = [{ {AArch64::FeatureFPARMv8} }] in { 1311def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; 1312def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; 1313} 1314def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; 1315def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; 1316def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; 1317def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>; 1318def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>; 1319def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>; 1320def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>; 1321def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>; 1322def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>; 1323def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>; 1324def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>; 1325def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>; 1326def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>; 1327def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>; 1328def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>; 1329def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>; 1330def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>; 1331def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>; 1332def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>; 1333def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>; 1334def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>; 1335def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; 1336def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; 1337def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; 1338def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; 1339def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; 1340def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; 1341def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; 1342def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; 1343def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; 1344def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; 1345def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; 1346def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; 1347def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; 1348def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; 1349def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; 1350def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; 1351def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; 1352def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; 1353def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>; 1354def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>; 1355def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>; 1356def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>; 1357def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>; 1358def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>; 1359def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>; 1360def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>; 1361def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>; 1362def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>; 1363def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>; 1364def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>; 1365def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>; 1366def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>; 1367def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>; 1368def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>; 1369def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>; 1370def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>; 1371def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>; 1372def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>; 1373def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>; 1374def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>; 1375def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>; 1376def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>; 1377def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>; 1378def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>; 1379def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>; 1380def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>; 1381def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>; 1382def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>; 1383def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>; 1384def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>; 1385def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>; 1386def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>; 1387def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>; 1388def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>; 1389def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>; 1390def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>; 1391def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>; 1392def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>; 1393def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>; 1394def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>; 1395def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>; 1396def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>; 1397def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>; 1398def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>; 1399def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>; 1400def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>; 1401def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>; 1402def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>; 1403def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>; 1404def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>; 1405def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>; 1406def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>; 1407def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>; 1408def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>; 1409def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>; 1410def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>; 1411def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>; 1412def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>; 1413def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>; 1414def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>; 1415def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>; 1416def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>; 1417def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>; 1418def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>; 1419def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>; 1420def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>; 1421def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>; 1422def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>; 1423def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>; 1424def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>; 1425def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>; 1426def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>; 1427def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>; 1428def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>; 1429def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>; 1430def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>; 1431def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>; 1432def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>; 1433def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>; 1434def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>; 1435def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>; 1436def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>; 1437def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>; 1438def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>; 1439def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>; 1440def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>; 1441 1442// Trace registers 1443// Op0 Op1 CRn CRm Op2 1444def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>; 1445def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>; 1446def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>; 1447def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>; 1448def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>; 1449def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>; 1450def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>; 1451def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>; 1452def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>; 1453def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>; 1454def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>; 1455def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>; 1456def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>; 1457def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>; 1458def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>; 1459def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>; 1460def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>; 1461def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>; 1462def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>; 1463def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>; 1464def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>; 1465def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>; 1466def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; 1467def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; 1468def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; 1469def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1470def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; 1471def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; 1472def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; 1473def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>; 1474def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>; 1475def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>; 1476def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>; 1477def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>; 1478def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>; 1479def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>; 1480def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>; 1481def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>; 1482def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>; 1483def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>; 1484def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>; 1485def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>; 1486def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>; 1487def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>; 1488def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>; 1489def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>; 1490def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>; 1491def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>; 1492def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>; 1493def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>; 1494def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>; 1495def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>; 1496def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>; 1497def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>; 1498def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>; 1499def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>; 1500def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>; 1501def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>; 1502def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>; 1503def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>; 1504def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>; 1505def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>; 1506def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>; 1507def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>; 1508def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>; 1509def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>; 1510def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>; 1511def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>; 1512def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>; 1513def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>; 1514def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>; 1515def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>; 1516def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>; 1517def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>; 1518def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>; 1519def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>; 1520def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>; 1521def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>; 1522def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>; 1523def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>; 1524def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>; 1525def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>; 1526def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>; 1527def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>; 1528def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>; 1529def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>; 1530def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>; 1531def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>; 1532def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>; 1533def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>; 1534def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>; 1535def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>; 1536def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>; 1537def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>; 1538def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>; 1539def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>; 1540def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>; 1541def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>; 1542def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>; 1543def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>; 1544def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>; 1545def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>; 1546def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>; 1547def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>; 1548def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>; 1549def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>; 1550def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>; 1551def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>; 1552def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>; 1553def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>; 1554def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>; 1555def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>; 1556def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>; 1557def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>; 1558def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>; 1559def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>; 1560def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>; 1561def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>; 1562def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>; 1563def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>; 1564def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>; 1565def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>; 1566def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>; 1567def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>; 1568def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>; 1569def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>; 1570def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>; 1571def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>; 1572def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>; 1573def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>; 1574def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>; 1575def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>; 1576def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>; 1577def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>; 1578def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>; 1579def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>; 1580def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>; 1581def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>; 1582def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>; 1583def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>; 1584def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>; 1585def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>; 1586def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>; 1587def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>; 1588def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>; 1589def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>; 1590def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>; 1591def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>; 1592def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>; 1593def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>; 1594def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>; 1595def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>; 1596def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>; 1597def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>; 1598def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>; 1599def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>; 1600def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>; 1601def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>; 1602def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>; 1603def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>; 1604def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>; 1605def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>; 1606def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>; 1607def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>; 1608def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>; 1609def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>; 1610def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>; 1611def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>; 1612def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>; 1613def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>; 1614def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>; 1615def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>; 1616 1617// GICv3 registers 1618// Op0 Op1 CRn CRm Op2 1619def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>; 1620def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>; 1621def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>; 1622def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>; 1623def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>; 1624def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>; 1625def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>; 1626def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>; 1627def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>; 1628def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>; 1629def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>; 1630def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>; 1631def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>; 1632def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>; 1633def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>; 1634def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>; 1635def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>; 1636def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>; 1637def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>; 1638def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>; 1639def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>; 1640def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>; 1641def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>; 1642def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>; 1643def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; 1644def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>; 1645def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>; 1646def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>; 1647def : ROSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>; 1648def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>; 1649def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>; 1650def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>; 1651def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>; 1652def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>; 1653def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>; 1654def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>; 1655def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>; 1656def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>; 1657def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>; 1658def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>; 1659def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>; 1660def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>; 1661def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>; 1662def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>; 1663def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; 1664def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; 1665 1666// v8r system registers 1667let Requires = [{ {AArch64::HasV8_0rOps} }] in { 1668//Virtualization System Control Register 1669// Op0 Op1 CRn CRm Op2 1670def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>; 1671 1672//MPU Type Register 1673// Op0 Op1 CRn CRm Op2 1674def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>; 1675def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>; 1676 1677//Protection Region Enable Register 1678// Op0 Op1 CRn CRm Op2 1679def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>; 1680def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>; 1681 1682//Protection Region Selection Register 1683// Op0 Op1 CRn CRm Op2 1684def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>; 1685def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>; 1686 1687//Protection Region Base Address Register 1688// Op0 Op1 CRn CRm Op2 1689def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>; 1690def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>; 1691 1692//Protection Region Limit Address Register 1693// Op0 Op1 CRn CRm Op2 1694def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>; 1695def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>; 1696 1697foreach n = 1-15 in { 1698foreach x = 1-2 in { 1699//Direct acces to Protection Region Base Address Register for n th MPU region 1700 def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x), 1701 0b11, 0b000, 0b0110, 0b1000, 0b000>{ 1702 let Encoding{5-2} = n; 1703 let Encoding{13} = !add(x,-1); 1704 } 1705 1706 def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x), 1707 0b11, 0b000, 0b0110, 0b1000, 0b001>{ 1708 let Encoding{5-2} = n; 1709 let Encoding{13} = !add(x,-1); 1710 } 1711} //foreach x = 1-2 in 1712} //foreach n = 1-15 in 1713} //let Requires = [{ {AArch64::HasV8_0rOps} }] in 1714 1715// v8.1a "Privileged Access Never" extension-specific system registers 1716let Requires = [{ {AArch64::FeaturePAN} }] in 1717def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; 1718 1719// v8.1a "Limited Ordering Regions" extension-specific system registers 1720// Op0 Op1 CRn CRm Op2 1721let Requires = [{ {AArch64::FeatureLOR} }] in { 1722def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; 1723def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; 1724def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; 1725def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; 1726} 1727 1728// v8.1a "Virtualization Host extensions" system registers 1729// Op0 Op1 CRn CRm Op2 1730let Requires = [{ {AArch64::FeatureVH} }] in { 1731def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; 1732def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; 1733def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>; 1734def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>; 1735def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>; 1736def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>; 1737def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>; 1738def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>; 1739def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>; 1740def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>; 1741def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>; 1742def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>; 1743def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>; 1744def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>; 1745def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>; 1746def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>; 1747def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>; 1748def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>; 1749def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>; 1750def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>; 1751def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>; 1752def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>; 1753def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>; 1754def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>; 1755def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>; 1756def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; 1757let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in { 1758 def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; 1759} 1760} 1761// v8.2a registers 1762// Op0 Op1 CRn CRm Op2 1763let Requires = [{ {AArch64::FeaturePsUAO} }] in 1764def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; 1765 1766// v8.2a "Statistical Profiling extension" registers 1767// Op0 Op1 CRn CRm Op2 1768let Requires = [{ {AArch64::FeatureSPE} }] in { 1769def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>; 1770def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>; 1771def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>; 1772def : ROSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>; 1773def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>; 1774def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>; 1775def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>; 1776def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>; 1777def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; 1778def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>; 1779def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>; 1780def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>; 1781def : ROSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>; 1782} 1783 1784// v8.2a "RAS extension" registers 1785// Op0 Op1 CRn CRm Op2 1786let Requires = [{ {AArch64::FeatureRAS} }] in { 1787def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>; 1788def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>; 1789def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>; 1790def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>; 1791def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>; 1792def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>; 1793def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>; 1794def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>; 1795def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; 1796} 1797 1798// v8.3a "Pointer authentication extension" registers 1799// Op0 Op1 CRn CRm Op2 1800let Requires = [{ {AArch64::FeaturePAuth} }] in { 1801def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; 1802def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; 1803def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; 1804def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>; 1805def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>; 1806def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>; 1807def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>; 1808def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>; 1809def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; 1810def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; 1811} 1812 1813// v8.4 "Secure Exception Level 2 extension" 1814let Requires = [{ {AArch64::FeatureSEL2} }] in { 1815// v8.4a "Virtualization secure second stage translation" registers 1816// Op0 Op1 CRn CRm Op2 1817def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; 1818def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> { 1819 let Requires = [{ {AArch64::HasV8_0aOps} }]; 1820} 1821 1822// v8.4a "Virtualization timer" registers 1823// Op0 Op1 CRn CRm Op2 1824def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>; 1825def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>; 1826def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>; 1827def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>; 1828def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>; 1829def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; 1830 1831// v8.4a "Virtualization debug state" registers 1832// Op0 Op1 CRn CRm Op2 1833def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; 1834} // FeatureSEL2 1835 1836// v8.4a RAS registers 1837// Op0 Op1 CRn CRm Op2 1838def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; 1839def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; 1840def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; 1841def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; 1842def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; 1843 1844// v8.4a MPAM registers 1845// Op0 Op1 CRn CRm Op2 1846let Requires = [{ {AArch64::FeatureMPAM} }] in { 1847def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>; 1848def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>; 1849def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>; 1850def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>; 1851def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>; 1852def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>; 1853def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>; 1854def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>; 1855def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>; 1856def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>; 1857def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>; 1858def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>; 1859def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>; 1860def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>; 1861def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>; 1862def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>; 1863} //FeatureMPAM 1864 1865// v8.4a Activity Monitor registers 1866// Op0 Op1 CRn CRm Op2 1867let Requires = [{ {AArch64::FeatureAM} }] in { 1868def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>; 1869def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>; 1870def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>; 1871def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>; 1872def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>; 1873def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>; 1874def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>; 1875def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>; 1876def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>; 1877def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>; 1878def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>; 1879def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>; 1880def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>; 1881def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>; 1882def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>; 1883def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>; 1884def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>; 1885def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>; 1886def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>; 1887def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>; 1888def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>; 1889def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>; 1890def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>; 1891def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>; 1892def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>; 1893def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>; 1894def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>; 1895def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>; 1896def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>; 1897def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>; 1898def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>; 1899def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>; 1900def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>; 1901def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>; 1902def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>; 1903def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>; 1904def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>; 1905def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>; 1906def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>; 1907def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>; 1908def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>; 1909def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>; 1910def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>; 1911def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>; 1912def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>; 1913def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>; 1914def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>; 1915def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; 1916} //FeatureAM 1917 1918// v8.4a Trace Extension registers 1919// 1920// Please note that the 8.4 spec also defines these registers: 1921// TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3, 1922// but they are already defined above. 1923// 1924// Op0 Op1 CRn CRm Op2 1925let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in { 1926def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>; 1927def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>; 1928def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>; 1929} //FeatureTRACEV8_4 1930 1931// v8.4a Timing insensitivity of data processing instructions 1932// DIT: Data Independent Timing instructions 1933// Op0 Op1 CRn CRm Op2 1934let Requires = [{ {AArch64::FeatureDIT} }] in { 1935def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>; 1936} //FeatureDIT 1937 1938// v8.4a Enhanced Support for Nested Virtualization 1939// Op0 Op1 CRn CRm Op2 1940let Requires = [{ {AArch64::FeatureNV} }] in { 1941def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; 1942} //FeatureNV 1943 1944// SVE control registers 1945// Op0 Op1 CRn CRm Op2 1946let Requires = [{ {AArch64::FeatureSVE} }] in { 1947def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; 1948def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; 1949def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; 1950def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; 1951} 1952 1953// V8.5a Spectre mitigation SSBS register 1954// Op0 Op1 CRn CRm Op2 1955let Requires = [{ {AArch64::FeatureSSBS} }] in 1956def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>; 1957 1958// v8.5a Memory Tagging Extension 1959// Op0 Op1 CRn CRm Op2 1960let Requires = [{ {AArch64::FeatureMTE} }] in { 1961def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>; 1962def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>; 1963def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>; 1964def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>; 1965def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>; 1966def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>; 1967def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>; 1968def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>; 1969def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; 1970} // HasMTE 1971 1972// Embedded Trace Extension R/W System registers 1973let Requires = [{ {AArch64::FeatureETE} }] in { 1974// Name Op0 Op1 CRn CRm Op2 1975def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; 1976// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR 1977def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; 1978def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>; 1979def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>; 1980def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>; 1981} // FeatureETE 1982 1983// Trace Buffer Extension System registers 1984let Requires = [{ {AArch64::FeatureTRBE} }] in { 1985// Name Op0 Op1 CRn CRm Op2 1986def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>; 1987def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>; 1988def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>; 1989def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>; 1990def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>; 1991def : RWSysReg<"TRBMPAM_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b101>; 1992def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>; 1993def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>; 1994} // FeatureTRBE 1995 1996 1997// v8.6a Activity Monitors Virtualization Support 1998let Requires = [{ {AArch64::FeatureAMVS} }] in { 1999// Name Op0 Op1 CRn CRm Op2 2000def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>; 2001foreach n = 0-15 in { 2002 foreach x = 0-1 in { 2003 def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2", 2004 0b11, 0b100, 0b1101, 0b1000, 0b000>{ 2005 let Encoding{4} = x; 2006 let Encoding{3-0} = n; 2007 } 2008 } 2009} 2010} 2011 2012// v8.6a Fine Grained Virtualization Traps 2013// Op0 Op1 CRn CRm Op2 2014let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in { 2015def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>; 2016def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>; 2017def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>; 2018def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>; 2019def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>; 2020def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>; 2021 2022// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2) 2023// Op0 Op1 CRn CRm Op2 2024def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>; 2025def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>; 2026def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>; 2027def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>; 2028def : RWSysReg<"HFGITR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b111>; 2029} 2030 2031// v8.6a Enhanced Counter Virtualization 2032// Op0 Op1 CRn CRm Op2 2033let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in { 2034def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>; 2035def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>; 2036def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>; 2037def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>; 2038def : ROSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>; 2039def : ROSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>; 2040} 2041 2042// v8.7a LD64B/ST64B Accelerator Extension system register 2043let Requires = [{ {AArch64::FeatureLS64} }] in 2044def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>; 2045 2046// Branch Record Buffer system registers 2047let Requires = [{ {AArch64::FeatureBRBE} }] in { 2048def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>; 2049def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>; 2050def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>; 2051def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>; 2052def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>; 2053def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>; 2054def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>; 2055def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>; 2056def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>; 2057foreach n = 0-31 in { 2058 defvar nb = !cast<bits<5>>(n); 2059 def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>; 2060 def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>; 2061 def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>; 2062} 2063} 2064 2065// Statistical Profiling Extension system register 2066let Requires = [{ {AArch64::FeatureSPE_EEF} }] in 2067def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>; 2068 2069// Scalable Matrix Extension (SME) 2070// Op0 Op1 CRn CRm Op2 2071let Requires = [{ {AArch64::FeatureSME} }] in { 2072def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>; 2073def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>; 2074def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>; 2075def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>; 2076def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>; 2077def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>; 2078def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>; 2079def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>; 2080def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>; 2081} // HasSME 2082 2083// v8.4a MPAM and SME registers 2084// Op0 Op1 CRn CRm Op2 2085let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in { 2086def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>; 2087} // HasMPAM, HasSME 2088 2089// v8.8a Non-Maskable Interrupts 2090let Requires = [{ {AArch64::FeatureNMI} }] in { 2091 // Op0 Op1 CRn CRm Op2 2092 def : RWSysReg<"ALLINT", 0b11, 0b000, 0b0100, 0b0011, 0b000>; 2093 def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI 2094} 2095 2096// v9.4a Guarded Control Stack Extension (GCS) 2097// Op0 Op1 CRn CRm Op2 2098def : RWSysReg<"GCSCR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b000>; 2099def : RWSysReg<"GCSPR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b001>; 2100def : RWSysReg<"GCSCRE0_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b010>; 2101def : RWSysReg<"GCSPR_EL0", 0b11, 0b011, 0b0010, 0b0101, 0b001>; 2102def : RWSysReg<"GCSCR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b000>; 2103def : RWSysReg<"GCSPR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b001>; 2104def : RWSysReg<"GCSCR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b000>; 2105def : RWSysReg<"GCSPR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b001>; 2106def : RWSysReg<"GCSCR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b000>; 2107def : RWSysReg<"GCSPR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b001>; 2108 2109// v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE) 2110// Op0 Op1 CRn CRm Op2 2111def : RWSysReg<"AMAIR2_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b001>; 2112def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>; 2113def : RWSysReg<"AMAIR2_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b001>; 2114def : RWSysReg<"AMAIR2_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b001>; 2115def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>; 2116def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>; 2117def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>; 2118def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>; 2119 2120// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE) 2121// Op0 Op1 CRn CRm Op2 2122def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>; 2123def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>; 2124def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>; 2125def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>; 2126def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>; 2127def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>; 2128def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>; 2129 2130// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE) 2131// Op0 Op1 CRn CRm Op2 2132def : RWSysReg<"S2PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b101>; 2133 2134// v8.9a/v9.4a Stage 1 Permission Overlay Extension (FEAT_S1POE) 2135// Op0 Op1 CRn CRm Op2 2136def : RWSysReg<"POR_EL0", 0b11, 0b011, 0b1010, 0b0010, 0b100>; 2137def : RWSysReg<"POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b100>; 2138def : RWSysReg<"POR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b100>; 2139def : RWSysReg<"POR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b100>; 2140def : RWSysReg<"POR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b100>; 2141 2142// v8.9a/v9.4a Stage 2 Permission Overlay Extension (FEAT_S2POE) 2143// Op0 Op1 CRn CRm Op2 2144def : RWSysReg<"S2POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b101>; 2145 2146// v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2) 2147// Op0 Op1 CRn CRm Op2 2148def : RWSysReg<"SCTLR2_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b011>; 2149def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>; 2150def : RWSysReg<"SCTLR2_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b011>; 2151def : RWSysReg<"SCTLR2_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b011>; 2152 2153// v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2) 2154// Op0 Op1 CRn CRm Op2 2155def : RWSysReg<"TCR2_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b011>; 2156def : RWSysReg<"TCR2_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b011>; 2157def : RWSysReg<"TCR2_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b011>; 2158 2159// v8.9a/9.4a Translation Hardening Extension (FEAT_THE) 2160// Op0 Op1 CRn CRm Op2 2161let Requires = [{ {AArch64::FeatureTHE} }] in { 2162def : RWSysReg<"RCWMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b110>; 2163def : RWSysReg<"RCWSMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b011>; 2164} 2165 2166// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9) 2167// Op0 Op1 CRn CRm Op2 2168def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>; 2169 2170// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9) 2171// Op0 Op1 CRn CRm Op2 2172def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>; 2173 2174// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS) 2175// Op0 Op1 CRn CRm Op2 2176def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>; 2177def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>; 2178def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>; 2179foreach n = 0-30 in { 2180 defvar nb = !cast<bits<5>>(n); 2181 def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>; 2182} 2183 2184// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR) 2185// Op0 Op1 CRn CRm Op2 2186def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>; 2187def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>; 2188 2189// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR) 2190// Op0 Op1 CRn CRm Op2 2191def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>; 2192 2193// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP) 2194// Op0 Op1 CRn CRm Op2 2195def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>; 2196def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>; 2197 2198// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU) 2199// Op0 Op1 CRn CRm Op2 2200def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>; 2201def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>; 2202def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>; 2203def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>; 2204def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>; 2205def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>; 2206def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>; 2207def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>; 2208def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>; 2209foreach n = 0-15 in { 2210 defvar nb = !cast<bits<4>>(n); 2211 // Op0 Op1 CRn CRm Op2 2212 def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>; 2213 def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>; 2214 def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>; 2215 def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>; 2216} 2217// Op0 Op1 CRn CRm Op2 2218def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>; 2219def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>; 2220def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>; 2221def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>; 2222def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>; 2223def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>; 2224def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>; 2225def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>; 2226def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>; 2227def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>; 2228def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>; 2229 2230// v8.9a/9.4a Instrumentation Extension (FEAT_ITE) 2231// Op0 Op1 CRn CRm Op2 2232let Requires = [{ {AArch64::FeatureITE} }] in { 2233def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>; 2234def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>; 2235def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>; 2236def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>; 2237} 2238 2239// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS) 2240// Op0 Op1 CRn CRm Op2 2241def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>; 2242 2243// v8.9a/9.4a RASv2 (FEAT_RASv2) 2244// Op0 Op1 CRn CRm Op2 2245let Requires = [{ {AArch64::FeatureRASv2} }] in 2246def : ROSysReg<"ERXGSR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b010>; 2247 2248// v8.9a/9.4a Physical Fault Address (FEAT_PFAR) 2249// Op0 Op1 CRn CRm Op2 2250def : RWSysReg<"PFAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b101>; 2251def : RWSysReg<"PFAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b101>; 2252def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>; 2253 2254// v9.4a Exception-based event profiling (FEAT_EBEP) 2255// Op0 Op1 CRn CRm Op2 2256def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>; 2257 2258// 2023 ISA Extension 2259// AArch64 Floating-point Mode Register controls behaviors of the FP8 2260// instructions (FEAT_FPMR) 2261// Op0 Op1 CRn CRm Op2 2262def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>; 2263def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>; 2264 2265// v9.5a Software Stepping Enhancements (FEAT_STEP2) 2266// Op0 Op1 CRn CRm Op2 2267def : RWSysReg<"MDSTEPOP_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b010>; 2268 2269// v9.5a System PMU zero register (FEAT_SPMU2) 2270// Op0 Op1 CRn CRm Op2 2271def : WOSysReg<"SPMZR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b100>; 2272 2273// v9.5a Delegated SError exceptions for EL3 (FEAT_E3DSE) 2274// Op0 Op1 CRn CRm Op2 2275def : RWSysReg<"VDISR_EL3", 0b11, 0b110, 0b1100, 0b0001, 0b001>; 2276def : RWSysReg<"VSESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b011>; 2277 2278// v9.5a Hardware Dirty State Tracking Structure (FEAT_HDBSS) 2279// Op0 Op1 CRn CRm Op2 2280def : RWSysReg<"HDBSSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b010>; 2281def : RWSysReg<"HDBSSPROD_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b011>; 2282 2283// v9.5a Hardware Accelerator for Cleaning Dirty State (FEAT_HACDBS) 2284// Op0 Op1 CRn CRm Op2 2285def : RWSysReg<"HACDBSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b100>; 2286def : RWSysReg<"HACDBSCONS_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b101>; 2287 2288// v9.5a Fine Grained Write Trap EL3 (FEAT_FGWTE3) 2289// Op0 Op1 CRn CRm Op2 2290def : RWSysReg<"FGWTE3_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b101>; 2291 2292// v9.6a Memory partitioning and monitoring (FEAT_MPAM) registers 2293// Op0 Op1 CRn CRm Op2 2294def : ROSysReg<"MPAMBWIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b101>; 2295def : RWSysReg<"MPAMBW3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b100>; 2296def : RWSysReg<"MPAMBW2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b100>; 2297def : RWSysReg<"MPAMBW1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b100>; 2298def : RWSysReg<"MPAMBW1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b100>; 2299def : RWSysReg<"MPAMBW0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b101>; 2300def : RWSysReg<"MPAMBWCAP_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b110>; 2301def : RWSysReg<"MPAMBWSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b111>; 2302 2303//===----------------------------------------------------------------------===// 2304// FEAT_SRMASK v9.6a registers 2305//===----------------------------------------------------------------------===// 2306def : RWSysReg<"SCTLRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b000>; 2307def : RWSysReg<"SCTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b000>; 2308def : RWSysReg<"SCTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b000>; 2309def : RWSysReg<"CPACRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b010>; 2310def : RWSysReg<"CPTRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b010>; 2311def : RWSysReg<"CPACRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b010>; 2312def : RWSysReg<"SCTLR2MASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b011>; 2313def : RWSysReg<"SCTLR2MASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b011>; 2314def : RWSysReg<"SCTLR2MASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b011>; 2315def : RWSysReg<"CPACRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b100>; 2316def : RWSysReg<"SCTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b110>; 2317def : RWSysReg<"SCTLR2ALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b111>; 2318def : RWSysReg<"TCRMASK_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b010>; 2319def : RWSysReg<"TCRMASK_EL2", 0b11, 0b100, 0b0010, 0b0111, 0b010>; 2320def : RWSysReg<"TCRMASK_EL12", 0b11, 0b101, 0b0010, 0b0111, 0b010>; 2321def : RWSysReg<"TCR2MASK_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b011>; 2322def : RWSysReg<"TCR2MASK_EL2", 0b11, 0b100, 0b0010, 0b0111, 0b011>; 2323def : RWSysReg<"TCR2MASK_EL12", 0b11, 0b101, 0b0010, 0b0111, 0b011>; 2324def : RWSysReg<"TCRALIAS_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b110>; 2325def : RWSysReg<"TCR2ALIAS_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b111>; 2326def : RWSysReg<"ACTLRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b001>; 2327def : RWSysReg<"ACTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b001>; 2328def : RWSysReg<"ACTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b001>; 2329def : RWSysReg<"ACTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b101>; 2330 2331//===----------------------------------------------------------------------===// 2332// v9.6a PCDPHINT instruction options. 2333//===----------------------------------------------------------------------===// 2334 2335class PHint<bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm, 2336 bits<3> op2, string name> { 2337 string Name = name; 2338 bits<16> Encoding; 2339 let Encoding{15-14} = op0; 2340 let Encoding{13-11} = op1; 2341 let Encoding{10-7} = crn; 2342 let Encoding{6-3} = crm; 2343 let Encoding{2-0} = op2; 2344 code Requires = [{ {} }]; 2345} 2346 2347def PHintValues : GenericEnum { 2348 let FilterClass = "PHint"; 2349 let NameField = "Name"; 2350 let ValueField = "Encoding"; 2351} 2352 2353def PHintsList : GenericTable { 2354 let FilterClass = "PHint"; 2355 let Fields = ["Name", "Encoding", "Requires"]; 2356 2357 let PrimaryKey = ["Encoding"]; 2358 let PrimaryKeyName = "lookupPHintByEncoding"; 2359} 2360 2361def lookupPHintByName : SearchIndex { 2362 let Table = PHintsList; 2363 let Key = ["Name"]; 2364} 2365 2366let Requires = [{ {AArch64::FeaturePCDPHINT} }] in { 2367 def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">; 2368 def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">; 2369} 2370 2371// v9.6a Realm management extension enhancements 2372def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>; 2373 2374// v9.6a Statistical Profiling Extension exception registers (FEAT_SPE_EXC) 2375// Op0 Op1 CRn CRm Op2 2376def : RWSysReg<"PMBMAR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b101>; 2377def : RWSysReg<"PMBSR_EL12", 0b11, 0b101, 0b1001, 0b1010, 0b011>; 2378def : RWSysReg<"PMBSR_EL2", 0b11, 0b100, 0b1001, 0b1010, 0b011>; 2379def : RWSysReg<"PMBSR_EL3", 0b11, 0b110, 0b1001, 0b1010, 0b011>; 2380 2381// v9.6a Trace Buffer Management Events exception registers (FEAT_TRBE_EXC) 2382// Op0 Op1 CRn CRm Op2 2383def : RWSysReg<"TRBSR_EL12", 0b11, 0b101, 0b1001, 0b1011, 0b011>; 2384def : RWSysReg<"TRBSR_EL2", 0b11, 0b100, 0b1001, 0b1011, 0b011>; 2385def : RWSysReg<"TRBSR_EL3", 0b11, 0b110, 0b1001, 0b1011, 0b011>; 2386 2387// v9.6 FEAT_PoPS 2388// 2389let Requires = [{ {AArch64::FeaturePoPS} }] in { 2390def : DC<"CIGDVAPS", 0b000, 0b0111, 0b1111, 0b101>; 2391def : DC<"CIVAPS", 0b000, 0b0111, 0b1111, 0b001>; 2392} 2393