1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// This pass is required to take advantage of the interprocedural register 10 /// allocation infrastructure. 11 /// 12 /// This pass is simple MachineFunction pass which collects register usage 13 /// details by iterating through each physical registers and checking 14 /// MRI::isPhysRegUsed() then creates a RegMask based on this details. 15 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp 16 /// 17 //===----------------------------------------------------------------------===// 18 19 #include "llvm/CodeGen/RegUsageInfoCollector.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/MachinePassManager.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/Passes.h" 26 #include "llvm/CodeGen/RegisterUsageInfo.h" 27 #include "llvm/CodeGen/TargetFrameLowering.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "ip-regalloc" 35 36 STATISTIC(NumCSROpt, 37 "Number of functions optimized for callee saved registers"); 38 39 namespace { 40 41 class RegUsageInfoCollector { 42 PhysicalRegisterUsageInfo &PRUI; 43 44 public: 45 RegUsageInfoCollector(PhysicalRegisterUsageInfo &PRUI) : PRUI(PRUI) {} 46 bool run(MachineFunction &MF); 47 48 // Call getCalleeSaves and then also set the bits for subregs and 49 // fully saved superregs. 50 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF); 51 }; 52 53 class RegUsageInfoCollectorLegacy : public MachineFunctionPass { 54 public: 55 static char ID; 56 RegUsageInfoCollectorLegacy() : MachineFunctionPass(ID) { 57 initializeRegUsageInfoCollectorLegacyPass(*PassRegistry::getPassRegistry()); 58 } 59 60 StringRef getPassName() const override { 61 return "Register Usage Information Collector Pass"; 62 } 63 64 void getAnalysisUsage(AnalysisUsage &AU) const override { 65 AU.addRequired<PhysicalRegisterUsageInfoWrapperLegacy>(); 66 AU.setPreservesAll(); 67 MachineFunctionPass::getAnalysisUsage(AU); 68 } 69 70 bool runOnMachineFunction(MachineFunction &MF) override; 71 }; 72 } // end of anonymous namespace 73 74 char RegUsageInfoCollectorLegacy::ID = 0; 75 76 INITIALIZE_PASS_BEGIN(RegUsageInfoCollectorLegacy, "RegUsageInfoCollector", 77 "Register Usage Information Collector", false, false) 78 INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfoWrapperLegacy) 79 INITIALIZE_PASS_END(RegUsageInfoCollectorLegacy, "RegUsageInfoCollector", 80 "Register Usage Information Collector", false, false) 81 82 FunctionPass *llvm::createRegUsageInfoCollector() { 83 return new RegUsageInfoCollectorLegacy(); 84 } 85 86 // TODO: Move to hook somwehere? 87 88 // Return true if it is useful to track the used registers for IPRA / no CSR 89 // optimizations. This is not useful for entry points, and computing the 90 // register usage information is expensive. 91 static bool isCallableFunction(const MachineFunction &MF) { 92 switch (MF.getFunction().getCallingConv()) { 93 case CallingConv::AMDGPU_VS: 94 case CallingConv::AMDGPU_GS: 95 case CallingConv::AMDGPU_PS: 96 case CallingConv::AMDGPU_CS: 97 case CallingConv::AMDGPU_HS: 98 case CallingConv::AMDGPU_ES: 99 case CallingConv::AMDGPU_LS: 100 case CallingConv::AMDGPU_KERNEL: 101 return false; 102 default: 103 return true; 104 } 105 } 106 107 PreservedAnalyses 108 RegUsageInfoCollectorPass::run(MachineFunction &MF, 109 MachineFunctionAnalysisManager &MFAM) { 110 Module &MFA = *MF.getFunction().getParent(); 111 auto *PRUI = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF) 112 .getCachedResult<PhysicalRegisterUsageAnalysis>(MFA); 113 assert(PRUI && "PhysicalRegisterUsageAnalysis not available"); 114 RegUsageInfoCollector(*PRUI).run(MF); 115 return PreservedAnalyses::all(); 116 } 117 118 bool RegUsageInfoCollectorLegacy::runOnMachineFunction(MachineFunction &MF) { 119 PhysicalRegisterUsageInfo &PRUI = 120 getAnalysis<PhysicalRegisterUsageInfoWrapperLegacy>().getPRUI(); 121 return RegUsageInfoCollector(PRUI).run(MF); 122 } 123 124 bool RegUsageInfoCollector::run(MachineFunction &MF) { 125 MachineRegisterInfo *MRI = &MF.getRegInfo(); 126 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 127 const TargetMachine &TM = MF.getTarget(); 128 129 LLVM_DEBUG( 130 dbgs() 131 << " -------------------- Register Usage Information Collector Pass" 132 << " -------------------- \nFunction Name : " << MF.getName() << '\n'); 133 134 // Analyzing the register usage may be expensive on some targets. 135 if (!isCallableFunction(MF)) { 136 LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n"); 137 return false; 138 } 139 140 // If there are no callers, there's no point in computing more precise 141 // register usage here. 142 if (MF.getFunction().use_empty()) { 143 LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n"); 144 return false; 145 } 146 147 std::vector<uint32_t> RegMask; 148 149 // Compute the size of the bit vector to represent all the registers. 150 // The bit vector is broken into 32-bit chunks, thus takes the ceil of 151 // the number of registers divided by 32 for the size. 152 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); 153 RegMask.resize(RegMaskSize, ~((uint32_t)0)); 154 155 const Function &F = MF.getFunction(); 156 157 PRUI.setTargetMachine(TM); 158 159 LLVM_DEBUG(dbgs() << "Clobbered Registers: "); 160 161 BitVector SavedRegs; 162 computeCalleeSavedRegs(SavedRegs, MF); 163 164 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); 165 auto SetRegAsDefined = [&RegMask](MCRegister Reg) { 166 RegMask[Reg.id() / 32] &= ~(1u << Reg.id() % 32); 167 }; 168 169 // Don't include $noreg in any regmasks. 170 SetRegAsDefined(MCRegister()); 171 172 // Some targets can clobber registers "inside" a call, typically in 173 // linker-generated code. 174 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF)) 175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 176 SetRegAsDefined(*AI); 177 178 // Scan all the physical registers. When a register is defined in the current 179 // function set it and all the aliasing registers as defined in the regmask. 180 // FIXME: Rewrite to use regunits. 181 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 182 // Don't count registers that are saved and restored. 183 if (SavedRegs.test(PReg)) 184 continue; 185 // If a register is defined by an instruction mark it as defined together 186 // with all it's unsaved aliases. 187 if (!MRI->def_empty(PReg)) { 188 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) 189 if (!SavedRegs.test((*AI).id())) 190 SetRegAsDefined(*AI); 191 continue; 192 } 193 // If a register is in the UsedPhysRegsMask set then mark it as defined. 194 // All clobbered aliases will also be in the set, so we can skip setting 195 // as defined all the aliases here. 196 if (UsedPhysRegsMask.test(PReg)) 197 SetRegAsDefined(PReg); 198 } 199 200 if (TargetFrameLowering::isSafeForNoCSROpt(F) && 201 MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) { 202 ++NumCSROpt; 203 LLVM_DEBUG(dbgs() << MF.getName() 204 << " function optimized for not having CSR.\n"); 205 } 206 207 LLVM_DEBUG( 208 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 209 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) 210 dbgs() << printReg(PReg, TRI) << " "; 211 } 212 213 dbgs() << " \n----------------------------------------\n"; 214 ); 215 216 PRUI.storeUpdateRegUsageInfo(F, RegMask); 217 218 return false; 219 } 220 221 void RegUsageInfoCollector:: 222 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { 223 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering(); 224 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 225 226 // Target will return the set of registers that it saves/restores as needed. 227 SavedRegs.clear(); 228 TFI.getCalleeSaves(MF, SavedRegs); 229 if (SavedRegs.none()) 230 return; 231 232 // Insert subregs. 233 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); 234 for (unsigned i = 0; CSRegs[i]; ++i) { 235 MCPhysReg Reg = CSRegs[i]; 236 if (SavedRegs.test(Reg)) { 237 // Save subregisters 238 for (MCPhysReg SR : TRI.subregs(Reg)) 239 SavedRegs.set(SR); 240 } 241 } 242 } 243