1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 //===----------------------------------------------------------------------===// 4 5 #include "llvm/CodeGen/MachineInstr.h" 6 #include "llvm/CodeGen/MachineBasicBlock.h" 7 #include "llvm/Value.h" 8 #include "llvm/Target/TargetMachine.h" 9 #include "llvm/Target/TargetInstrInfo.h" 10 #include "llvm/Target/MRegisterInfo.h" 11 using std::cerr; 12 13 14 // Global variable holding an array of descriptors for machine instructions. 15 // The actual object needs to be created separately for each target machine. 16 // This variable is initialized and reset by class TargetInstrInfo. 17 // 18 // FIXME: This should be a property of the target so that more than one target 19 // at a time can be active... 20 // 21 extern const TargetInstrDescriptor *TargetInstrDescriptors; 22 23 // Constructor for instructions with variable #operands 24 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands) 25 : opCode(OpCode), 26 opCodeFlags(0), 27 operands(numOperands, MachineOperand()), 28 numImplicitRefs(0) 29 { 30 } 31 32 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 33 /// not a resize for them. It is expected that if you use this that you call 34 /// add* methods below to fill up the operands, instead of the Set methods. 35 /// Eventually, the "resizing" ctors will be phased out. 36 /// 37 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands, 38 bool XX, bool YY) 39 : opCode(Opcode), 40 opCodeFlags(0), 41 numImplicitRefs(0) 42 { 43 operands.reserve(numOperands); 44 } 45 46 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 47 /// MachineInstr is created and added to the end of the specified basic block. 48 /// 49 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, 50 unsigned numOperands) 51 : opCode(Opcode), 52 opCodeFlags(0), 53 numImplicitRefs(0) 54 { 55 assert(MBB && "Cannot use inserting ctor with null basic block!"); 56 operands.reserve(numOperands); 57 MBB->push_back(this); // Add instruction to end of basic block! 58 } 59 60 61 // OperandComplete - Return true if it's illegal to add a new operand 62 bool MachineInstr::OperandsComplete() const 63 { 64 int NumOperands = TargetInstrDescriptors[opCode].numOperands; 65 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 66 return true; // Broken: we have all the operands of this instruction! 67 return false; 68 } 69 70 71 // 72 // Support for replacing opcode and operands of a MachineInstr in place. 73 // This only resets the size of the operand vector and initializes it. 74 // The new operands must be set explicitly later. 75 // 76 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) 77 { 78 assert(getNumImplicitRefs() == 0 && 79 "This is probably broken because implicit refs are going to be lost."); 80 opCode = Opcode; 81 operands.clear(); 82 operands.resize(numOperands, MachineOperand()); 83 } 84 85 void 86 MachineInstr::SetMachineOperandVal(unsigned i, 87 MachineOperand::MachineOperandType opType, 88 Value* V, 89 bool isdef, 90 bool isDefAndUse) 91 { 92 assert(i < operands.size()); // may be explicit or implicit op 93 operands[i].opType = opType; 94 operands[i].value = V; 95 operands[i].regNum = -1; 96 97 if (isDefAndUse) 98 operands[i].flags = MachineOperand::DEFUSEFLAG; 99 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 100 operands[i].flags = MachineOperand::DEFONLYFLAG; 101 else 102 operands[i].flags = 0; 103 } 104 105 void 106 MachineInstr::SetMachineOperandConst(unsigned i, 107 MachineOperand::MachineOperandType operandType, 108 int64_t intValue) 109 { 110 assert(i < getNumOperands()); // must be explicit op 111 assert(TargetInstrDescriptors[opCode].resultPos != (int) i && 112 "immed. constant cannot be defined"); 113 114 operands[i].opType = operandType; 115 operands[i].value = NULL; 116 operands[i].immedVal = intValue; 117 operands[i].regNum = -1; 118 operands[i].flags = 0; 119 } 120 121 void 122 MachineInstr::SetMachineOperandReg(unsigned i, 123 int regNum, 124 bool isdef) { 125 assert(i < getNumOperands()); // must be explicit op 126 127 operands[i].opType = MachineOperand::MO_MachineRegister; 128 operands[i].value = NULL; 129 operands[i].regNum = regNum; 130 131 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 132 operands[i].flags = MachineOperand::DEFONLYFLAG; 133 else 134 operands[i].flags = 0; 135 136 insertUsedReg(regNum); 137 } 138 139 void 140 MachineInstr::SetRegForOperand(unsigned i, int regNum) 141 { 142 assert(i < getNumOperands()); // must be explicit op 143 operands[i].setRegForValue(regNum); 144 insertUsedReg(regNum); 145 } 146 147 void 148 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) 149 { 150 getImplicitOp(i).setRegForValue(regNum); 151 insertUsedReg(regNum); 152 } 153 154 155 // Subsitute all occurrences of Value* oldVal with newVal in all operands 156 // and all implicit refs. 157 // If defsOnly == true, substitute defs only. 158 unsigned 159 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 160 bool defsOnly, bool notDefsAndUses, 161 bool& someArgsWereIgnored) 162 { 163 assert((defsOnly || !notDefsAndUses) && 164 "notDefsAndUses is irrelevant if defsOnly == false."); 165 166 unsigned numSubst = 0; 167 168 // Subsitute operands 169 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 170 if (*O == oldVal) 171 if (!defsOnly || 172 notDefsAndUses && O.isDefOnly() || 173 !notDefsAndUses && !O.isUseOnly()) 174 { 175 O.getMachineOperand().value = newVal; 176 ++numSubst; 177 } 178 else 179 someArgsWereIgnored = true; 180 181 // Subsitute implicit refs 182 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 183 if (getImplicitRef(i) == oldVal) 184 if (!defsOnly || 185 notDefsAndUses && getImplicitOp(i).opIsDefOnly() || 186 !notDefsAndUses && !getImplicitOp(i).opIsUse()) 187 { 188 getImplicitOp(i).value = newVal; 189 ++numSubst; 190 } 191 else 192 someArgsWereIgnored = true; 193 194 return numSubst; 195 } 196 197 198 void 199 MachineInstr::dump() const 200 { 201 cerr << " " << *this; 202 } 203 204 static inline std::ostream& 205 OutputValue(std::ostream &os, const Value* val) 206 { 207 os << "(val "; 208 os << (void*) val; // print address always 209 if (val && val->hasName()) 210 os << " " << val->getName() << ")"; // print name also, if available 211 return os; 212 } 213 214 static inline void OutputReg(std::ostream &os, unsigned RegNo, 215 const MRegisterInfo *MRI = 0) { 216 if (MRI) { 217 if (RegNo < MRegisterInfo::FirstVirtualRegister) 218 os << "%" << MRI->get(RegNo).Name; 219 else 220 os << "%reg" << RegNo; 221 } else 222 os << "%mreg(" << RegNo << ")"; 223 } 224 225 static void print(const MachineOperand &MO, std::ostream &OS, 226 const TargetMachine &TM) { 227 const MRegisterInfo *MRI = TM.getRegisterInfo(); 228 bool CloseParen = true; 229 if (MO.opHiBits32()) 230 OS << "%lm("; 231 else if (MO.opLoBits32()) 232 OS << "%lo("; 233 else if (MO.opHiBits64()) 234 OS << "%hh("; 235 else if (MO.opLoBits64()) 236 OS << "%hm("; 237 else 238 CloseParen = false; 239 240 switch (MO.getType()) { 241 case MachineOperand::MO_VirtualRegister: 242 if (MO.getVRegValue()) { 243 OS << "%reg"; 244 OutputValue(OS, MO.getVRegValue()); 245 if (MO.hasAllocatedReg()) 246 OS << "=="; 247 } 248 if (MO.hasAllocatedReg()) 249 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 250 break; 251 case MachineOperand::MO_CCRegister: 252 OS << "%ccreg"; 253 OutputValue(OS, MO.getVRegValue()); 254 if (MO.hasAllocatedReg()) { 255 OS << "=="; 256 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 257 } 258 break; 259 case MachineOperand::MO_MachineRegister: 260 OutputReg(OS, MO.getMachineRegNum(), MRI); 261 break; 262 case MachineOperand::MO_SignExtendedImmed: 263 OS << (long)MO.getImmedValue(); 264 break; 265 case MachineOperand::MO_UnextendedImmed: 266 OS << (long)MO.getImmedValue(); 267 break; 268 case MachineOperand::MO_PCRelativeDisp: { 269 const Value* opVal = MO.getVRegValue(); 270 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 271 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 272 if (opVal->hasName()) 273 OS << opVal->getName(); 274 else 275 OS << (const void*) opVal; 276 OS << ")"; 277 break; 278 } 279 case MachineOperand::MO_MachineBasicBlock: 280 OS << "bb<" 281 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 282 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 283 break; 284 case MachineOperand::MO_FrameIndex: 285 OS << "<fi#" << MO.getFrameIndex() << ">"; 286 break; 287 case MachineOperand::MO_ConstantPoolIndex: 288 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 289 break; 290 case MachineOperand::MO_GlobalAddress: 291 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 292 break; 293 case MachineOperand::MO_ExternalSymbol: 294 OS << "<es:" << MO.getSymbolName() << ">"; 295 break; 296 default: 297 assert(0 && "Unrecognized operand type"); 298 } 299 300 if (CloseParen) 301 OS << ")"; 302 } 303 304 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { 305 unsigned StartOp = 0; 306 307 // Specialize printing if op#0 is definition 308 if (getNumOperands() && 309 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) { 310 ::print(getOperand(0), OS, TM); 311 OS << " = "; 312 ++StartOp; // Don't print this operand again! 313 } 314 OS << TM.getInstrInfo().getName(getOpcode()); 315 316 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 317 const MachineOperand& mop = getOperand(i); 318 if (i != StartOp) 319 OS << ","; 320 OS << " "; 321 ::print(mop, OS, TM); 322 323 if (mop.opIsDefAndUse()) 324 OS << "<def&use>"; 325 else if (mop.opIsDefOnly()) 326 OS << "<def>"; 327 } 328 329 // code for printing implict references 330 if (getNumImplicitRefs()) { 331 OS << "\tImplicitRefs: "; 332 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 333 OS << "\t"; 334 OutputValue(OS, getImplicitRef(i)); 335 if (getImplicitOp(i).opIsDefAndUse()) 336 OS << "<def&use>"; 337 else if (getImplicitOp(i).opIsDefOnly()) 338 OS << "<def>"; 339 } 340 } 341 342 OS << "\n"; 343 } 344 345 346 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) 347 { 348 os << TargetInstrDescriptors[MI.opCode].Name; 349 350 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { 351 os << "\t" << MI.getOperand(i); 352 if (MI.getOperand(i).opIsDefOnly()) 353 os << "<d>"; 354 if (MI.getOperand(i).opIsDefAndUse()) 355 os << "<d&u>"; 356 } 357 358 // code for printing implict references 359 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 360 if (NumOfImpRefs > 0) { 361 os << "\tImplicit: "; 362 for (unsigned z=0; z < NumOfImpRefs; z++) { 363 OutputValue(os, MI.getImplicitRef(z)); 364 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>"; 365 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>"; 366 os << "\t"; 367 } 368 } 369 370 return os << "\n"; 371 } 372 373 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) 374 { 375 if (MO.opHiBits32()) 376 OS << "%lm("; 377 else if (MO.opLoBits32()) 378 OS << "%lo("; 379 else if (MO.opHiBits64()) 380 OS << "%hh("; 381 else if (MO.opLoBits64()) 382 OS << "%hm("; 383 384 switch (MO.getType()) 385 { 386 case MachineOperand::MO_VirtualRegister: 387 if (MO.hasAllocatedReg()) 388 OutputReg(OS, MO.getAllocatedRegNum()); 389 390 if (MO.getVRegValue()) { 391 if (MO.hasAllocatedReg()) OS << "=="; 392 OS << "%vreg"; 393 OutputValue(OS, MO.getVRegValue()); 394 } 395 break; 396 case MachineOperand::MO_CCRegister: 397 OS << "%ccreg"; 398 OutputValue(OS, MO.getVRegValue()); 399 if (MO.hasAllocatedReg()) { 400 OS << "=="; 401 OutputReg(OS, MO.getAllocatedRegNum()); 402 } 403 break; 404 case MachineOperand::MO_MachineRegister: 405 OutputReg(OS, MO.getMachineRegNum()); 406 break; 407 case MachineOperand::MO_SignExtendedImmed: 408 OS << (long)MO.getImmedValue(); 409 break; 410 case MachineOperand::MO_UnextendedImmed: 411 OS << (long)MO.getImmedValue(); 412 break; 413 case MachineOperand::MO_PCRelativeDisp: 414 { 415 const Value* opVal = MO.getVRegValue(); 416 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 417 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 418 if (opVal->hasName()) 419 OS << opVal->getName(); 420 else 421 OS << (const void*) opVal; 422 OS << ")"; 423 break; 424 } 425 case MachineOperand::MO_MachineBasicBlock: 426 OS << "bb<" 427 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 428 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 429 break; 430 case MachineOperand::MO_FrameIndex: 431 OS << "<fi#" << MO.getFrameIndex() << ">"; 432 break; 433 case MachineOperand::MO_ConstantPoolIndex: 434 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 435 break; 436 case MachineOperand::MO_GlobalAddress: 437 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 438 break; 439 case MachineOperand::MO_ExternalSymbol: 440 OS << "<es:" << MO.getSymbolName() << ">"; 441 break; 442 default: 443 assert(0 && "Unrecognized operand type"); 444 break; 445 } 446 447 if (MO.flags & 448 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | 449 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) 450 OS << ")"; 451 452 return OS; 453 } 454