1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 //===----------------------------------------------------------------------===// 4 5 #include "llvm/CodeGen/MachineInstr.h" 6 #include "llvm/CodeGen/MachineBasicBlock.h" 7 #include "llvm/Value.h" 8 #include "llvm/Target/TargetMachine.h" 9 #include "llvm/Target/TargetInstrInfo.h" 10 #include "llvm/Target/MRegisterInfo.h" 11 12 // Global variable holding an array of descriptors for machine instructions. 13 // The actual object needs to be created separately for each target machine. 14 // This variable is initialized and reset by class TargetInstrInfo. 15 // 16 // FIXME: This should be a property of the target so that more than one target 17 // at a time can be active... 18 // 19 extern const TargetInstrDescriptor *TargetInstrDescriptors; 20 21 // Constructor for instructions with variable #operands 22 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands) 23 : opCode(OpCode), 24 opCodeFlags(0), 25 operands(numOperands, MachineOperand()), 26 numImplicitRefs(0) 27 { 28 } 29 30 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 31 /// not a resize for them. It is expected that if you use this that you call 32 /// add* methods below to fill up the operands, instead of the Set methods. 33 /// Eventually, the "resizing" ctors will be phased out. 34 /// 35 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands, 36 bool XX, bool YY) 37 : opCode(Opcode), 38 opCodeFlags(0), 39 numImplicitRefs(0) 40 { 41 operands.reserve(numOperands); 42 } 43 44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 45 /// MachineInstr is created and added to the end of the specified basic block. 46 /// 47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, 48 unsigned numOperands) 49 : opCode(Opcode), 50 opCodeFlags(0), 51 numImplicitRefs(0) 52 { 53 assert(MBB && "Cannot use inserting ctor with null basic block!"); 54 operands.reserve(numOperands); 55 MBB->push_back(this); // Add instruction to end of basic block! 56 } 57 58 59 // OperandComplete - Return true if it's illegal to add a new operand 60 bool MachineInstr::OperandsComplete() const 61 { 62 int NumOperands = TargetInstrDescriptors[opCode].numOperands; 63 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 64 return true; // Broken: we have all the operands of this instruction! 65 return false; 66 } 67 68 69 // 70 // Support for replacing opcode and operands of a MachineInstr in place. 71 // This only resets the size of the operand vector and initializes it. 72 // The new operands must be set explicitly later. 73 // 74 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) 75 { 76 assert(getNumImplicitRefs() == 0 && 77 "This is probably broken because implicit refs are going to be lost."); 78 opCode = Opcode; 79 operands.clear(); 80 operands.resize(numOperands, MachineOperand()); 81 } 82 83 void 84 MachineInstr::SetMachineOperandVal(unsigned i, 85 MachineOperand::MachineOperandType opType, 86 Value* V, 87 bool isdef, 88 bool isDefAndUse) 89 { 90 assert(i < operands.size()); // may be explicit or implicit op 91 operands[i].opType = opType; 92 operands[i].value = V; 93 operands[i].regNum = -1; 94 95 if (isDefAndUse) 96 operands[i].flags = MachineOperand::DEFUSEFLAG; 97 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 98 operands[i].flags = MachineOperand::DEFONLYFLAG; 99 else 100 operands[i].flags = 0; 101 } 102 103 void 104 MachineInstr::SetMachineOperandConst(unsigned i, 105 MachineOperand::MachineOperandType operandType, 106 int64_t intValue) 107 { 108 assert(i < getNumOperands()); // must be explicit op 109 assert(TargetInstrDescriptors[opCode].resultPos != (int) i && 110 "immed. constant cannot be defined"); 111 112 operands[i].opType = operandType; 113 operands[i].value = NULL; 114 operands[i].immedVal = intValue; 115 operands[i].regNum = -1; 116 operands[i].flags = 0; 117 } 118 119 void 120 MachineInstr::SetMachineOperandReg(unsigned i, 121 int regNum, 122 bool isdef) { 123 assert(i < getNumOperands()); // must be explicit op 124 125 operands[i].opType = MachineOperand::MO_MachineRegister; 126 operands[i].value = NULL; 127 operands[i].regNum = regNum; 128 129 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int)i) { 130 assert(operands[i].flags == MachineOperand::DEFONLYFLAG && 131 "Shouldn't be changing a register type once set!"); 132 operands[i].flags = MachineOperand::DEFONLYFLAG; 133 } 134 135 insertUsedReg(regNum); 136 } 137 138 void 139 MachineInstr::SetRegForOperand(unsigned i, int regNum) 140 { 141 assert(i < getNumOperands()); // must be explicit op 142 operands[i].setRegForValue(regNum); 143 insertUsedReg(regNum); 144 } 145 146 void 147 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) 148 { 149 getImplicitOp(i).setRegForValue(regNum); 150 insertUsedReg(regNum); 151 } 152 153 154 // Subsitute all occurrences of Value* oldVal with newVal in all operands 155 // and all implicit refs. 156 // If defsOnly == true, substitute defs only. 157 unsigned 158 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 159 bool defsOnly, bool notDefsAndUses, 160 bool& someArgsWereIgnored) 161 { 162 assert((defsOnly || !notDefsAndUses) && 163 "notDefsAndUses is irrelevant if defsOnly == false."); 164 165 unsigned numSubst = 0; 166 167 // Subsitute operands 168 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 169 if (*O == oldVal) 170 if (!defsOnly || 171 notDefsAndUses && O.isDefOnly() || 172 !notDefsAndUses && !O.isUseOnly()) 173 { 174 O.getMachineOperand().value = newVal; 175 ++numSubst; 176 } 177 else 178 someArgsWereIgnored = true; 179 180 // Subsitute implicit refs 181 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 182 if (getImplicitRef(i) == oldVal) 183 if (!defsOnly || 184 notDefsAndUses && getImplicitOp(i).opIsDefOnly() || 185 !notDefsAndUses && !getImplicitOp(i).opIsUse()) 186 { 187 getImplicitOp(i).value = newVal; 188 ++numSubst; 189 } 190 else 191 someArgsWereIgnored = true; 192 193 return numSubst; 194 } 195 196 197 void 198 MachineInstr::dump() const 199 { 200 std::cerr << " " << *this; 201 } 202 203 static inline std::ostream& 204 OutputValue(std::ostream &os, const Value* val) 205 { 206 os << "(val "; 207 os << (void*) val; // print address always 208 if (val && val->hasName()) 209 os << " " << val->getName() << ")"; // print name also, if available 210 return os; 211 } 212 213 static inline void OutputReg(std::ostream &os, unsigned RegNo, 214 const MRegisterInfo *MRI = 0) { 215 if (MRI) { 216 if (RegNo < MRegisterInfo::FirstVirtualRegister) 217 os << "%" << MRI->get(RegNo).Name; 218 else 219 os << "%reg" << RegNo; 220 } else 221 os << "%mreg(" << RegNo << ")"; 222 } 223 224 static void print(const MachineOperand &MO, std::ostream &OS, 225 const TargetMachine &TM) { 226 const MRegisterInfo *MRI = TM.getRegisterInfo(); 227 bool CloseParen = true; 228 if (MO.opHiBits32()) 229 OS << "%lm("; 230 else if (MO.opLoBits32()) 231 OS << "%lo("; 232 else if (MO.opHiBits64()) 233 OS << "%hh("; 234 else if (MO.opLoBits64()) 235 OS << "%hm("; 236 else 237 CloseParen = false; 238 239 switch (MO.getType()) { 240 case MachineOperand::MO_VirtualRegister: 241 if (MO.getVRegValue()) { 242 OS << "%reg"; 243 OutputValue(OS, MO.getVRegValue()); 244 if (MO.hasAllocatedReg()) 245 OS << "=="; 246 } 247 if (MO.hasAllocatedReg()) 248 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 249 break; 250 case MachineOperand::MO_CCRegister: 251 OS << "%ccreg"; 252 OutputValue(OS, MO.getVRegValue()); 253 if (MO.hasAllocatedReg()) { 254 OS << "=="; 255 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 256 } 257 break; 258 case MachineOperand::MO_MachineRegister: 259 OutputReg(OS, MO.getMachineRegNum(), MRI); 260 break; 261 case MachineOperand::MO_SignExtendedImmed: 262 OS << (long)MO.getImmedValue(); 263 break; 264 case MachineOperand::MO_UnextendedImmed: 265 OS << (long)MO.getImmedValue(); 266 break; 267 case MachineOperand::MO_PCRelativeDisp: { 268 const Value* opVal = MO.getVRegValue(); 269 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 270 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 271 if (opVal->hasName()) 272 OS << opVal->getName(); 273 else 274 OS << (const void*) opVal; 275 OS << ")"; 276 break; 277 } 278 case MachineOperand::MO_MachineBasicBlock: 279 OS << "bb<" 280 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 281 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 282 break; 283 case MachineOperand::MO_FrameIndex: 284 OS << "<fi#" << MO.getFrameIndex() << ">"; 285 break; 286 case MachineOperand::MO_ConstantPoolIndex: 287 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 288 break; 289 case MachineOperand::MO_GlobalAddress: 290 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 291 break; 292 case MachineOperand::MO_ExternalSymbol: 293 OS << "<es:" << MO.getSymbolName() << ">"; 294 break; 295 default: 296 assert(0 && "Unrecognized operand type"); 297 } 298 299 if (CloseParen) 300 OS << ")"; 301 } 302 303 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { 304 unsigned StartOp = 0; 305 306 // Specialize printing if op#0 is definition 307 if (getNumOperands() && 308 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) { 309 ::print(getOperand(0), OS, TM); 310 OS << " = "; 311 ++StartOp; // Don't print this operand again! 312 } 313 OS << TM.getInstrInfo().getName(getOpcode()); 314 315 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 316 const MachineOperand& mop = getOperand(i); 317 if (i != StartOp) 318 OS << ","; 319 OS << " "; 320 ::print(mop, OS, TM); 321 322 if (mop.opIsDefAndUse()) 323 OS << "<def&use>"; 324 else if (mop.opIsDefOnly()) 325 OS << "<def>"; 326 } 327 328 // code for printing implict references 329 if (getNumImplicitRefs()) { 330 OS << "\tImplicitRefs: "; 331 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 332 OS << "\t"; 333 OutputValue(OS, getImplicitRef(i)); 334 if (getImplicitOp(i).opIsDefAndUse()) 335 OS << "<def&use>"; 336 else if (getImplicitOp(i).opIsDefOnly()) 337 OS << "<def>"; 338 } 339 } 340 341 OS << "\n"; 342 } 343 344 345 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) 346 { 347 os << TargetInstrDescriptors[MI.opCode].Name; 348 349 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { 350 os << "\t" << MI.getOperand(i); 351 if (MI.getOperand(i).opIsDefOnly()) 352 os << "<d>"; 353 if (MI.getOperand(i).opIsDefAndUse()) 354 os << "<d&u>"; 355 } 356 357 // code for printing implict references 358 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 359 if (NumOfImpRefs > 0) { 360 os << "\tImplicit: "; 361 for (unsigned z=0; z < NumOfImpRefs; z++) { 362 OutputValue(os, MI.getImplicitRef(z)); 363 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>"; 364 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>"; 365 os << "\t"; 366 } 367 } 368 369 return os << "\n"; 370 } 371 372 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) 373 { 374 if (MO.opHiBits32()) 375 OS << "%lm("; 376 else if (MO.opLoBits32()) 377 OS << "%lo("; 378 else if (MO.opHiBits64()) 379 OS << "%hh("; 380 else if (MO.opLoBits64()) 381 OS << "%hm("; 382 383 switch (MO.getType()) 384 { 385 case MachineOperand::MO_VirtualRegister: 386 if (MO.hasAllocatedReg()) 387 OutputReg(OS, MO.getAllocatedRegNum()); 388 389 if (MO.getVRegValue()) { 390 if (MO.hasAllocatedReg()) OS << "=="; 391 OS << "%vreg"; 392 OutputValue(OS, MO.getVRegValue()); 393 } 394 break; 395 case MachineOperand::MO_CCRegister: 396 OS << "%ccreg"; 397 OutputValue(OS, MO.getVRegValue()); 398 if (MO.hasAllocatedReg()) { 399 OS << "=="; 400 OutputReg(OS, MO.getAllocatedRegNum()); 401 } 402 break; 403 case MachineOperand::MO_MachineRegister: 404 OutputReg(OS, MO.getMachineRegNum()); 405 break; 406 case MachineOperand::MO_SignExtendedImmed: 407 OS << (long)MO.getImmedValue(); 408 break; 409 case MachineOperand::MO_UnextendedImmed: 410 OS << (long)MO.getImmedValue(); 411 break; 412 case MachineOperand::MO_PCRelativeDisp: 413 { 414 const Value* opVal = MO.getVRegValue(); 415 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 416 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 417 if (opVal->hasName()) 418 OS << opVal->getName(); 419 else 420 OS << (const void*) opVal; 421 OS << ")"; 422 break; 423 } 424 case MachineOperand::MO_MachineBasicBlock: 425 OS << "bb<" 426 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 427 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 428 break; 429 case MachineOperand::MO_FrameIndex: 430 OS << "<fi#" << MO.getFrameIndex() << ">"; 431 break; 432 case MachineOperand::MO_ConstantPoolIndex: 433 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 434 break; 435 case MachineOperand::MO_GlobalAddress: 436 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 437 break; 438 case MachineOperand::MO_ExternalSymbol: 439 OS << "<es:" << MO.getSymbolName() << ">"; 440 break; 441 default: 442 assert(0 && "Unrecognized operand type"); 443 break; 444 } 445 446 if (MO.flags & 447 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | 448 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) 449 OS << ")"; 450 451 return OS; 452 } 453