1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/MachineInstr.h" 13 #include "llvm/CodeGen/MachineBasicBlock.h" 14 #include "llvm/Value.h" 15 #include "llvm/Target/TargetMachine.h" 16 #include "llvm/Target/TargetInstrInfo.h" 17 #include "llvm/Target/MRegisterInfo.h" 18 19 namespace llvm { 20 21 // Global variable holding an array of descriptors for machine instructions. 22 // The actual object needs to be created separately for each target machine. 23 // This variable is initialized and reset by class TargetInstrInfo. 24 // 25 // FIXME: This should be a property of the target so that more than one target 26 // at a time can be active... 27 // 28 extern const TargetInstrDescriptor *TargetInstrDescriptors; 29 30 bool MachineOperand::isEverUsed(const MachineInstr& mi) const 31 { 32 for (int i = 0, e = mi.getNumOperands(); i != e; ++i) { 33 if (*this == mi.getOperand(i) && mi.getOperand(i).isUse()) 34 return true; 35 } 36 return false; 37 } 38 39 bool MachineOperand::isEverDefined(const MachineInstr& mi) const 40 { 41 for (int i = 0, e = mi.getNumOperands(); i != e; ++i) { 42 if (*this == mi.getOperand(i) && mi.getOperand(i).isDef()) 43 return true; 44 } 45 return false; 46 } 47 48 // Constructor for instructions with variable #operands 49 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands) 50 : opCode(OpCode), 51 opCodeFlags(0), 52 operands(numOperands, MachineOperand()), 53 numImplicitRefs(0) 54 { 55 } 56 57 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 58 /// not a resize for them. It is expected that if you use this that you call 59 /// add* methods below to fill up the operands, instead of the Set methods. 60 /// Eventually, the "resizing" ctors will be phased out. 61 /// 62 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands, 63 bool XX, bool YY) 64 : opCode(Opcode), 65 opCodeFlags(0), 66 numImplicitRefs(0) 67 { 68 operands.reserve(numOperands); 69 } 70 71 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 72 /// MachineInstr is created and added to the end of the specified basic block. 73 /// 74 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, 75 unsigned numOperands) 76 : opCode(Opcode), 77 opCodeFlags(0), 78 numImplicitRefs(0) 79 { 80 assert(MBB && "Cannot use inserting ctor with null basic block!"); 81 operands.reserve(numOperands); 82 MBB->push_back(this); // Add instruction to end of basic block! 83 } 84 85 86 // OperandComplete - Return true if it's illegal to add a new operand 87 bool MachineInstr::OperandsComplete() const 88 { 89 int NumOperands = TargetInstrDescriptors[opCode].numOperands; 90 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 91 return true; // Broken: we have all the operands of this instruction! 92 return false; 93 } 94 95 96 // 97 // Support for replacing opcode and operands of a MachineInstr in place. 98 // This only resets the size of the operand vector and initializes it. 99 // The new operands must be set explicitly later. 100 // 101 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) 102 { 103 assert(getNumImplicitRefs() == 0 && 104 "This is probably broken because implicit refs are going to be lost."); 105 opCode = Opcode; 106 operands.clear(); 107 operands.resize(numOperands, MachineOperand()); 108 } 109 110 void MachineInstr::SetMachineOperandVal(unsigned i, 111 MachineOperand::MachineOperandType opTy, 112 Value* V) { 113 assert(i < operands.size()); // may be explicit or implicit op 114 operands[i].opType = opTy; 115 operands[i].value = V; 116 operands[i].regNum = -1; 117 } 118 119 void 120 MachineInstr::SetMachineOperandConst(unsigned i, 121 MachineOperand::MachineOperandType operandType, 122 int64_t intValue) 123 { 124 assert(i < getNumOperands()); // must be explicit op 125 assert(TargetInstrDescriptors[opCode].resultPos != (int) i && 126 "immed. constant cannot be defined"); 127 128 operands[i].opType = operandType; 129 operands[i].value = NULL; 130 operands[i].immedVal = intValue; 131 operands[i].regNum = -1; 132 operands[i].flags = 0; 133 } 134 135 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { 136 assert(i < getNumOperands()); // must be explicit op 137 138 operands[i].opType = MachineOperand::MO_MachineRegister; 139 operands[i].value = NULL; 140 operands[i].regNum = regNum; 141 } 142 143 void 144 MachineInstr::SetRegForOperand(unsigned i, int regNum) 145 { 146 assert(i < getNumOperands()); // must be explicit op 147 operands[i].setRegForValue(regNum); 148 } 149 150 void 151 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) 152 { 153 getImplicitOp(i).setRegForValue(regNum); 154 } 155 156 157 // Substitute all occurrences of Value* oldVal with newVal in all operands 158 // and all implicit refs. 159 // If defsOnly == true, substitute defs only. 160 unsigned 161 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 162 bool defsOnly, bool notDefsAndUses, 163 bool& someArgsWereIgnored) 164 { 165 assert((!defsOnly || !notDefsAndUses) && 166 "notDefsAndUses is irrelevant if defsOnly == true."); 167 168 unsigned numSubst = 0; 169 170 // Substitute operands 171 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 172 if (*O == oldVal) 173 if (!defsOnly || 174 notDefsAndUses && (O.isDef() && !O.isUse()) || 175 !notDefsAndUses && O.isDef()) 176 { 177 O.getMachineOperand().value = newVal; 178 ++numSubst; 179 } 180 else 181 someArgsWereIgnored = true; 182 183 // Substitute implicit refs 184 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 185 if (getImplicitRef(i) == oldVal) 186 if (!defsOnly || 187 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) || 188 !notDefsAndUses && getImplicitOp(i).isDef()) 189 { 190 getImplicitOp(i).value = newVal; 191 ++numSubst; 192 } 193 else 194 someArgsWereIgnored = true; 195 196 return numSubst; 197 } 198 199 200 void 201 MachineInstr::dump() const 202 { 203 std::cerr << " " << *this; 204 } 205 206 static inline std::ostream& 207 OutputValue(std::ostream &os, const Value* val) 208 { 209 os << "(val "; 210 os << (void*) val; // print address always 211 if (val && val->hasName()) 212 os << " " << val->getName() << ")"; // print name also, if available 213 return os; 214 } 215 216 static inline void OutputReg(std::ostream &os, unsigned RegNo, 217 const MRegisterInfo *MRI = 0) { 218 if (MRI) { 219 if (RegNo < MRegisterInfo::FirstVirtualRegister) 220 os << "%" << MRI->get(RegNo).Name; 221 else 222 os << "%reg" << RegNo; 223 } else 224 os << "%mreg(" << RegNo << ")"; 225 } 226 227 static void print(const MachineOperand &MO, std::ostream &OS, 228 const TargetMachine &TM) { 229 const MRegisterInfo *MRI = TM.getRegisterInfo(); 230 bool CloseParen = true; 231 if (MO.isHiBits32()) 232 OS << "%lm("; 233 else if (MO.isLoBits32()) 234 OS << "%lo("; 235 else if (MO.isHiBits64()) 236 OS << "%hh("; 237 else if (MO.isLoBits64()) 238 OS << "%hm("; 239 else 240 CloseParen = false; 241 242 switch (MO.getType()) { 243 case MachineOperand::MO_VirtualRegister: 244 if (MO.getVRegValue()) { 245 OS << "%reg"; 246 OutputValue(OS, MO.getVRegValue()); 247 if (MO.hasAllocatedReg()) 248 OS << "=="; 249 } 250 if (MO.hasAllocatedReg()) 251 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 252 break; 253 case MachineOperand::MO_CCRegister: 254 OS << "%ccreg"; 255 OutputValue(OS, MO.getVRegValue()); 256 if (MO.hasAllocatedReg()) { 257 OS << "=="; 258 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 259 } 260 break; 261 case MachineOperand::MO_MachineRegister: 262 OutputReg(OS, MO.getMachineRegNum(), MRI); 263 break; 264 case MachineOperand::MO_SignExtendedImmed: 265 OS << (long)MO.getImmedValue(); 266 break; 267 case MachineOperand::MO_UnextendedImmed: 268 OS << (long)MO.getImmedValue(); 269 break; 270 case MachineOperand::MO_PCRelativeDisp: { 271 const Value* opVal = MO.getVRegValue(); 272 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 273 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 274 if (opVal->hasName()) 275 OS << opVal->getName(); 276 else 277 OS << (const void*) opVal; 278 OS << ")"; 279 break; 280 } 281 case MachineOperand::MO_MachineBasicBlock: 282 OS << "bb<" 283 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 284 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 285 break; 286 case MachineOperand::MO_FrameIndex: 287 OS << "<fi#" << MO.getFrameIndex() << ">"; 288 break; 289 case MachineOperand::MO_ConstantPoolIndex: 290 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 291 break; 292 case MachineOperand::MO_GlobalAddress: 293 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 294 break; 295 case MachineOperand::MO_ExternalSymbol: 296 OS << "<es:" << MO.getSymbolName() << ">"; 297 break; 298 default: 299 assert(0 && "Unrecognized operand type"); 300 } 301 302 if (CloseParen) 303 OS << ")"; 304 } 305 306 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { 307 unsigned StartOp = 0; 308 309 // Specialize printing if op#0 is definition 310 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { 311 llvm::print(getOperand(0), OS, TM); 312 OS << " = "; 313 ++StartOp; // Don't print this operand again! 314 } 315 OS << TM.getInstrInfo().getName(getOpcode()); 316 317 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 318 const MachineOperand& mop = getOperand(i); 319 if (i != StartOp) 320 OS << ","; 321 OS << " "; 322 llvm::print(mop, OS, TM); 323 324 if (mop.isDef()) 325 if (mop.isUse()) 326 OS << "<def&use>"; 327 else 328 OS << "<def>"; 329 } 330 331 // code for printing implicit references 332 if (getNumImplicitRefs()) { 333 OS << "\tImplicitRefs: "; 334 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 335 OS << "\t"; 336 OutputValue(OS, getImplicitRef(i)); 337 if (getImplicitOp(i).isDef()) 338 if (getImplicitOp(i).isUse()) 339 OS << "<def&use>"; 340 else 341 OS << "<def>"; 342 } 343 } 344 345 OS << "\n"; 346 } 347 348 349 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) 350 { 351 os << TargetInstrDescriptors[MI.opCode].Name; 352 353 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { 354 os << "\t" << MI.getOperand(i); 355 if (MI.getOperand(i).isDef()) 356 if (MI.getOperand(i).isUse()) 357 os << "<d&u>"; 358 else 359 os << "<d>"; 360 } 361 362 // code for printing implicit references 363 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 364 if (NumOfImpRefs > 0) { 365 os << "\tImplicit: "; 366 for (unsigned z=0; z < NumOfImpRefs; z++) { 367 OutputValue(os, MI.getImplicitRef(z)); 368 if (MI.getImplicitOp(z).isDef()) 369 if (MI.getImplicitOp(z).isUse()) 370 os << "<d&u>"; 371 else 372 os << "<d>"; 373 os << "\t"; 374 } 375 } 376 377 return os << "\n"; 378 } 379 380 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) 381 { 382 if (MO.isHiBits32()) 383 OS << "%lm("; 384 else if (MO.isLoBits32()) 385 OS << "%lo("; 386 else if (MO.isHiBits64()) 387 OS << "%hh("; 388 else if (MO.isLoBits64()) 389 OS << "%hm("; 390 391 switch (MO.getType()) 392 { 393 case MachineOperand::MO_VirtualRegister: 394 if (MO.hasAllocatedReg()) 395 OutputReg(OS, MO.getAllocatedRegNum()); 396 397 if (MO.getVRegValue()) { 398 if (MO.hasAllocatedReg()) OS << "=="; 399 OS << "%vreg"; 400 OutputValue(OS, MO.getVRegValue()); 401 } 402 break; 403 case MachineOperand::MO_CCRegister: 404 OS << "%ccreg"; 405 OutputValue(OS, MO.getVRegValue()); 406 if (MO.hasAllocatedReg()) { 407 OS << "=="; 408 OutputReg(OS, MO.getAllocatedRegNum()); 409 } 410 break; 411 case MachineOperand::MO_MachineRegister: 412 OutputReg(OS, MO.getMachineRegNum()); 413 break; 414 case MachineOperand::MO_SignExtendedImmed: 415 OS << (long)MO.getImmedValue(); 416 break; 417 case MachineOperand::MO_UnextendedImmed: 418 OS << (long)MO.getImmedValue(); 419 break; 420 case MachineOperand::MO_PCRelativeDisp: 421 { 422 const Value* opVal = MO.getVRegValue(); 423 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 424 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 425 if (opVal->hasName()) 426 OS << opVal->getName(); 427 else 428 OS << (const void*) opVal; 429 OS << ")"; 430 break; 431 } 432 case MachineOperand::MO_MachineBasicBlock: 433 OS << "bb<" 434 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 435 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 436 break; 437 case MachineOperand::MO_FrameIndex: 438 OS << "<fi#" << MO.getFrameIndex() << ">"; 439 break; 440 case MachineOperand::MO_ConstantPoolIndex: 441 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 442 break; 443 case MachineOperand::MO_GlobalAddress: 444 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 445 break; 446 case MachineOperand::MO_ExternalSymbol: 447 OS << "<es:" << MO.getSymbolName() << ">"; 448 break; 449 default: 450 assert(0 && "Unrecognized operand type"); 451 break; 452 } 453 454 if (MO.flags & 455 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | 456 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) 457 OS << ")"; 458 459 return OS; 460 } 461 462 } // End llvm namespace 463