1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 //===----------------------------------------------------------------------===// 4 5 #include "llvm/CodeGen/MachineInstr.h" 6 #include "llvm/CodeGen/MachineBasicBlock.h" 7 #include "llvm/Value.h" 8 #include "llvm/Target/TargetMachine.h" 9 #include "llvm/Target/MachineInstrInfo.h" 10 #include "llvm/Target/MRegisterInfo.h" 11 using std::cerr; 12 13 // Global variable holding an array of descriptors for machine instructions. 14 // The actual object needs to be created separately for each target machine. 15 // This variable is initialized and reset by class MachineInstrInfo. 16 // 17 // FIXME: This should be a property of the target so that more than one target 18 // at a time can be active... 19 // 20 extern const MachineInstrDescriptor *TargetInstrDescriptors; 21 22 // Constructor for instructions with fixed #operands (nearly all) 23 MachineInstr::MachineInstr(MachineOpCode _opCode) 24 : opCode(_opCode), 25 operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()), 26 numImplicitRefs(0) 27 { 28 assert(TargetInstrDescriptors[_opCode].numOperands >= 0); 29 } 30 31 // Constructor for instructions with variable #operands 32 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands) 33 : opCode(OpCode), 34 operands(numOperands, MachineOperand()), 35 numImplicitRefs(0) 36 { 37 } 38 39 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 40 /// not a resize for them. It is expected that if you use this that you call 41 /// add* methods below to fill up the operands, instead of the Set methods. 42 /// Eventually, the "resizing" ctors will be phased out. 43 /// 44 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands, 45 bool XX, bool YY) 46 : opCode(Opcode), 47 numImplicitRefs(0) 48 { 49 operands.reserve(numOperands); 50 } 51 52 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 53 /// MachineInstr is created and added to the end of the specified basic block. 54 /// 55 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, 56 unsigned numOperands) 57 : opCode(Opcode), 58 numImplicitRefs(0) 59 { 60 assert(MBB && "Cannot use inserting ctor with null basic block!"); 61 operands.reserve(numOperands); 62 MBB->push_back(this); // Add instruction to end of basic block! 63 } 64 65 66 // OperandComplete - Return true if it's illegal to add a new operand 67 bool MachineInstr::OperandsComplete() const 68 { 69 int NumOperands = TargetInstrDescriptors[opCode].numOperands; 70 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 71 return true; // Broken! 72 return false; 73 } 74 75 76 // 77 // Support for replacing opcode and operands of a MachineInstr in place. 78 // This only resets the size of the operand vector and initializes it. 79 // The new operands must be set explicitly later. 80 // 81 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) 82 { 83 assert(getNumImplicitRefs() == 0 && 84 "This is probably broken because implicit refs are going to be lost."); 85 opCode = Opcode; 86 operands.clear(); 87 operands.resize(numOperands, MachineOperand()); 88 } 89 90 void 91 MachineInstr::SetMachineOperandVal(unsigned i, 92 MachineOperand::MachineOperandType opType, 93 Value* V, 94 bool isdef, 95 bool isDefAndUse) 96 { 97 assert(i < operands.size()); // may be explicit or implicit op 98 operands[i].opType = opType; 99 operands[i].value = V; 100 operands[i].regNum = -1; 101 102 if (isDefAndUse) 103 operands[i].flags = MachineOperand::DEFUSEFLAG; 104 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 105 operands[i].flags = MachineOperand::DEFFLAG; 106 else 107 operands[i].flags = 0; 108 } 109 110 void 111 MachineInstr::SetMachineOperandConst(unsigned i, 112 MachineOperand::MachineOperandType operandType, 113 int64_t intValue) 114 { 115 assert(i < getNumOperands()); // must be explicit op 116 assert(TargetInstrDescriptors[opCode].resultPos != (int) i && 117 "immed. constant cannot be defined"); 118 119 operands[i].opType = operandType; 120 operands[i].value = NULL; 121 operands[i].immedVal = intValue; 122 operands[i].regNum = -1; 123 operands[i].flags = 0; 124 } 125 126 void 127 MachineInstr::SetMachineOperandReg(unsigned i, 128 int regNum, 129 bool isdef) { 130 assert(i < getNumOperands()); // must be explicit op 131 132 operands[i].opType = MachineOperand::MO_MachineRegister; 133 operands[i].value = NULL; 134 operands[i].regNum = regNum; 135 136 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i) 137 operands[i].flags = MachineOperand::DEFFLAG; 138 else 139 operands[i].flags = 0; 140 141 insertUsedReg(regNum); 142 } 143 144 void 145 MachineInstr::SetRegForOperand(unsigned i, int regNum) 146 { 147 assert(i < getNumOperands()); // must be explicit op 148 operands[i].setRegForValue(regNum); 149 insertUsedReg(regNum); 150 } 151 152 153 // Subsitute all occurrences of Value* oldVal with newVal in all operands 154 // and all implicit refs. If defsOnly == true, substitute defs only. 155 unsigned 156 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly) 157 { 158 unsigned numSubst = 0; 159 160 // Subsitute operands 161 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 162 if (*O == oldVal) 163 if (!defsOnly || O.isDef()) 164 { 165 O.getMachineOperand().value = newVal; 166 ++numSubst; 167 } 168 169 // Subsitute implicit refs 170 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 171 if (getImplicitRef(i) == oldVal) 172 if (!defsOnly || implicitRefIsDefined(i)) 173 { 174 getImplicitOp(i).value = newVal; 175 ++numSubst; 176 } 177 178 return numSubst; 179 } 180 181 182 void 183 MachineInstr::dump() const 184 { 185 cerr << " " << *this; 186 } 187 188 static inline std::ostream& 189 OutputValue(std::ostream &os, const Value* val) 190 { 191 os << "(val "; 192 if (val && val->hasName()) 193 return os << val->getName() << ")"; 194 else 195 return os << (void*) val << ")"; // print address only 196 } 197 198 static inline void OutputReg(std::ostream &os, unsigned RegNo, 199 const MRegisterInfo *MRI = 0) { 200 if (MRI) { 201 if (RegNo < MRegisterInfo::FirstVirtualRegister) 202 os << "%" << MRI->get(RegNo).Name; 203 else 204 os << "%reg" << RegNo; 205 } else 206 os << "%mreg(" << RegNo << ")"; 207 } 208 209 static void print(const MachineOperand &MO, std::ostream &OS, 210 const TargetMachine &TM) { 211 const MRegisterInfo *MRI = TM.getRegisterInfo(); 212 bool CloseParen = true; 213 if (MO.opHiBits32()) 214 OS << "%lm("; 215 else if (MO.opLoBits32()) 216 OS << "%lo("; 217 else if (MO.opHiBits64()) 218 OS << "%hh("; 219 else if (MO.opLoBits64()) 220 OS << "%hm("; 221 else 222 CloseParen = false; 223 224 switch (MO.getType()) { 225 case MachineOperand::MO_VirtualRegister: 226 if (MO.getVRegValue()) { 227 OS << "%reg"; 228 OutputValue(OS, MO.getVRegValue()); 229 if (MO.hasAllocatedReg()) 230 OS << "=="; 231 } 232 if (MO.hasAllocatedReg()) 233 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 234 break; 235 case MachineOperand::MO_CCRegister: 236 OS << "%ccreg"; 237 OutputValue(OS, MO.getVRegValue()); 238 if (MO.hasAllocatedReg()) { 239 OS << "=="; 240 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 241 } 242 break; 243 case MachineOperand::MO_MachineRegister: 244 OutputReg(OS, MO.getMachineRegNum(), MRI); 245 break; 246 case MachineOperand::MO_SignExtendedImmed: 247 OS << (long)MO.getImmedValue(); 248 break; 249 case MachineOperand::MO_UnextendedImmed: 250 OS << (long)MO.getImmedValue(); 251 break; 252 case MachineOperand::MO_PCRelativeDisp: { 253 const Value* opVal = MO.getVRegValue(); 254 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 255 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 256 if (opVal->hasName()) 257 OS << opVal->getName(); 258 else 259 OS << (const void*) opVal; 260 OS << ")"; 261 break; 262 } 263 default: 264 assert(0 && "Unrecognized operand type"); 265 } 266 267 if (CloseParen) 268 OS << ")"; 269 } 270 271 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) { 272 unsigned StartOp = 0; 273 274 // Specialize printing if op#0 is definition 275 if (getNumOperands() && operandIsDefined(0)) { 276 ::print(getOperand(0), OS, TM); 277 OS << " = "; 278 ++StartOp; // Don't print this operand again! 279 } 280 OS << TM.getInstrInfo().getName(getOpcode()); 281 282 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 283 if (i != StartOp) 284 OS << ","; 285 OS << " "; 286 ::print(getOperand(i), OS, TM); 287 288 if (operandIsDefinedAndUsed(i)) 289 OS << "<def&use>"; 290 else if (operandIsDefined(i)) 291 OS << "<def>"; 292 } 293 294 // code for printing implict references 295 if (getNumImplicitRefs()) { 296 OS << "\tImplicitRefs: "; 297 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 298 OS << "\t"; 299 OutputValue(OS, getImplicitRef(i)); 300 if (implicitRefIsDefinedAndUsed(i)) 301 OS << "<def&use>"; 302 else if (implicitRefIsDefined(i)) 303 OS << "<def>"; 304 } 305 } 306 307 OS << "\n"; 308 } 309 310 311 std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr) 312 { 313 os << TargetInstrDescriptors[minstr.opCode].Name; 314 315 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) { 316 os << "\t" << minstr.getOperand(i); 317 if( minstr.operandIsDefined(i) ) 318 os << "*"; 319 if( minstr.operandIsDefinedAndUsed(i) ) 320 os << "*"; 321 } 322 323 // code for printing implict references 324 unsigned NumOfImpRefs = minstr.getNumImplicitRefs(); 325 if( NumOfImpRefs > 0 ) { 326 os << "\tImplicit: "; 327 for(unsigned z=0; z < NumOfImpRefs; z++) { 328 OutputValue(os, minstr.getImplicitRef(z)); 329 if( minstr.implicitRefIsDefined(z)) os << "*"; 330 if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*"; 331 os << "\t"; 332 } 333 } 334 335 return os << "\n"; 336 } 337 338 std::ostream &operator<<(std::ostream &os, const MachineOperand &mop) 339 { 340 if (mop.opHiBits32()) 341 os << "%lm("; 342 else if (mop.opLoBits32()) 343 os << "%lo("; 344 else if (mop.opHiBits64()) 345 os << "%hh("; 346 else if (mop.opLoBits64()) 347 os << "%hm("; 348 349 switch (mop.getType()) 350 { 351 case MachineOperand::MO_VirtualRegister: 352 os << "%reg"; 353 OutputValue(os, mop.getVRegValue()); 354 if (mop.hasAllocatedReg()) { 355 os << "=="; 356 OutputReg(os, mop.getAllocatedRegNum()); 357 } 358 break; 359 case MachineOperand::MO_CCRegister: 360 os << "%ccreg"; 361 OutputValue(os, mop.getVRegValue()); 362 if (mop.hasAllocatedReg()) { 363 os << "=="; 364 OutputReg(os, mop.getAllocatedRegNum()); 365 } 366 break; 367 case MachineOperand::MO_MachineRegister: 368 OutputReg(os, mop.getMachineRegNum()); 369 break; 370 case MachineOperand::MO_SignExtendedImmed: 371 os << (long)mop.getImmedValue(); 372 break; 373 case MachineOperand::MO_UnextendedImmed: 374 os << (long)mop.getImmedValue(); 375 break; 376 case MachineOperand::MO_PCRelativeDisp: 377 { 378 const Value* opVal = mop.getVRegValue(); 379 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 380 os << "%disp(" << (isLabel? "label " : "addr-of-val "); 381 if (opVal->hasName()) 382 os << opVal->getName(); 383 else 384 os << (const void*) opVal; 385 os << ")"; 386 break; 387 } 388 default: 389 assert(0 && "Unrecognized operand type"); 390 break; 391 } 392 393 if (mop.flags & 394 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | 395 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) 396 os << ")"; 397 398 return os; 399 } 400