1 //===- CombinerHelperArtifacts.cpp-----------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements CombinerHelper for legalization artifacts. 10 // 11 //===----------------------------------------------------------------------===// 12 // 13 // G_MERGE_VALUES 14 // 15 //===----------------------------------------------------------------------===// 16 #include "llvm/CodeGen/GlobalISel/CombinerHelper.h" 17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 20 #include "llvm/CodeGen/GlobalISel/Utils.h" 21 #include "llvm/CodeGen/LowLevelTypeUtils.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/TargetOpcodes.h" 25 #include "llvm/Support/Casting.h" 26 27 #define DEBUG_TYPE "gi-combiner" 28 29 using namespace llvm; 30 31 bool CombinerHelper::matchMergeXAndUndef(const MachineInstr &MI, 32 BuildFnTy &MatchInfo) const { 33 const GMerge *Merge = cast<GMerge>(&MI); 34 35 Register Dst = Merge->getReg(0); 36 LLT DstTy = MRI.getType(Dst); 37 LLT SrcTy = MRI.getType(Merge->getSourceReg(0)); 38 39 // Otherwise, we would miscompile. 40 assert(Merge->getNumSources() == 2 && "Unexpected number of operands"); 41 42 // 43 // %bits_8_15:_(s8) = G_IMPLICIT_DEF 44 // %0:_(s16) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8) 45 // 46 // -> 47 // 48 // %0:_(s16) = G_ANYEXT %bits_0_7:(s8) 49 // 50 51 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ANYEXT, {DstTy, SrcTy}})) 52 return false; 53 54 MatchInfo = [=](MachineIRBuilder &B) { 55 B.buildAnyExt(Dst, Merge->getSourceReg(0)); 56 }; 57 return true; 58 } 59 60 bool CombinerHelper::matchMergeXAndZero(const MachineInstr &MI, 61 BuildFnTy &MatchInfo) const { 62 const GMerge *Merge = cast<GMerge>(&MI); 63 64 Register Dst = Merge->getReg(0); 65 LLT DstTy = MRI.getType(Dst); 66 LLT SrcTy = MRI.getType(Merge->getSourceReg(0)); 67 68 // No multi-use check. It is a constant. 69 70 // 71 // %bits_8_15:_(s8) = G_CONSTANT i8 0 72 // %0:_(s16) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8) 73 // 74 // -> 75 // 76 // %0:_(s16) = G_ZEXT %bits_0_7:(s8) 77 // 78 79 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}})) 80 return false; 81 82 MatchInfo = [=](MachineIRBuilder &B) { 83 B.buildZExt(Dst, Merge->getSourceReg(0)); 84 }; 85 return true; 86 } 87