xref: /llvm-project/lldb/test/API/python_api/lldbutil/iter/TestRegistersIterator.py (revision 2238dcc39358353cac21df75c3c3286ab20b8f53) 
1"""
2Test the iteration protocol for frame registers.
3"""
4
5import lldb
6from lldbsuite.test.decorators import *
7from lldbsuite.test.lldbtest import *
8from lldbsuite.test import lldbutil
9
10
11class RegistersIteratorTestCase(TestBase):
12    def setUp(self):
13        # Call super's setUp().
14        TestBase.setUp(self)
15        # Find the line number to break inside main().
16        self.line1 = line_number("main.cpp", "// Set break point at this line.")
17
18    def test_iter_registers(self):
19        """Test iterator works correctly for lldbutil.iter_registers()."""
20        self.build()
21        exe = self.getBuildArtifact("a.out")
22
23        target = self.dbg.CreateTarget(exe)
24        self.assertTrue(target, VALID_TARGET)
25
26        breakpoint = target.BreakpointCreateByLocation("main.cpp", self.line1)
27        self.assertTrue(breakpoint, VALID_BREAKPOINT)
28
29        # Now launch the process, and do not stop at entry point.
30        process = target.LaunchSimple(None, None, self.get_process_working_directory())
31
32        if not process:
33            self.fail("SBTarget.LaunchProcess() failed")
34
35        import lldbsuite.test.lldbutil as lldbutil
36
37        for thread in process:
38            if thread.GetStopReason() == lldb.eStopReasonBreakpoint:
39                for frame in thread:
40                    # Dump the registers of this frame using
41                    # lldbutil.get_GPRs() and friends.
42                    if self.TraceOn():
43                        print(frame)
44
45                    REGs = lldbutil.get_GPRs(frame)
46                    num = len(REGs)
47                    if self.TraceOn():
48                        print("\nNumber of general purpose registers: %d" % num)
49                    for reg in REGs:
50                        self.assertTrue(reg)
51                        if self.TraceOn():
52                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
53
54                    REGs = lldbutil.get_FPRs(frame)
55                    num = len(REGs)
56                    if self.TraceOn():
57                        print("\nNumber of floating point registers: %d" % num)
58                    for reg in REGs:
59                        self.assertTrue(reg)
60                        if self.TraceOn():
61                            print("%s => %s" % (reg.GetName(), reg.GetValue()))
62
63                    REGs = lldbutil.get_ESRs(frame)
64                    if self.platformIsDarwin():
65                        if (
66                            self.getArchitecture() != "armv7"
67                            and self.getArchitecture() != "armv7k"
68                        ):
69                            num = len(REGs)
70                            if self.TraceOn():
71                                print("\nNumber of exception state registers: %d" % num)
72                            for reg in REGs:
73                                self.assertTrue(reg)
74                                if self.TraceOn():
75                                    print("%s => %s" % (reg.GetName(), reg.GetValue()))
76                    else:
77                        self.assertIsNone(REGs)
78
79                    # And these should also work.
80                    for kind in [
81                        "General Purpose Registers",
82                        "Floating Point Registers",
83                    ]:
84                        REGs = lldbutil.get_registers(frame, kind)
85                        self.assertTrue(REGs)
86
87                    REGs = lldbutil.get_registers(frame, "Exception State Registers")
88                    if self.platformIsDarwin():
89                        if (
90                            self.getArchitecture() != "armv7"
91                            and self.getArchitecture() != "armv7k"
92                        ):
93                            self.assertIsNotNone(REGs)
94                    else:
95                        self.assertIsNone(REGs)
96
97                    # We've finished dumping the registers for frame #0.
98                    break
99