1import lldb 2from lldbsuite.test.lldbtest import * 3from lldbsuite.test.decorators import * 4from lldbsuite.test.gdbclientutils import * 5from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase 6 7 8class MyResponder(MockGDBServerResponder): 9 def qXferRead(self, obj, annex, offset, length): 10 if annex == "target.xml": 11 return ( 12 """<?xml version="1.0"?> 13 <target version="1.0"> 14 <architecture>i386:x86-64</architecture> 15 <feature name="org.gnu.gdb.i386.core"> 16 17 <flags id="i386_eflags" size="4"> 18 <field name="CF" start="0" end="0"/> 19 <field name="" start="1" end="1"/> 20 <field name="PF" start="2" end="2"/> 21 <field name="AF" start="4" end="4"/> 22 <field name="ZF" start="6" end="6"/> 23 <field name="SF" start="7" end="7"/> 24 <field name="TF" start="8" end="8"/> 25 <field name="IF" start="9" end="9"/> 26 <field name="DF" start="10" end="10"/> 27 <field name="OF" start="11" end="11"/> 28 <field name="NT" start="14" end="14"/> 29 <field name="RF" start="16" end="16"/> 30 <field name="VM" start="17" end="17"/> 31 <field name="AC" start="18" end="18"/> 32 <field name="VIF" start="19" end="19"/> 33 <field name="VIP" start="20" end="20"/> 34 <field name="ID" start="21" end="21"/> 35 </flags> 36 37 <reg name="rax" bitsize="64" regnum="0" type="int" group="general"/> 38 <reg name="rbx" bitsize="64" regnum="1" type="int" group="general"/> 39 <reg name="rcx" bitsize="64" regnum="2" type="int" group="general"/> 40 <reg name="rdx" bitsize="64" regnum="3" type="int" group="general"/> 41 <reg name="rsi" bitsize="64" regnum="4" type="int" group="general"/> 42 <reg name="rdi" bitsize="64" regnum="5" type="int" group="general"/> 43 <reg name="rbp" bitsize="64" regnum="6" type="data_ptr" group="general"/> 44 <reg name="rsp" bitsize="64" regnum="7" type="data_ptr" group="general"/> 45 <reg name="r8" bitsize="64" regnum="8" type="int" group="general"/> 46 <reg name="r9" bitsize="64" regnum="9" type="int" group="general"/> 47 <reg name="r10" bitsize="64" regnum="10" type="int" group="general"/> 48 <reg name="r11" bitsize="64" regnum="11" type="int" group="general"/> 49 <reg name="r12" bitsize="64" regnum="12" type="int" group="general"/> 50 <reg name="r13" bitsize="64" regnum="13" type="int" group="general"/> 51 <reg name="r14" bitsize="64" regnum="14" type="int" group="general"/> 52 <reg name="r15" bitsize="64" regnum="15" type="int" group="general"/> 53 <reg name="rip" bitsize="64" regnum="16" type="code_ptr" group="general"/> 54 <reg name="eflags" bitsize="32" regnum="17" type="i386_eflags" group="general"/> 55 56 <reg name="cs" bitsize="32" regnum="18" type="int" group="general"/> 57 <reg name="ss" bitsize="32" regnum="19" type="int" group="general"/> 58 <reg name="ds" bitsize="32" regnum="20" type="int" group="general"/> 59 <reg name="es" bitsize="32" regnum="21" type="int" group="general"/> 60 <reg name="fs" bitsize="32" regnum="22" type="int" group="general"/> 61 <reg name="gs" bitsize="32" regnum="23" type="int" group="general"/> 62 63 <reg name="st0" bitsize="80" regnum="24" type="i387_ext" group="float"/> 64 <reg name="st1" bitsize="80" regnum="25" type="i387_ext" group="float"/> 65 <reg name="st2" bitsize="80" regnum="26" type="i387_ext" group="float"/> 66 <reg name="st3" bitsize="80" regnum="27" type="i387_ext" group="float"/> 67 <reg name="st4" bitsize="80" regnum="28" type="i387_ext" group="float"/> 68 <reg name="st5" bitsize="80" regnum="29" type="i387_ext" group="float"/> 69 <reg name="st6" bitsize="80" regnum="30" type="i387_ext" group="float"/> 70 <reg name="st7" bitsize="80" regnum="31" type="i387_ext" group="float"/> 71 72 <reg name="fctrl" bitsize="32" regnum="32" type="int" group="float"/> 73 <reg name="fstat" bitsize="32" regnum="33" type="int" group="float"/> 74 <reg name="ftag" bitsize="32" regnum="34" type="int" group="float"/> 75 <reg name="fiseg" bitsize="32" regnum="35" type="int" group="float"/> 76 <reg name="fioff" bitsize="32" regnum="36" type="int" group="float"/> 77 <reg name="foseg" bitsize="32" regnum="37" type="int" group="float"/> 78 <reg name="fooff" bitsize="32" regnum="38" type="int" group="float"/> 79 <reg name="fop" bitsize="32" regnum="39" type="int" group="float"/> 80 </feature> 81 </target>""", 82 False, 83 ) 84 else: 85 return None, False 86 87 def qC(self): 88 return "QC1" 89 90 def haltReason(self): 91 return "T05thread:00000001;06:9038d60f00700000;07:98b4062680ffffff;10:c0d7bf1b80ffffff;" 92 93 def readRegister(self, register): 94 regs = { 95 0x0: "00b0060000610000", 96 0xA: "68fe471c80ffffff", 97 0xC: "60574a1c80ffffff", 98 0xD: "18f3042680ffffff", 99 0xE: "be8a4d7142000000", 100 0xF: "50df471c80ffffff", 101 0x10: "c0d7bf1b80ffffff", 102 } 103 if register in regs: 104 return regs[register] 105 else: 106 return "0000000000000000" 107 108 109class TestTargetXMLArch(GDBRemoteTestBase): 110 @skipIfXmlSupportMissing 111 @expectedFailureAll(archs=["i386"]) 112 @skipIfRemote 113 def test(self): 114 """ 115 Test lldb's parsing of the <architecture> tag in the target.xml register 116 description packet. 117 """ 118 self.server.responder = MyResponder() 119 interp = self.dbg.GetCommandInterpreter() 120 result = lldb.SBCommandReturnObject() 121 if self.TraceOn(): 122 self.runCmd("log enable gdb-remote packets") 123 self.addTearDownHook(lambda: self.runCmd("log disable gdb-remote packets")) 124 125 target = self.dbg.CreateTarget("") 126 self.assertEqual("", target.GetTriple()) 127 process = self.connect(target) 128 if self.TraceOn(): 129 interp.HandleCommand("target list", result) 130 print(result.GetOutput()) 131 self.assertTrue(target.GetTriple().startswith("x86_64-unknown-unknown")) 132 133 @skipIfXmlSupportMissing 134 @skipIfRemote 135 @skipIfLLVMTargetMissing("X86") 136 def test_register_augmentation(self): 137 """ 138 Test that we correctly associate the register info with the eh_frame 139 register numbers. 140 """ 141 142 target = self.createTarget("basic_eh_frame.yaml") 143 self.server.responder = MyResponder() 144 145 process = self.connect(target) 146 lldbutil.expect_state_changes( 147 self, self.dbg.GetListener(), process, [lldb.eStateStopped] 148 ) 149 self.filecheck("image show-unwind -n foo", __file__, "--check-prefix=UNWIND") 150 151 152# UNWIND: eh_frame UnwindPlan: 153# UNWIND: row[0]: 0: CFA=rsp+128 => rip=[CFA-8] 154