1from textwrap import dedent 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from lldbsuite.test.gdbclientutils import * 6from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase 7 8 9class MyResponder(MockGDBServerResponder): 10 def qXferRead(self, obj, annex, offset, length): 11 if annex == "target.xml": 12 return ( 13 dedent( 14 """\ 15 <?xml version="1.0"?> 16 <target version="1.0"> 17 <architecture>aarch64</architecture> 18 <feature name="org.gnu.gdb.aarch64.core"> 19 <reg name="cpsr" regnum="33" bitsize="32"/> 20 <reg name="x0" regnum="0" bitsize="64"/> 21 <reg name="x1" bitsize="64"/> 22 <reg name="x2" bitsize="64"/> 23 <reg name="x3" bitsize="64"/> 24 <reg name="x4" bitsize="64"/> 25 <reg name="x5" bitsize="64"/> 26 <reg name="x6" bitsize="64"/> 27 <reg name="x7" bitsize="64"/> 28 <reg name="x8" bitsize="64"/> 29 <reg name="x9" bitsize="64"/> 30 <reg name="x10" bitsize="64"/> 31 <reg name="x11" bitsize="64"/> 32 <reg name="x12" bitsize="64"/> 33 <reg name="x13" bitsize="64"/> 34 <reg name="x14" bitsize="64"/> 35 <reg name="x15" bitsize="64"/> 36 <reg name="x16" bitsize="64"/> 37 <reg name="x17" bitsize="64"/> 38 <reg name="x18" bitsize="64"/> 39 <reg name="x19" bitsize="64"/> 40 <reg name="x20" bitsize="64"/> 41 <reg name="x21" bitsize="64"/> 42 <reg name="x22" bitsize="64"/> 43 <reg name="x23" bitsize="64"/> 44 <reg name="x24" bitsize="64"/> 45 <reg name="x25" bitsize="64"/> 46 <reg name="x26" bitsize="64"/> 47 <reg name="x27" bitsize="64"/> 48 <reg name="x28" bitsize="64"/> 49 <reg name="x29" bitsize="64"/> 50 <reg name="x30" bitsize="64"/> 51 <reg name="sp" bitsize="64"/> 52 <reg name="pc" bitsize="64"/> 53 <reg name="w0" bitsize="32" value_regnums="0" invalidate_regnums="0" regnum="34"/> 54 <reg name="w1" bitsize="32" value_regnums="1" invalidate_regnums="1"/> 55 <reg name="w2" bitsize="32" value_regnums="2" invalidate_regnums="2"/> 56 <reg name="w3" bitsize="32" value_regnums="3" invalidate_regnums="3"/> 57 <reg name="w4" bitsize="32" value_regnums="4" invalidate_regnums="4"/> 58 <reg name="w5" bitsize="32" value_regnums="5" invalidate_regnums="5"/> 59 <reg name="w6" bitsize="32" value_regnums="6" invalidate_regnums="6"/> 60 <reg name="w7" bitsize="32" value_regnums="7" invalidate_regnums="7"/> 61 <reg name="w8" bitsize="32" value_regnums="8" invalidate_regnums="8"/> 62 <reg name="w9" bitsize="32" value_regnums="9" invalidate_regnums="9"/> 63 <reg name="w10" bitsize="32" value_regnums="10" invalidate_regnums="10"/> 64 <reg name="w11" bitsize="32" value_regnums="11" invalidate_regnums="11"/> 65 <reg name="w12" bitsize="32" value_regnums="12" invalidate_regnums="12"/> 66 <reg name="w13" bitsize="32" value_regnums="13" invalidate_regnums="13"/> 67 <reg name="w14" bitsize="32" value_regnums="14" invalidate_regnums="14"/> 68 <reg name="w15" bitsize="32" value_regnums="15" invalidate_regnums="15"/> 69 <reg name="w16" bitsize="32" value_regnums="16" invalidate_regnums="16"/> 70 <reg name="w17" bitsize="32" value_regnums="17" invalidate_regnums="17"/> 71 <reg name="w18" bitsize="32" value_regnums="18" invalidate_regnums="18"/> 72 <reg name="w19" bitsize="32" value_regnums="19" invalidate_regnums="19"/> 73 <reg name="w20" bitsize="32" value_regnums="20" invalidate_regnums="20"/> 74 <reg name="w21" bitsize="32" value_regnums="21" invalidate_regnums="21"/> 75 <reg name="w22" bitsize="32" value_regnums="22" invalidate_regnums="22"/> 76 <reg name="w23" bitsize="32" value_regnums="23" invalidate_regnums="23"/> 77 <reg name="w24" bitsize="32" value_regnums="24" invalidate_regnums="24"/> 78 <reg name="w25" bitsize="32" value_regnums="25" invalidate_regnums="25"/> 79 <reg name="w26" bitsize="32" value_regnums="26" invalidate_regnums="26"/> 80 <reg name="w27" bitsize="32" value_regnums="27" invalidate_regnums="27"/> 81 <reg name="w28" bitsize="32" value_regnums="28" invalidate_regnums="28"/> 82 </feature> 83 </target> 84 """ 85 ), 86 False, 87 ) 88 else: 89 return (None,) 90 91 def readRegister(self, regnum): 92 return "E01" 93 94 def readRegisters(self): 95 return "20000000000000002000000000000000f0c154bfffff00005daa985a8fea0b48f0b954bfffff0000ad13cce570150b48380000000000000070456abfffff0000a700000000000000000000000000000001010101010101010000000000000000f0c154bfffff00000f2700000000000008e355bfffff0000080e55bfffff0000281041000000000010de61bfffff00005c05000000000000f0c154bfffff000090fcffffffff00008efcffffffff00008ffcffffffff00000000000000000000001000000000000090fcffffffff000000d06cbfffff0000f0c154bfffff00000100000000000000d0b954bfffff0000e407400000000000d0b954bfffff0000e40740000000000000100000" 96 97 98class TestAArch64XMLRegOffsets(GDBRemoteTestBase): 99 @skipIfXmlSupportMissing 100 @skipIfRemote 101 @skipIfLLVMTargetMissing("AArch64") 102 def test_register_gpacket_offsets(self): 103 """ 104 Test that we correctly associate the register info with the eh_frame 105 register numbers. 106 """ 107 108 target = self.createTarget("basic_eh_frame-aarch64.yaml") 109 self.server.responder = MyResponder() 110 111 if self.TraceOn(): 112 self.runCmd("log enable gdb-remote packets") 113 self.addTearDownHook(lambda: self.runCmd("log disable gdb-remote packets")) 114 115 process = self.connect(target) 116 lldbutil.expect_state_changes( 117 self, self.dbg.GetListener(), process, [lldb.eStateStopped] 118 ) 119 120 registerSet = ( 121 process.GetThreadAtIndex(0) 122 .GetFrameAtIndex(0) 123 .GetRegisters() 124 .GetValueAtIndex(0) 125 ) 126 127 reg_val_dict = { 128 "x0": 0x0000000000000020, 129 "x1": 0x0000000000000020, 130 "x2": 0x0000FFFFBF54C1F0, 131 "x3": 0x480BEA8F5A98AA5D, 132 "x4": 0x0000FFFFBF54B9F0, 133 "x5": 0x480B1570E5CC13AD, 134 "x6": 0x0000000000000038, 135 "x7": 0x0000FFFFBF6A4570, 136 "x8": 0x00000000000000A7, 137 "x9": 0x0000000000000000, 138 "x10": 0x0101010101010101, 139 "x11": 0x0000000000000000, 140 "x12": 0x0000FFFFBF54C1F0, 141 "x13": 0x000000000000270F, 142 "x14": 0x0000FFFFBF55E308, 143 "x15": 0x0000FFFFBF550E08, 144 "x16": 0x0000000000411028, 145 "x17": 0x0000FFFFBF61DE10, 146 "x18": 0x000000000000055C, 147 "x19": 0x0000FFFFBF54C1F0, 148 "x20": 0x0000FFFFFFFFFC90, 149 "x21": 0x0000FFFFFFFFFC8E, 150 "x22": 0x0000FFFFFFFFFC8F, 151 "x23": 0x0000000000000000, 152 "x24": 0x0000000000001000, 153 "x25": 0x0000FFFFFFFFFC90, 154 "x26": 0x0000FFFFBF6CD000, 155 "x27": 0x0000FFFFBF54C1F0, 156 "x28": 0x0000000000000001, 157 "x29": 0x0000FFFFBF54B9D0, 158 "x30": 0x00000000004007E4, 159 "sp": 0x0000FFFFBF54B9D0, 160 "pc": 0x00000000004007E4, 161 "cpsr": 0x00001000, 162 "w0": 0x00000020, 163 "w1": 0x00000020, 164 "w2": 0xBF54C1F0, 165 "w3": 0x5A98AA5D, 166 "w4": 0xBF54B9F0, 167 "w5": 0xE5CC13AD, 168 "w6": 0x00000038, 169 "w7": 0xBF6A4570, 170 "w8": 0x000000A7, 171 "w9": 0x00000000, 172 "w10": 0x01010101, 173 "w11": 0x00000000, 174 "w12": 0xBF54C1F0, 175 "w13": 0x0000270F, 176 "w14": 0xBF55E308, 177 "w15": 0xBF550E08, 178 "w16": 0x00411028, 179 "w17": 0xBF61DE10, 180 "w18": 0x0000055C, 181 "w19": 0xBF54C1F0, 182 "w20": 0xFFFFFC90, 183 "w21": 0xFFFFFC8E, 184 "w22": 0xFFFFFC8F, 185 "w23": 0x00000000, 186 "w24": 0x00001000, 187 "w25": 0xFFFFFC90, 188 "w26": 0xBF6CD000, 189 "w27": 0xBF54C1F0, 190 "w28": 0x00000001, 191 } 192 193 for reg in registerSet: 194 self.assertEqual(reg.GetValueAsUnsigned(), reg_val_dict[reg.GetName()]) 195