xref: /llvm-project/lldb/examples/python/armv7_cortex_m_target_defintion.py (revision 586114510c5fa71d1377c7f53e68a3b12c472aa2) 
1#!/usr/bin/env python
2# ===-- armv7_cortex_m_target_definition.py.py ------------------*- C++ -*-===//
3#
4#                     The LLVM Compiler Infrastructure
5#
6# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
7# See https://llvm.org/LICENSE.txt for license information.
8# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9#
10# ===----------------------------------------------------------------------===//
11
12# ----------------------------------------------------------------------
13# DESCRIPTION
14#
15# This file can be used with the following setting:
16#   plugin.process.gdb-remote.target-definition-file
17# This setting should be used when you are trying to connect to a
18# remote GDB server that doesn't support any of the register discovery
19# packets that LLDB normally uses.
20#
21# Why is this necessary? LLDB doesn't require a new build of LLDB that
22# targets each new architecture you will debug with. Instead, all
23# architectures are supported and LLDB relies on extra GDB server
24# packets to discover the target we are connecting to so that is can
25# show the right registers for each target. This allows the GDB server
26# to change and add new registers without requiring a new LLDB build
27# just so we can see new registers.
28#
29# This file implements the x86_64 registers for the darwin version of
30# GDB and allows you to connect to servers that use this register set.
31#
32# USAGE
33#
34# (lldb) settings set plugin.process.gdb-remote.target-definition-file /path/to/armv7_cortex_m_target_definition.py
35# (lldb) gdb-remote other.baz.com:1234
36#
37# The target definition file will get used if and only if the
38# qRegisterInfo packets are not supported when connecting to a remote
39# GDB server.
40# ----------------------------------------------------------------------
41
42from lldb import *
43
44# DWARF register numbers
45name_to_dwarf_regnum = {
46    "r0": 0,
47    "r1": 1,
48    "r2": 2,
49    "r3": 3,
50    "r4": 4,
51    "r5": 5,
52    "r6": 6,
53    "r7": 7,
54    "r9": 8,
55    "r10": 9,
56    "r11": 10,
57    "r12": 11,
58    "sp": 12,
59    "lr": 13,
60    "pc": 14,
61    "r15": 15,
62    "xpsr": 16,
63}
64
65name_to_generic_regnum = {
66    "pc": LLDB_REGNUM_GENERIC_PC,
67    "sp": LLDB_REGNUM_GENERIC_SP,
68    "r7": LLDB_REGNUM_GENERIC_FP,
69    "lr": LLDB_REGNUM_GENERIC_RA,
70    "r0": LLDB_REGNUM_GENERIC_ARG1,
71    "r1": LLDB_REGNUM_GENERIC_ARG2,
72    "r2": LLDB_REGNUM_GENERIC_ARG3,
73    "r3": LLDB_REGNUM_GENERIC_ARG4,
74}
75
76
77def get_reg_num(reg_num_dict, reg_name):
78    if reg_name in reg_num_dict:
79        return reg_num_dict[reg_name]
80    return LLDB_INVALID_REGNUM
81
82
83def get_reg_num(reg_num_dict, reg_name):
84    if reg_name in reg_num_dict:
85        return reg_num_dict[reg_name]
86    return LLDB_INVALID_REGNUM
87
88
89armv7_register_infos = [
90    {
91        "name": "r0",
92        "set": 0,
93        "bitsize": 32,
94        "encoding": eEncodingUint,
95        "format": eFormatAddressInfo,
96        "alt-name": "arg1",
97    },
98    {
99        "name": "r1",
100        "set": 0,
101        "bitsize": 32,
102        "encoding": eEncodingUint,
103        "format": eFormatAddressInfo,
104        "alt-name": "arg2",
105    },
106    {
107        "name": "r2",
108        "set": 0,
109        "bitsize": 32,
110        "encoding": eEncodingUint,
111        "format": eFormatAddressInfo,
112        "alt-name": "arg3",
113    },
114    {
115        "name": "r3",
116        "set": 0,
117        "bitsize": 32,
118        "encoding": eEncodingUint,
119        "format": eFormatAddressInfo,
120        "alt-name": "arg4",
121    },
122    {
123        "name": "r4",
124        "set": 0,
125        "bitsize": 32,
126        "encoding": eEncodingUint,
127        "format": eFormatAddressInfo,
128    },
129    {
130        "name": "r5",
131        "set": 0,
132        "bitsize": 32,
133        "encoding": eEncodingUint,
134        "format": eFormatAddressInfo,
135    },
136    {
137        "name": "r6",
138        "set": 0,
139        "bitsize": 32,
140        "encoding": eEncodingUint,
141        "format": eFormatAddressInfo,
142    },
143    {
144        "name": "r7",
145        "set": 0,
146        "bitsize": 32,
147        "encoding": eEncodingUint,
148        "format": eFormatAddressInfo,
149        "alt-name": "fp",
150    },
151    {
152        "name": "r8",
153        "set": 0,
154        "bitsize": 32,
155        "encoding": eEncodingUint,
156        "format": eFormatAddressInfo,
157    },
158    {
159        "name": "r9",
160        "set": 0,
161        "bitsize": 32,
162        "encoding": eEncodingUint,
163        "format": eFormatAddressInfo,
164    },
165    {
166        "name": "r10",
167        "set": 0,
168        "bitsize": 32,
169        "encoding": eEncodingUint,
170        "format": eFormatAddressInfo,
171    },
172    {
173        "name": "r11",
174        "set": 0,
175        "bitsize": 32,
176        "encoding": eEncodingUint,
177        "format": eFormatAddressInfo,
178    },
179    {
180        "name": "r12",
181        "set": 0,
182        "bitsize": 32,
183        "encoding": eEncodingUint,
184        "format": eFormatAddressInfo,
185    },
186    {
187        "name": "sp",
188        "set": 0,
189        "bitsize": 32,
190        "encoding": eEncodingUint,
191        "format": eFormatAddressInfo,
192        "alt-name": "r13",
193    },
194    {
195        "name": "lr",
196        "set": 0,
197        "bitsize": 32,
198        "encoding": eEncodingUint,
199        "format": eFormatAddressInfo,
200        "alt-name": "r14",
201    },
202    {
203        "name": "pc",
204        "set": 0,
205        "bitsize": 32,
206        "encoding": eEncodingUint,
207        "format": eFormatAddressInfo,
208        "alt-name": "r15",
209    },
210    {
211        "name": "xpsr",
212        "set": 0,
213        "bitsize": 32,
214        "encoding": eEncodingUint,
215        "format": eFormatAddressInfo,
216        "alt-name": "cpsr",
217    },
218]
219
220g_target_definition = None
221
222
223def get_target_definition():
224    global g_target_definition
225    if g_target_definition is None:
226        g_target_definition = {}
227        offset = 0
228        for reg_info in armv7_register_infos:
229            reg_name = reg_info["name"]
230
231            if "slice" not in reg_info and "composite" not in reg_info:
232                reg_info["offset"] = offset
233                offset += reg_info["bitsize"] / 8
234
235            # Set the DWARF/eh_frame register number for this register if it has one
236            reg_num = get_reg_num(name_to_dwarf_regnum, reg_name)
237            if reg_num != LLDB_INVALID_REGNUM:
238                reg_info["gcc"] = reg_num
239                reg_info["ehframe"] = reg_num
240
241            # Set the generic register number for this register if it has one
242            reg_num = get_reg_num(name_to_generic_regnum, reg_name)
243            if reg_num != LLDB_INVALID_REGNUM:
244                reg_info["generic"] = reg_num
245
246        g_target_definition["sets"] = ["General Purpose Registers"]
247        g_target_definition["registers"] = armv7_register_infos
248        g_target_definition["host-info"] = {
249            "triple": "armv7em--",
250            "endian": eByteOrderLittle,
251        }
252        g_target_definition["g-packet-size"] = offset
253    return g_target_definition
254
255
256def get_dynamic_setting(target, setting_name):
257    if setting_name == "gdb-server-target-definition":
258        return get_target_definition()
259