1 //===-- Hexagon.cpp -------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/Support/Endian.h" 16 17 using namespace llvm; 18 using namespace llvm::object; 19 using namespace llvm::support::endian; 20 using namespace llvm::ELF; 21 using namespace lld; 22 using namespace lld::elf; 23 24 namespace { 25 class Hexagon final : public TargetInfo { 26 public: 27 Hexagon(Ctx &); 28 uint32_t calcEFlags() const override; 29 RelExpr getRelExpr(RelType type, const Symbol &s, 30 const uint8_t *loc) const override; 31 RelType getDynRel(RelType type) const override; 32 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 33 void relocate(uint8_t *loc, const Relocation &rel, 34 uint64_t val) const override; 35 void writePltHeader(uint8_t *buf) const override; 36 void writePlt(uint8_t *buf, const Symbol &sym, 37 uint64_t pltEntryAddr) const override; 38 }; 39 } // namespace 40 41 Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) { 42 pltRel = R_HEX_JMP_SLOT; 43 relativeRel = R_HEX_RELATIVE; 44 gotRel = R_HEX_GLOB_DAT; 45 symbolicRel = R_HEX_32; 46 47 gotBaseSymInGotPlt = true; 48 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The 49 // next 3 are reserved for the dynamic loader. 50 gotPltHeaderEntriesNum = 4; 51 52 pltEntrySize = 16; 53 pltHeaderSize = 32; 54 55 // Hexagon Linux uses 64K pages by default. 56 defaultMaxPageSize = 0x10000; 57 tlsGotRel = R_HEX_TPREL_32; 58 tlsModuleIndexRel = R_HEX_DTPMOD_32; 59 tlsOffsetRel = R_HEX_DTPREL_32; 60 } 61 62 uint32_t Hexagon::calcEFlags() const { 63 // The architecture revision must always be equal to or greater than 64 // greatest revision in the list of inputs. 65 std::optional<uint32_t> ret; 66 for (InputFile *f : ctx.objectFiles) { 67 uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags; 68 if (!ret || eflags > *ret) 69 ret = eflags; 70 } 71 return ret.value_or(/* Default Arch Rev: */ 0x60); 72 } 73 74 static uint32_t applyMask(uint32_t mask, uint32_t data) { 75 uint32_t result = 0; 76 size_t off = 0; 77 78 for (size_t bit = 0; bit != 32; ++bit) { 79 uint32_t valBit = (data >> off) & 1; 80 uint32_t maskBit = (mask >> bit) & 1; 81 if (maskBit) { 82 result |= (valBit << bit); 83 ++off; 84 } 85 } 86 return result; 87 } 88 89 RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s, 90 const uint8_t *loc) const { 91 switch (type) { 92 case R_HEX_NONE: 93 return R_NONE; 94 case R_HEX_6_X: 95 case R_HEX_8_X: 96 case R_HEX_9_X: 97 case R_HEX_10_X: 98 case R_HEX_11_X: 99 case R_HEX_12_X: 100 case R_HEX_16_X: 101 case R_HEX_32: 102 case R_HEX_32_6_X: 103 case R_HEX_HI16: 104 case R_HEX_LO16: 105 case R_HEX_DTPREL_32: 106 return R_ABS; 107 case R_HEX_B9_PCREL: 108 case R_HEX_B13_PCREL: 109 case R_HEX_B15_PCREL: 110 case R_HEX_6_PCREL_X: 111 case R_HEX_32_PCREL: 112 return R_PC; 113 case R_HEX_B9_PCREL_X: 114 case R_HEX_B15_PCREL_X: 115 case R_HEX_B22_PCREL: 116 case R_HEX_PLT_B22_PCREL: 117 case R_HEX_B22_PCREL_X: 118 case R_HEX_B32_PCREL_X: 119 case R_HEX_GD_PLT_B22_PCREL: 120 case R_HEX_GD_PLT_B22_PCREL_X: 121 case R_HEX_GD_PLT_B32_PCREL_X: 122 return R_PLT_PC; 123 case R_HEX_IE_32_6_X: 124 case R_HEX_IE_16_X: 125 case R_HEX_IE_HI16: 126 case R_HEX_IE_LO16: 127 return R_GOT; 128 case R_HEX_GD_GOT_11_X: 129 case R_HEX_GD_GOT_16_X: 130 case R_HEX_GD_GOT_32_6_X: 131 return R_TLSGD_GOTPLT; 132 case R_HEX_GOTREL_11_X: 133 case R_HEX_GOTREL_16_X: 134 case R_HEX_GOTREL_32_6_X: 135 case R_HEX_GOTREL_HI16: 136 case R_HEX_GOTREL_LO16: 137 return R_GOTPLTREL; 138 case R_HEX_GOT_11_X: 139 case R_HEX_GOT_16_X: 140 case R_HEX_GOT_32_6_X: 141 return R_GOTPLT; 142 case R_HEX_IE_GOT_11_X: 143 case R_HEX_IE_GOT_16_X: 144 case R_HEX_IE_GOT_32_6_X: 145 case R_HEX_IE_GOT_HI16: 146 case R_HEX_IE_GOT_LO16: 147 return R_GOTPLT; 148 case R_HEX_TPREL_11_X: 149 case R_HEX_TPREL_16: 150 case R_HEX_TPREL_16_X: 151 case R_HEX_TPREL_32_6_X: 152 case R_HEX_TPREL_HI16: 153 case R_HEX_TPREL_LO16: 154 return R_TPREL; 155 default: 156 Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v 157 << ") against symbol " << &s; 158 return R_NONE; 159 } 160 } 161 162 // There are (arguably too) many relocation masks for the DSP's 163 // R_HEX_6_X type. The table below is used to select the correct mask 164 // for the given instruction. 165 struct InstructionMask { 166 uint32_t cmpMask; 167 uint32_t relocMask; 168 }; 169 static const InstructionMask r6[] = { 170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f}, 171 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80}, 172 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0}, 173 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0}, 174 {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0}, 175 {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0}, 176 {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000}, 177 {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60}, 178 {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60}, 179 {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f}, 180 {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078}, 181 {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0}, 182 {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}}; 183 184 constexpr uint32_t instParsePacketEnd = 0x0000c000; 185 186 static bool isDuplex(uint32_t insn) { 187 // Duplex forms have a fixed mask and parse bits 15:14 are always 188 // zero. Non-duplex insns will always have at least one bit set in the 189 // parse field. 190 return (instParsePacketEnd & insn) == 0; 191 } 192 193 static uint32_t findMaskR6(Ctx &ctx, uint32_t insn) { 194 if (isDuplex(insn)) 195 return 0x03f00000; 196 197 for (InstructionMask i : r6) 198 if ((0xff000000 & insn) == i.cmpMask) 199 return i.relocMask; 200 201 Err(ctx) << "unrecognized instruction for 6_X relocation: 0x" 202 << utohexstr(insn, true); 203 return 0; 204 } 205 206 static uint32_t findMaskR8(uint32_t insn) { 207 if ((0xff000000 & insn) == 0xde000000) 208 return 0x00e020e8; 209 if ((0xff000000 & insn) == 0x3c000000) 210 return 0x0000207f; 211 return 0x00001fe0; 212 } 213 214 static uint32_t findMaskR11(uint32_t insn) { 215 if ((0xff000000 & insn) == 0xa1000000) 216 return 0x060020ff; 217 return 0x06003fe0; 218 } 219 220 static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) { 221 if (isDuplex(insn)) 222 return 0x03f00000; 223 224 // Clear the end-packet-parse bits: 225 insn = insn & ~instParsePacketEnd; 226 227 if ((0xff000000 & insn) == 0x48000000) 228 return 0x061f20ff; 229 if ((0xff000000 & insn) == 0x49000000) 230 return 0x061f3fe0; 231 if ((0xff000000 & insn) == 0x78000000) 232 return 0x00df3fe0; 233 if ((0xff000000 & insn) == 0xb0000000) 234 return 0x0fe03fe0; 235 236 if ((0xff802000 & insn) == 0x74000000) 237 return 0x00001fe0; 238 if ((0xff802000 & insn) == 0x74002000) 239 return 0x00001fe0; 240 if ((0xff802000 & insn) == 0x74800000) 241 return 0x00001fe0; 242 if ((0xff802000 & insn) == 0x74802000) 243 return 0x00001fe0; 244 245 for (InstructionMask i : r6) 246 if ((0xff000000 & insn) == i.cmpMask) 247 return i.relocMask; 248 249 Err(ctx) << "unrecognized instruction for 16_X type: 0x" << utohexstr(insn); 250 return 0; 251 } 252 253 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } 254 255 void Hexagon::relocate(uint8_t *loc, const Relocation &rel, 256 uint64_t val) const { 257 switch (rel.type) { 258 case R_HEX_NONE: 259 break; 260 case R_HEX_6_PCREL_X: 261 case R_HEX_6_X: 262 or32le(loc, applyMask(findMaskR6(ctx, read32le(loc)), val)); 263 break; 264 case R_HEX_8_X: 265 or32le(loc, applyMask(findMaskR8(read32le(loc)), val)); 266 break; 267 case R_HEX_9_X: 268 or32le(loc, applyMask(0x00003fe0, val & 0x3f)); 269 break; 270 case R_HEX_10_X: 271 or32le(loc, applyMask(0x00203fe0, val & 0x3f)); 272 break; 273 case R_HEX_11_X: 274 case R_HEX_GD_GOT_11_X: 275 case R_HEX_IE_GOT_11_X: 276 case R_HEX_GOT_11_X: 277 case R_HEX_GOTREL_11_X: 278 case R_HEX_TPREL_11_X: 279 or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f)); 280 break; 281 case R_HEX_12_X: 282 or32le(loc, applyMask(0x000007e0, val)); 283 break; 284 case R_HEX_16_X: // These relocs only have 6 effective bits. 285 case R_HEX_IE_16_X: 286 case R_HEX_IE_GOT_16_X: 287 case R_HEX_GD_GOT_16_X: 288 case R_HEX_GOT_16_X: 289 case R_HEX_GOTREL_16_X: 290 case R_HEX_TPREL_16_X: 291 or32le(loc, applyMask(findMaskR16(ctx, read32le(loc)), val & 0x3f)); 292 break; 293 case R_HEX_TPREL_16: 294 or32le(loc, applyMask(findMaskR16(ctx, read32le(loc)), val & 0xffff)); 295 break; 296 case R_HEX_32: 297 case R_HEX_32_PCREL: 298 case R_HEX_DTPREL_32: 299 or32le(loc, val); 300 break; 301 case R_HEX_32_6_X: 302 case R_HEX_GD_GOT_32_6_X: 303 case R_HEX_GOT_32_6_X: 304 case R_HEX_GOTREL_32_6_X: 305 case R_HEX_IE_GOT_32_6_X: 306 case R_HEX_IE_32_6_X: 307 case R_HEX_TPREL_32_6_X: 308 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 309 break; 310 case R_HEX_B9_PCREL: 311 checkInt(ctx, loc, val, 11, rel); 312 or32le(loc, applyMask(0x003000fe, val >> 2)); 313 break; 314 case R_HEX_B9_PCREL_X: 315 or32le(loc, applyMask(0x003000fe, val & 0x3f)); 316 break; 317 case R_HEX_B13_PCREL: 318 checkInt(ctx, loc, val, 15, rel); 319 or32le(loc, applyMask(0x00202ffe, val >> 2)); 320 break; 321 case R_HEX_B15_PCREL: 322 checkInt(ctx, loc, val, 17, rel); 323 or32le(loc, applyMask(0x00df20fe, val >> 2)); 324 break; 325 case R_HEX_B15_PCREL_X: 326 or32le(loc, applyMask(0x00df20fe, val & 0x3f)); 327 break; 328 case R_HEX_B22_PCREL: 329 case R_HEX_GD_PLT_B22_PCREL: 330 case R_HEX_PLT_B22_PCREL: 331 checkInt(ctx, loc, val, 24, rel); 332 or32le(loc, applyMask(0x1ff3ffe, val >> 2)); 333 break; 334 case R_HEX_B22_PCREL_X: 335 case R_HEX_GD_PLT_B22_PCREL_X: 336 or32le(loc, applyMask(0x1ff3ffe, val & 0x3f)); 337 break; 338 case R_HEX_B32_PCREL_X: 339 case R_HEX_GD_PLT_B32_PCREL_X: 340 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 341 break; 342 case R_HEX_GOTREL_HI16: 343 case R_HEX_HI16: 344 case R_HEX_IE_GOT_HI16: 345 case R_HEX_IE_HI16: 346 case R_HEX_TPREL_HI16: 347 or32le(loc, applyMask(0x00c03fff, val >> 16)); 348 break; 349 case R_HEX_GOTREL_LO16: 350 case R_HEX_LO16: 351 case R_HEX_IE_GOT_LO16: 352 case R_HEX_IE_LO16: 353 case R_HEX_TPREL_LO16: 354 or32le(loc, applyMask(0x00c03fff, val)); 355 break; 356 default: 357 llvm_unreachable("unknown relocation"); 358 } 359 } 360 361 void Hexagon::writePltHeader(uint8_t *buf) const { 362 const uint8_t pltData[] = { 363 0x00, 0x40, 0x00, 0x00, // { immext (#0) 364 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0 365 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn 366 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2 367 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1 368 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn 369 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker 370 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment 371 }; 372 memcpy(buf, pltData, sizeof(pltData)); 373 374 // Offset from PLT0 to the GOT. 375 uint64_t off = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA(); 376 relocateNoSym(buf, R_HEX_B32_PCREL_X, off); 377 relocateNoSym(buf + 4, R_HEX_6_PCREL_X, off); 378 } 379 380 void Hexagon::writePlt(uint8_t *buf, const Symbol &sym, 381 uint64_t pltEntryAddr) const { 382 const uint8_t inst[] = { 383 0x00, 0x40, 0x00, 0x00, // { immext (#0) 384 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) } 385 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14) 386 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 387 }; 388 memcpy(buf, inst, sizeof(inst)); 389 390 uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx); 391 relocateNoSym(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr); 392 relocateNoSym(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr); 393 } 394 395 RelType Hexagon::getDynRel(RelType type) const { 396 if (type == R_HEX_32) 397 return type; 398 return R_HEX_NONE; 399 } 400 401 int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const { 402 switch (type) { 403 case R_HEX_NONE: 404 case R_HEX_GLOB_DAT: 405 case R_HEX_JMP_SLOT: 406 return 0; 407 case R_HEX_32: 408 case R_HEX_RELATIVE: 409 case R_HEX_DTPMOD_32: 410 case R_HEX_DTPREL_32: 411 case R_HEX_TPREL_32: 412 return SignExtend64<32>(read32(ctx, buf)); 413 default: 414 InternalErr(ctx, buf) << "cannot read addend for relocation " << type; 415 return 0; 416 } 417 } 418 419 void elf::setHexagonTargetInfo(Ctx &ctx) { ctx.target.reset(new Hexagon(ctx)); } 420