1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 // Check that the PowerPC vector registers are restored properly during
10 // unwinding.
11
12 // REQUIRES: target=powerpc{{(64)?}}le-unknown-linux-gnu
13 // UNSUPPORTED: no-exceptions
14
15 // Callee-saved VSR's 62 and 63 (vr30, vr31 respectively) are set to 16 bytes
16 // with values 1, 2 respectively in main. In order to ensure the two doublewords
17 // in each register are different, they are merged. Then they are reset to 16
18 // bytes with values 9 and 12 respectively in a callee and an exception is
19 // thrown. When catching an exception in main, the values in the two registers
20 // need to be the original ones (including the correct doubleword order).
21
22 #include <cassert>
23 #include <cstdlib>
24
test2(int i)25 int __attribute__((noinline)) test2(int i) {
26 if (i > 3)
27 throw i;
28 srand(i);
29 return rand();
30 }
31
test(int i)32 int __attribute__((noinline)) test(int i) {
33 // Clobber VS63 and VS62 in the function body.
34 // Set VS63 to 16 bytes each with value 9
35 asm volatile("vspltisb 31, 9" : : : "v31");
36
37 // Set VS62 to 16 bytes each with value 12
38 asm volatile("vspltisb 30, 12" : : : "v30");
39 return test2(i);
40 }
41
42 #define cmpVS63(vec, result) \
43 { \
44 vector unsigned char gbg; \
45 asm volatile("vcmpequb. %[gbg], 31, %[veca];" \
46 "mfocrf %[res], 2;" \
47 "rlwinm %[res], %[res], 25, 31, 31" \
48 : [res] "=r"(result), [gbg] "=v"(gbg) \
49 : [veca] "v"(vec) \
50 : "cr6"); \
51 }
52
53 #define cmpVS62(vec, result) \
54 { \
55 vector unsigned char gbg; \
56 asm volatile("vcmpequb. %[gbg], 30, %[veca];" \
57 "mfocrf %[res], 2;" \
58 "rlwinm %[res], %[res], 25, 31, 31" \
59 : [res] "=r"(result), [gbg] "=v"(gbg) \
60 : [veca] "v"(vec) \
61 : "cr6"); \
62 }
63
main(int,char **)64 int main(int, char **) {
65 // Set VS63 to 16 bytes each with value 1.
66 asm volatile("vspltisb 31, 1" : : : "v31");
67
68 // Set VS62 to 16 bytes each with value 2.
69 asm volatile("vspltisb 30, 2" : : : "v30");
70
71 // Mix doublewords for both VS62 and VS63.
72 asm volatile("xxmrghd 63, 63, 62");
73 asm volatile("xxmrghd 62, 63, 62");
74
75 vector unsigned long long expectedVS63Value = {0x202020202020202,
76 0x101010101010101};
77 vector unsigned long long expectedVS62Value = {0x202020202020202,
78 0x101010101010101};
79 try {
80 test(4);
81 } catch (int num) {
82 // If the unwinder restores VS63 and VS62 correctly, they should contain
83 // 0x01's and 0x02's respectively instead of 0x09's and 0x12's.
84 bool isEqualVS63, isEqualVS62;
85 cmpVS63(expectedVS63Value, isEqualVS63);
86 cmpVS62(expectedVS62Value, isEqualVS62);
87 assert(isEqualVS63 && isEqualVS62);
88 }
89 return 0;
90 }
91