1! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s 2! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s 3! REQUIRES: target=powerpc{{.*}} 4 5!---------------------- 6! vec_sl 7!---------------------- 8 9! CHECK-LABEL: vec_sl_i1 10subroutine vec_sl_i1(arg1, arg2) 11 vector(integer(1)) :: arg1, r 12 vector(unsigned(1)) :: arg2 13 r = vec_sl(arg1, arg2) 14 15! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 16! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 17! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8) 18! LLVMIR: %7 = shl <16 x i8> %[[arg1]], %[[msk]] 19end subroutine vec_sl_i1 20 21! CHECK-LABEL: vec_sl_i2 22subroutine vec_sl_i2(arg1, arg2) 23 vector(integer(2)) :: arg1, r 24 vector(unsigned(2)) :: arg2 25 r = vec_sl(arg1, arg2) 26 27! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 28! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 29! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16) 30! LLVMIR: %7 = shl <8 x i16> %[[arg1]], %[[msk]] 31end subroutine vec_sl_i2 32 33! CHECK-LABEL: vec_sl_i4 34subroutine vec_sl_i4(arg1, arg2) 35 vector(integer(4)) :: arg1, r 36 vector(unsigned(4)) :: arg2 37 r = vec_sl(arg1, arg2) 38 39! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 40! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 41! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32) 42! LLVMIR: %7 = shl <4 x i32> %[[arg1]], %[[msk]] 43end subroutine vec_sl_i4 44 45! CHECK-LABEL: vec_sl_i8 46subroutine vec_sl_i8(arg1, arg2) 47 vector(integer(8)) :: arg1, r 48 vector(unsigned(8)) :: arg2 49 r = vec_sl(arg1, arg2) 50 51! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 52! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 53! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64) 54! LLVMIR: %7 = shl <2 x i64> %[[arg1]], %[[msk]] 55end subroutine vec_sl_i8 56 57! CHECK-LABEL: vec_sl_u1 58subroutine vec_sl_u1(arg1, arg2) 59 vector(unsigned(1)) :: arg1, r 60 vector(unsigned(1)) :: arg2 61 r = vec_sl(arg1, arg2) 62 63! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 64! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 65! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8) 66! LLVMIR: %7 = shl <16 x i8> %[[arg1]], %[[msk]] 67end subroutine vec_sl_u1 68 69! CHECK-LABEL: vec_sl_u2 70subroutine vec_sl_u2(arg1, arg2) 71 vector(unsigned(2)) :: arg1, r 72 vector(unsigned(2)) :: arg2 73 r = vec_sl(arg1, arg2) 74 75! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 76! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 77! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16) 78! LLVMIR: %7 = shl <8 x i16> %[[arg1]], %[[msk]] 79end subroutine vec_sl_u2 80 81! CHECK-LABEL: vec_sl_u4 82subroutine vec_sl_u4(arg1, arg2) 83 vector(unsigned(4)) :: arg1, r 84 vector(unsigned(4)) :: arg2 85 r = vec_sl(arg1, arg2) 86 87! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 88! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 89! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32) 90! LLVMIR: %7 = shl <4 x i32> %[[arg1]], %[[msk]] 91end subroutine vec_sl_u4 92 93! CHECK-LABEL: vec_sl_u8 94subroutine vec_sl_u8(arg1, arg2) 95 vector(unsigned(8)) :: arg1, r 96 vector(unsigned(8)) :: arg2 97 r = vec_sl(arg1, arg2) 98 99! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 100! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 101! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64) 102! LLVMIR: %{{[0-9]+}} = shl <2 x i64> %[[arg1]], %[[msk]] 103end subroutine vec_sl_u8 104 105!---------------------- 106! vec_sll 107!---------------------- 108! CHECK-LABEL: vec_sll_i1u1 109subroutine vec_sll_i1u1(arg1, arg2) 110 vector(integer(1)) :: arg1, r 111 vector(unsigned(1)) :: arg2 112 r = vec_sll(arg1, arg2) 113 114! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 115! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 116! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 117! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 118! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 119! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 120end subroutine vec_sll_i1u1 121 122! CHECK-LABEL: vec_sll_i2u1 123subroutine vec_sll_i2u1(arg1, arg2) 124 vector(integer(2)) :: arg1, r 125 vector(unsigned(1)) :: arg2 126 r = vec_sll(arg1, arg2) 127 128! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 129! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 130! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 131! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 132! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 133! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 134end subroutine vec_sll_i2u1 135 136! CHECK-LABEL: vec_sll_i4u1 137subroutine vec_sll_i4u1(arg1, arg2) 138 vector(integer(4)) :: arg1, r 139 vector(unsigned(1)) :: arg2 140 r = vec_sll(arg1, arg2) 141 142! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 143! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 144! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 145! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 146end subroutine vec_sll_i4u1 147 148! CHECK-LABEL: vec_sll_i1u2 149subroutine vec_sll_i1u2(arg1, arg2) 150 vector(integer(1)) :: arg1, r 151 vector(unsigned(2)) :: arg2 152 r = vec_sll(arg1, arg2) 153 154! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 155! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 156! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 157! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 158! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 159! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 160end subroutine vec_sll_i1u2 161 162! CHECK-LABEL: vec_sll_i2u2 163subroutine vec_sll_i2u2(arg1, arg2) 164 vector(integer(2)) :: arg1, r 165 vector(unsigned(2)) :: arg2 166 r = vec_sll(arg1, arg2) 167 168! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 169! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 170! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 171! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 172! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 173! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 174end subroutine vec_sll_i2u2 175 176! CHECK-LABEL: vec_sll_i4u2 177subroutine vec_sll_i4u2(arg1, arg2) 178 vector(integer(4)) :: arg1, r 179 vector(unsigned(2)) :: arg2 180 r = vec_sll(arg1, arg2) 181 182! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 183! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 184! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 185! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 186end subroutine vec_sll_i4u2 187 188! CHECK-LABEL: vec_sll_i1u4 189subroutine vec_sll_i1u4(arg1, arg2) 190 vector(integer(1)) :: arg1, r 191 vector(unsigned(4)) :: arg2 192 r = vec_sll(arg1, arg2) 193 194! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 195! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 196! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 197! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 198! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 199end subroutine vec_sll_i1u4 200 201! CHECK-LABEL: vec_sll_i2u4 202subroutine vec_sll_i2u4(arg1, arg2) 203 vector(integer(2)) :: arg1, r 204 vector(unsigned(4)) :: arg2 205 r = vec_sll(arg1, arg2) 206 207! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 208! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 209! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 210! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 211! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 212end subroutine vec_sll_i2u4 213 214! CHECK-LABEL: vec_sll_i4u4 215subroutine vec_sll_i4u4(arg1, arg2) 216 vector(integer(4)) :: arg1, r 217 vector(unsigned(4)) :: arg2 218 r = vec_sll(arg1, arg2) 219 220! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 221! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 222! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]]) 223end subroutine vec_sll_i4u4 224 225! CHECK-LABEL: vec_sll_u1u1 226subroutine vec_sll_u1u1(arg1, arg2) 227 vector(unsigned(1)) :: arg1, r 228 vector(unsigned(1)) :: arg2 229 r = vec_sll(arg1, arg2) 230 231! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 232! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 233! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 234! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 235! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 236! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 237end subroutine vec_sll_u1u1 238 239! CHECK-LABEL: vec_sll_u2u1 240subroutine vec_sll_u2u1(arg1, arg2) 241 vector(unsigned(2)) :: arg1, r 242 vector(unsigned(1)) :: arg2 243 r = vec_sll(arg1, arg2) 244 245! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 246! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 247! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 248! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 249! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 250! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 251end subroutine vec_sll_u2u1 252 253! CHECK-LABEL: vec_sll_u4u1 254subroutine vec_sll_u4u1(arg1, arg2) 255 vector(unsigned(4)) :: arg1, r 256 vector(unsigned(1)) :: arg2 257 r = vec_sll(arg1, arg2) 258 259! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 260! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 261! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 262! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 263end subroutine vec_sll_u4u1 264 265! CHECK-LABEL: vec_sll_u1u2 266subroutine vec_sll_u1u2(arg1, arg2) 267 vector(unsigned(1)) :: arg1, r 268 vector(unsigned(2)) :: arg2 269 r = vec_sll(arg1, arg2) 270 271! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 272! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 273! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 274! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 275! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 276! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 277end subroutine vec_sll_u1u2 278 279! CHECK-LABEL: vec_sll_u2u2 280subroutine vec_sll_u2u2(arg1, arg2) 281 vector(unsigned(2)) :: arg1, r 282 vector(unsigned(2)) :: arg2 283 r = vec_sll(arg1, arg2) 284 285! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 286! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 287! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 288! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 289! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 290! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 291end subroutine vec_sll_u2u2 292 293! CHECK-LABEL: vec_sll_u4u2 294subroutine vec_sll_u4u2(arg1, arg2) 295 vector(unsigned(4)) :: arg1, r 296 vector(unsigned(2)) :: arg2 297 r = vec_sll(arg1, arg2) 298 299! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 300! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 301! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 302! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 303end subroutine vec_sll_u4u2 304 305! CHECK-LABEL: vec_sll_u1u4 306subroutine vec_sll_u1u4(arg1, arg2) 307 vector(unsigned(1)) :: arg1, r 308 vector(unsigned(4)) :: arg2 309 r = vec_sll(arg1, arg2) 310 311! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 312! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 313! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 314! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 315! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 316end subroutine vec_sll_u1u4 317 318! CHECK-LABEL: vec_sll_u2u4 319subroutine vec_sll_u2u4(arg1, arg2) 320 vector(unsigned(2)) :: arg1, r 321 vector(unsigned(4)) :: arg2 322 r = vec_sll(arg1, arg2) 323 324! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 325! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 326! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 327! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 328! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 329end subroutine vec_sll_u2u4 330 331! CHECK-LABEL: vec_sll_u4u4 332subroutine vec_sll_u4u4(arg1, arg2) 333 vector(unsigned(4)) :: arg1, r 334 vector(unsigned(4)) :: arg2 335 r = vec_sll(arg1, arg2) 336 337! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 338! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 339! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsl(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]]) 340end subroutine vec_sll_u4u4 341 342!---------------------- 343! vec_slo 344!---------------------- 345 346! CHECK-LABEL: vec_slo_i1u1 347subroutine vec_slo_i1u1(arg1, arg2) 348 vector(integer(1)) :: arg1, r 349 vector(unsigned(1)) :: arg2 350 r = vec_slo(arg1, arg2) 351 352! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 353! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 354! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 355! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 356! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 357! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 358end subroutine vec_slo_i1u1 359 360! CHECK-LABEL: vec_slo_i2u1 361subroutine vec_slo_i2u1(arg1, arg2) 362 vector(integer(2)) :: arg1, r 363 vector(unsigned(1)) :: arg2 364 r = vec_slo(arg1, arg2) 365 366! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 367! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 368! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 369! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 370! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 371! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 372end subroutine vec_slo_i2u1 373 374! CHECK-LABEL: vec_slo_i4u1 375subroutine vec_slo_i4u1(arg1, arg2) 376 vector(integer(4)) :: arg1, r 377 vector(unsigned(1)) :: arg2 378 r = vec_slo(arg1, arg2) 379 380! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 381! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 382! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 383! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 384end subroutine vec_slo_i4u1 385 386! CHECK-LABEL: vec_slo_u1u1 387subroutine vec_slo_u1u1(arg1, arg2) 388 vector(unsigned(1)) :: arg1, r 389 vector(unsigned(1)) :: arg2 390 r = vec_slo(arg1, arg2) 391 392! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 393! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 394! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 395! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 396! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 397! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 398end subroutine vec_slo_u1u1 399 400! CHECK-LABEL: vec_slo_u2u1 401subroutine vec_slo_u2u1(arg1, arg2) 402 vector(unsigned(2)) :: arg1, r 403 vector(unsigned(1)) :: arg2 404 r = vec_slo(arg1, arg2) 405 406! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 407! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 408! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 409! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 410! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 411! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 412end subroutine vec_slo_u2u1 413 414! CHECK-LABEL: vec_slo_u4u1 415subroutine vec_slo_u4u1(arg1, arg2) 416 vector(unsigned(4)) :: arg1, r 417 vector(unsigned(1)) :: arg2 418 r = vec_slo(arg1, arg2) 419 420! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 421! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 422! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 423! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 424end subroutine vec_slo_u4u1 425 426! CHECK-LABEL: vec_slo_r4u1 427subroutine vec_slo_r4u1(arg1, arg2) 428 vector(real(4)) :: arg1, r 429 vector(unsigned(1)) :: arg2 430 r = vec_slo(arg1, arg2) 431 432! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16 433! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 434! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32> 435! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 436! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 437! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float> 438end subroutine vec_slo_r4u1 439 440! CHECK-LABEL: vec_slo_i1u2 441subroutine vec_slo_i1u2(arg1, arg2) 442 vector(integer(1)) :: arg1, r 443 vector(unsigned(2)) :: arg2 444 r = vec_slo(arg1, arg2) 445 446! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 447! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 448! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 449! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 450! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 451! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 452end subroutine vec_slo_i1u2 453 454! CHECK-LABEL: vec_slo_i2u2 455subroutine vec_slo_i2u2(arg1, arg2) 456 vector(integer(2)) :: arg1, r 457 vector(unsigned(2)) :: arg2 458 r = vec_slo(arg1, arg2) 459 460! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 461! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 462! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 463! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 464! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 465! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 466end subroutine vec_slo_i2u2 467 468! CHECK-LABEL: vec_slo_i4u2 469subroutine vec_slo_i4u2(arg1, arg2) 470 vector(integer(4)) :: arg1, r 471 vector(unsigned(2)) :: arg2 472 r = vec_slo(arg1, arg2) 473 474! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 475! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 476! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 477! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 478end subroutine vec_slo_i4u2 479 480! CHECK-LABEL: vec_slo_u1u2 481subroutine vec_slo_u1u2(arg1, arg2) 482 vector(unsigned(1)) :: arg1, r 483 vector(unsigned(2)) :: arg2 484 r = vec_slo(arg1, arg2) 485 486! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 487! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 488! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 489! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 490! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 491! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 492end subroutine vec_slo_u1u2 493 494! CHECK-LABEL: vec_slo_u2u2 495subroutine vec_slo_u2u2(arg1, arg2) 496 vector(unsigned(2)) :: arg1, r 497 vector(unsigned(2)) :: arg2 498 r = vec_slo(arg1, arg2) 499 500! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 501! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 502! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 503! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 504! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 505! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 506 507end subroutine vec_slo_u2u2 508 509! CHECK-LABEL: vec_slo_u4u2 510subroutine vec_slo_u4u2(arg1, arg2) 511 vector(unsigned(4)) :: arg1, r 512 vector(unsigned(2)) :: arg2 513 r = vec_slo(arg1, arg2) 514 515! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 516! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 517! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 518! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 519end subroutine vec_slo_u4u2 520 521! CHECK-LABEL: vec_slo_r4u2 522subroutine vec_slo_r4u2(arg1, arg2) 523 vector(real(4)) :: arg1, r 524 vector(unsigned(2)) :: arg2 525 r = vec_slo(arg1, arg2) 526 527! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16 528! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 529! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32> 530! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 531! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vslo(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 532! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float> 533end subroutine vec_slo_r4u2 534 535!---------------------- 536! vec_sr 537!---------------------- 538! CHECK-LABEL: vec_sr_i1 539subroutine vec_sr_i1(arg1, arg2) 540 vector(integer(1)) :: arg1, r 541 vector(unsigned(1)) :: arg2 542 r = vec_sr(arg1, arg2) 543 544! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 545! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 546! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8) 547! LLVMIR: %7 = lshr <16 x i8> %[[arg1]], %[[msk]] 548end subroutine vec_sr_i1 549 550! CHECK-LABEL: vec_sr_i2 551subroutine vec_sr_i2(arg1, arg2) 552 vector(integer(2)) :: arg1, r 553 vector(unsigned(2)) :: arg2 554 r = vec_sr(arg1, arg2) 555 556! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 557! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 558! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16) 559! LLVMIR: %7 = lshr <8 x i16> %[[arg1]], %[[msk]] 560end subroutine vec_sr_i2 561 562! CHECK-LABEL: vec_sr_i4 563subroutine vec_sr_i4(arg1, arg2) 564 vector(integer(4)) :: arg1, r 565 vector(unsigned(4)) :: arg2 566 r = vec_sr(arg1, arg2) 567 568! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 569! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 570! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32) 571! LLVMIR: %7 = lshr <4 x i32> %[[arg1]], %[[msk]] 572end subroutine vec_sr_i4 573 574! CHECK-LABEL: vec_sr_i8 575subroutine vec_sr_i8(arg1, arg2) 576 vector(integer(8)) :: arg1, r 577 vector(unsigned(8)) :: arg2 578 r = vec_sr(arg1, arg2) 579 580! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 581! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 582! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64) 583! LLVMIR: %7 = lshr <2 x i64> %[[arg1]], %[[msk]] 584end subroutine vec_sr_i8 585 586! CHECK-LABEL: vec_sr_u1 587subroutine vec_sr_u1(arg1, arg2) 588 vector(unsigned(1)) :: arg1, r 589 vector(unsigned(1)) :: arg2 590 r = vec_sr(arg1, arg2) 591 592! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 593! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 594! LLVMIR: %[[msk:.*]] = urem <16 x i8> %[[arg2]], splat (i8 8) 595! LLVMIR: %7 = lshr <16 x i8> %[[arg1]], %[[msk]] 596end subroutine vec_sr_u1 597 598! CHECK-LABEL: vec_sr_u2 599subroutine vec_sr_u2(arg1, arg2) 600 vector(unsigned(2)) :: arg1, r 601 vector(unsigned(2)) :: arg2 602 r = vec_sr(arg1, arg2) 603 604! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 605! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 606! LLVMIR: %[[msk:.*]] = urem <8 x i16> %[[arg2]], splat (i16 16) 607! LLVMIR: %7 = lshr <8 x i16> %[[arg1]], %[[msk]] 608end subroutine vec_sr_u2 609 610! CHECK-LABEL: vec_sr_u4 611subroutine vec_sr_u4(arg1, arg2) 612 vector(unsigned(4)) :: arg1, r 613 vector(unsigned(4)) :: arg2 614 r = vec_sr(arg1, arg2) 615 616! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 617! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 618! LLVMIR: %[[msk:.*]] = urem <4 x i32> %[[arg2]], splat (i32 32) 619! LLVMIR: %7 = lshr <4 x i32> %[[arg1]], %[[msk]] 620end subroutine vec_sr_u4 621 622! CHECK-LABEL: vec_sr_u8 623subroutine vec_sr_u8(arg1, arg2) 624 vector(unsigned(8)) :: arg1, r 625 vector(unsigned(8)) :: arg2 626 r = vec_sr(arg1, arg2) 627 628! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 629! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 630! LLVMIR: %[[msk:.*]] = urem <2 x i64> %[[arg2]], splat (i64 64) 631! LLVMIR: %7 = lshr <2 x i64> %[[arg1]], %[[msk]] 632end subroutine vec_sr_u8 633 634!---------------------- 635! vec_srl 636!---------------------- 637! CHECK-LABEL: vec_srl_i1u1 638subroutine vec_srl_i1u1(arg1, arg2) 639 vector(integer(1)) :: arg1, r 640 vector(unsigned(1)) :: arg2 641 r = vec_srl(arg1, arg2) 642 643! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 644! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 645! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 646! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 647! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 648! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 649end subroutine vec_srl_i1u1 650 651! CHECK-LABEL: vec_srl_i2u1 652subroutine vec_srl_i2u1(arg1, arg2) 653 vector(integer(2)) :: arg1, r 654 vector(unsigned(1)) :: arg2 655 r = vec_srl(arg1, arg2) 656 657! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 658! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 659! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 660! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 661! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 662! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 663end subroutine vec_srl_i2u1 664 665! CHECK-LABEL: vec_srl_i4u1 666subroutine vec_srl_i4u1(arg1, arg2) 667 vector(integer(4)) :: arg1, r 668 vector(unsigned(1)) :: arg2 669 r = vec_srl(arg1, arg2) 670 671! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 672! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 673! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 674! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 675end subroutine vec_srl_i4u1 676 677! CHECK-LABEL: vec_srl_i1u2 678subroutine vec_srl_i1u2(arg1, arg2) 679 vector(integer(1)) :: arg1, r 680 vector(unsigned(2)) :: arg2 681 r = vec_srl(arg1, arg2) 682 683! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 684! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 685! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 686! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 687! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 688! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 689end subroutine vec_srl_i1u2 690 691! CHECK-LABEL: vec_srl_i2u2 692subroutine vec_srl_i2u2(arg1, arg2) 693 vector(integer(2)) :: arg1, r 694 vector(unsigned(2)) :: arg2 695 r = vec_srl(arg1, arg2) 696 697! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 698! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 699! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 700! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 701! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 702! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 703end subroutine vec_srl_i2u2 704 705! CHECK-LABEL: vec_srl_i4u2 706subroutine vec_srl_i4u2(arg1, arg2) 707 vector(integer(4)) :: arg1, r 708 vector(unsigned(2)) :: arg2 709 r = vec_srl(arg1, arg2) 710 711! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 712! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 713! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 714! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 715end subroutine vec_srl_i4u2 716 717! CHECK-LABEL: vec_srl_i1u4 718subroutine vec_srl_i1u4(arg1, arg2) 719 vector(integer(1)) :: arg1, r 720 vector(unsigned(4)) :: arg2 721 r = vec_srl(arg1, arg2) 722 723! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 724! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 725! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 726! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 727! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 728end subroutine vec_srl_i1u4 729 730! CHECK-LABEL: vec_srl_i2u4 731subroutine vec_srl_i2u4(arg1, arg2) 732 vector(integer(2)) :: arg1, r 733 vector(unsigned(4)) :: arg2 734 r = vec_srl(arg1, arg2) 735 736! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 737! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 738! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 739! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 740! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 741end subroutine vec_srl_i2u4 742 743! CHECK-LABEL: vec_srl_i4u4 744subroutine vec_srl_i4u4(arg1, arg2) 745 vector(integer(4)) :: arg1, r 746 vector(unsigned(4)) :: arg2 747 r = vec_srl(arg1, arg2) 748 749! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 750! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 751! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]]) 752end subroutine vec_srl_i4u4 753 754! CHECK-LABEL: vec_srl_u1u1 755subroutine vec_srl_u1u1(arg1, arg2) 756 vector(unsigned(1)) :: arg1, r 757 vector(unsigned(1)) :: arg2 758 r = vec_srl(arg1, arg2) 759 760! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 761! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 762! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 763! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 764! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 765! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 766end subroutine vec_srl_u1u1 767 768! CHECK-LABEL: vec_srl_u2u1 769subroutine vec_srl_u2u1(arg1, arg2) 770 vector(unsigned(2)) :: arg1, r 771 vector(unsigned(1)) :: arg2 772 r = vec_srl(arg1, arg2) 773 774! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 775! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 776! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 777! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 778! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 779! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 780end subroutine vec_srl_u2u1 781 782! CHECK-LABEL: vec_srl_u4u1 783subroutine vec_srl_u4u1(arg1, arg2) 784 vector(unsigned(4)) :: arg1, r 785 vector(unsigned(1)) :: arg2 786 r = vec_srl(arg1, arg2) 787 788! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 789! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 790! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 791! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 792end subroutine vec_srl_u4u1 793 794! CHECK-LABEL: vec_srl_u1u2 795subroutine vec_srl_u1u2(arg1, arg2) 796 vector(unsigned(1)) :: arg1, r 797 vector(unsigned(2)) :: arg2 798 r = vec_srl(arg1, arg2) 799 800! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 801! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 802! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 803! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 804! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 805! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 806end subroutine vec_srl_u1u2 807 808! CHECK-LABEL: vec_srl_u2u2 809subroutine vec_srl_u2u2(arg1, arg2) 810 vector(unsigned(2)) :: arg1, r 811 vector(unsigned(2)) :: arg2 812 r = vec_srl(arg1, arg2) 813 814! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 815! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 816! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 817! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 818! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 819! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 820end subroutine vec_srl_u2u2 821 822! CHECK-LABEL: vec_srl_u4u2 823subroutine vec_srl_u4u2(arg1, arg2) 824 vector(unsigned(4)) :: arg1, r 825 vector(unsigned(2)) :: arg2 826 r = vec_srl(arg1, arg2) 827 828! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 829! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 830! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 831! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 832end subroutine vec_srl_u4u2 833 834! CHECK-LABEL: vec_srl_u1u4 835subroutine vec_srl_u1u4(arg1, arg2) 836 vector(unsigned(1)) :: arg1, r 837 vector(unsigned(4)) :: arg2 838 r = vec_srl(arg1, arg2) 839 840! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 841! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 842! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 843! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 844! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 845end subroutine vec_srl_u1u4 846 847! CHECK-LABEL: vec_srl_u2u4 848subroutine vec_srl_u2u4(arg1, arg2) 849 vector(unsigned(2)) :: arg1, r 850 vector(unsigned(4)) :: arg2 851 r = vec_srl(arg1, arg2) 852 853! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 854! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 855! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 856! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[varg1]], <4 x i32> %[[arg2]]) 857! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 858end subroutine vec_srl_u2u4 859 860! CHECK-LABEL: vec_srl_u4u4 861subroutine vec_srl_u4u4(arg1, arg2) 862 vector(unsigned(4)) :: arg1, r 863 vector(unsigned(4)) :: arg2 864 r = vec_srl(arg1, arg2) 865 866! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 867! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 868! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %[[arg1]], <4 x i32> %[[arg2]]) 869end subroutine vec_srl_u4u4 870 871!---------------------- 872! vec_sro 873!---------------------- 874 875! CHECK-LABEL: vec_sro_i1u1 876subroutine vec_sro_i1u1(arg1, arg2) 877 vector(integer(1)) :: arg1, r 878 vector(unsigned(1)) :: arg2 879 r = vec_sro(arg1, arg2) 880 881! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 882! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 883! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 884! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 885! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 886! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 887end subroutine vec_sro_i1u1 888 889! CHECK-LABEL: vec_sro_i2u1 890subroutine vec_sro_i2u1(arg1, arg2) 891 vector(integer(2)) :: arg1, r 892 vector(unsigned(1)) :: arg2 893 r = vec_sro(arg1, arg2) 894 895! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 896! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 897! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 898! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 899! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 900! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 901end subroutine vec_sro_i2u1 902 903! CHECK-LABEL: vec_sro_i4u1 904subroutine vec_sro_i4u1(arg1, arg2) 905 vector(integer(4)) :: arg1, r 906 vector(unsigned(1)) :: arg2 907 r = vec_sro(arg1, arg2) 908 909! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 910! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 911! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 912! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 913end subroutine vec_sro_i4u1 914 915! CHECK-LABEL: vec_sro_u1u1 916subroutine vec_sro_u1u1(arg1, arg2) 917 vector(unsigned(1)) :: arg1, r 918 vector(unsigned(1)) :: arg2 919 r = vec_sro(arg1, arg2) 920 921! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 922! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 923! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 924! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 925! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 926! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 927end subroutine vec_sro_u1u1 928 929! CHECK-LABEL: vec_sro_u2u1 930subroutine vec_sro_u2u1(arg1, arg2) 931 vector(unsigned(2)) :: arg1, r 932 vector(unsigned(1)) :: arg2 933 r = vec_sro(arg1, arg2) 934 935! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 936! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 937! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 938! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 939! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 940! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 941end subroutine vec_sro_u2u1 942 943! CHECK-LABEL: vec_sro_u4u1 944subroutine vec_sro_u4u1(arg1, arg2) 945 vector(unsigned(4)) :: arg1, r 946 vector(unsigned(1)) :: arg2 947 r = vec_sro(arg1, arg2) 948 949! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 950! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 951! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 952! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 953end subroutine vec_sro_u4u1 954 955! CHECK-LABEL: vec_sro_r4u1 956subroutine vec_sro_r4u1(arg1, arg2) 957 vector(real(4)) :: arg1, r 958 vector(unsigned(1)) :: arg2 959 r = vec_sro(arg1, arg2) 960 961! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16 962! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 963! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32> 964! LLVMIR: %[[varg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32> 965! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 966! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float> 967end subroutine vec_sro_r4u1 968 969!------------------------------------- 970 971! CHECK-LABEL: vec_sro_i1u2 972subroutine vec_sro_i1u2(arg1, arg2) 973 vector(integer(1)) :: arg1, r 974 vector(unsigned(2)) :: arg2 975 r = vec_sro(arg1, arg2) 976 977! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 978! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 979! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 980! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 981! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 982! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 983end subroutine vec_sro_i1u2 984 985! CHECK-LABEL: vec_sro_i2u2 986subroutine vec_sro_i2u2(arg1, arg2) 987 vector(integer(2)) :: arg1, r 988 vector(unsigned(2)) :: arg2 989 r = vec_sro(arg1, arg2) 990 991! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 992! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 993! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 994! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 995! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 996! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 997end subroutine vec_sro_i2u2 998 999! CHECK-LABEL: vec_sro_i4u2 1000subroutine vec_sro_i4u2(arg1, arg2) 1001 vector(integer(4)) :: arg1, r 1002 vector(unsigned(2)) :: arg2 1003 r = vec_sro(arg1, arg2) 1004 1005! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 1006! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 1007! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 1008! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 1009end subroutine vec_sro_i4u2 1010 1011! CHECK-LABEL: vec_sro_u1u2 1012subroutine vec_sro_u1u2(arg1, arg2) 1013 vector(unsigned(1)) :: arg1, r 1014 vector(unsigned(2)) :: arg2 1015 r = vec_sro(arg1, arg2) 1016 1017! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 1018! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 1019! LLVMIR: %[[varg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32> 1020! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 1021! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 1022! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <16 x i8> 1023end subroutine vec_sro_u1u2 1024 1025! CHECK-LABEL: vec_sro_u2u2 1026subroutine vec_sro_u2u2(arg1, arg2) 1027 vector(unsigned(2)) :: arg1, r 1028 vector(unsigned(2)) :: arg2 1029 r = vec_sro(arg1, arg2) 1030 1031! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 1032! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 1033! LLVMIR: %[[varg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32> 1034! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 1035! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 1036! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <8 x i16> 1037 1038end subroutine vec_sro_u2u2 1039 1040! CHECK-LABEL: vec_sro_u4u2 1041subroutine vec_sro_u4u2(arg1, arg2) 1042 vector(unsigned(4)) :: arg1, r 1043 vector(unsigned(2)) :: arg2 1044 r = vec_sro(arg1, arg2) 1045 1046! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 1047! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 1048! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 1049! LLVMIR: %{{[0-9]+}} = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[arg1]], <4 x i32> %[[varg2]]) 1050end subroutine vec_sro_u4u2 1051 1052! CHECK-LABEL: vec_sro_r4u2 1053subroutine vec_sro_r4u2(arg1, arg2) 1054 vector(real(4)) :: arg1, r 1055 vector(unsigned(2)) :: arg2 1056 r = vec_sro(arg1, arg2) 1057 1058! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16 1059! LLVMIR: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16 1060! LLVMIR: %[[varg1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32> 1061! LLVMIR: %[[varg2:.*]] = bitcast <8 x i16> %[[arg2]] to <4 x i32> 1062! LLVMIR: %[[res:.*]] = call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %[[varg1]], <4 x i32> %[[varg2]]) 1063! LLVMIR: %{{[0-9]+}} = bitcast <4 x i32> %[[res]] to <4 x float> 1064end subroutine vec_sro_r4u2 1065