1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute private(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute private(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global, bound tid and loop vars 78 g = 1; 79 g1 = 1; 80 sivar = 2; 81 [&]() { 82 g = 2; 83 g1 = 2; 84 sivar = 4; 85 86 }(); 87 } 88 }(); 89 return 0; 90 #else 91 #pragma omp target teams distribute private(t_var, vec, s_arr, var, sivar) 92 for (int i = 0; i < 2; ++i) { 93 vec[i] = t_var; 94 s_arr[i] = var; 95 sivar += i; 96 } 97 return tmain<int>(); 98 #endif 99 } 100 101 102 103 // Skip global, bound tid and loop vars 104 105 // private(s_arr) 106 107 // private(var) 108 109 110 111 112 113 // Skip global, bound tid and loop vars 114 115 // private(s_arr) 116 117 118 // private(var) 119 120 121 #endif 122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 124 // CHECK1-NEXT: entry: 125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 126 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 127 // CHECK1-NEXT: ret void 128 // 129 // 130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 131 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 132 // CHECK1-NEXT: entry: 133 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 134 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 135 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 136 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 137 // CHECK1-NEXT: ret void 138 // 139 // 140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 141 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 142 // CHECK1-NEXT: entry: 143 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 144 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 145 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 146 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 151 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 154 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 157 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 158 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 159 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 164 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 167 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: ret void 170 // 171 // 172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 173 // CHECK1-SAME: () #[[ATTR0]] { 174 // CHECK1-NEXT: entry: 175 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 176 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 177 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 178 // CHECK1-NEXT: ret void 179 // 180 // 181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 182 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 183 // CHECK1-NEXT: entry: 184 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 185 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 186 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 187 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 188 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 190 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 191 // CHECK1-NEXT: ret void 192 // 193 // 194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 195 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 196 // CHECK1-NEXT: entry: 197 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 198 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 199 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 200 // CHECK1: arraydestroy.body: 201 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 202 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 203 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 204 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 205 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 206 // CHECK1: arraydestroy.done1: 207 // CHECK1-NEXT: ret void 208 // 209 // 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 211 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 212 // CHECK1-NEXT: entry: 213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 215 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 216 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 217 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 218 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 219 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 220 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 221 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 222 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 223 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 224 // CHECK1-NEXT: ret void 225 // 226 // 227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 228 // CHECK1-SAME: () #[[ATTR0]] { 229 // CHECK1-NEXT: entry: 230 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 231 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 232 // CHECK1-NEXT: ret void 233 // 234 // 235 // CHECK1-LABEL: define {{[^@]+}}@main 236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 237 // CHECK1-NEXT: entry: 238 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 239 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 241 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 242 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 243 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 244 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 245 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 246 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 247 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 248 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 249 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 250 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 251 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 252 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 253 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 254 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 255 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 256 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 257 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 258 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 259 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 260 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 261 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 262 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 263 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 264 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 265 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 266 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 267 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 268 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]]) 269 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 270 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 271 // CHECK1: omp_offload.failed: 272 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 273 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 274 // CHECK1: omp_offload.cont: 275 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 276 // CHECK1-NEXT: ret i32 [[CALL]] 277 // 278 // 279 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 280 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 281 // CHECK1-NEXT: entry: 282 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined) 283 // CHECK1-NEXT: ret void 284 // 285 // 286 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined 287 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 288 // CHECK1-NEXT: entry: 289 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 290 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 291 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 292 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 293 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 294 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 297 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 299 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 300 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 301 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 303 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 304 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 305 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 306 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 307 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 308 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 309 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 310 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 311 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 312 // CHECK1: arrayctor.loop: 313 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 314 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 315 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 316 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 317 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 318 // CHECK1: arrayctor.cont: 319 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 320 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 321 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 322 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 323 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 324 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 325 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 326 // CHECK1: cond.true: 327 // CHECK1-NEXT: br label [[COND_END:%.*]] 328 // CHECK1: cond.false: 329 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 330 // CHECK1-NEXT: br label [[COND_END]] 331 // CHECK1: cond.end: 332 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 333 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 334 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 335 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 336 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 337 // CHECK1: omp.inner.for.cond: 338 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 339 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 340 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 341 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 342 // CHECK1: omp.inner.for.cond.cleanup: 343 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 344 // CHECK1: omp.inner.for.body: 345 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 346 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 347 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 348 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 349 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 350 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 351 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 352 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 353 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 354 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 355 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 356 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 357 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 358 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 359 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 360 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 361 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 362 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 363 // CHECK1: omp.body.continue: 364 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 365 // CHECK1: omp.inner.for.inc: 366 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 367 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 368 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 369 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 370 // CHECK1: omp.inner.for.end: 371 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 372 // CHECK1: omp.loop.exit: 373 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 374 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 375 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 376 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 377 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 378 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 379 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 380 // CHECK1: arraydestroy.body: 381 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 382 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 383 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 384 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 385 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 386 // CHECK1: arraydestroy.done7: 387 // CHECK1-NEXT: ret void 388 // 389 // 390 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 391 // CHECK1-SAME: () #[[ATTR1]] comdat { 392 // CHECK1-NEXT: entry: 393 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 394 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 395 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 396 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 397 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 398 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 399 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 400 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 401 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 402 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 403 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 404 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 405 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) 406 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 407 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 408 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 409 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 410 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 411 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 412 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 413 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 414 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 415 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 416 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 417 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 418 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 419 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 420 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 421 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 422 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 423 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 424 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 425 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 426 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 427 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 428 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 429 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 430 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 431 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 432 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 433 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 434 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 435 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 436 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 437 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 438 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 439 // CHECK1: omp_offload.failed: 440 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 441 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 442 // CHECK1: omp_offload.cont: 443 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 444 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 445 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 446 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 447 // CHECK1: arraydestroy.body: 448 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 449 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 450 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 451 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 452 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 453 // CHECK1: arraydestroy.done2: 454 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 455 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 456 // CHECK1-NEXT: ret i32 [[TMP16]] 457 // 458 // 459 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 460 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 461 // CHECK1-NEXT: entry: 462 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 463 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 464 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 465 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 466 // CHECK1-NEXT: ret void 467 // 468 // 469 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 470 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 471 // CHECK1-NEXT: entry: 472 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 473 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 474 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 475 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 476 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 477 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 478 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 479 // CHECK1-NEXT: ret void 480 // 481 // 482 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 483 // CHECK1-SAME: () #[[ATTR4]] { 484 // CHECK1-NEXT: entry: 485 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 486 // CHECK1-NEXT: ret void 487 // 488 // 489 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 490 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 491 // CHECK1-NEXT: entry: 492 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 493 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 494 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 495 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 496 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 497 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 498 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 499 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 500 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 501 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 502 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 503 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 504 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 505 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 506 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 507 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 508 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 509 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 510 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 511 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 512 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 513 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 514 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 515 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 516 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 517 // CHECK1: arrayctor.loop: 518 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 519 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 520 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 521 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 522 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 523 // CHECK1: arrayctor.cont: 524 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 525 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 526 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 527 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 528 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 529 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 530 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 531 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 532 // CHECK1: cond.true: 533 // CHECK1-NEXT: br label [[COND_END:%.*]] 534 // CHECK1: cond.false: 535 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 536 // CHECK1-NEXT: br label [[COND_END]] 537 // CHECK1: cond.end: 538 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 539 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 540 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 541 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 542 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 543 // CHECK1: omp.inner.for.cond: 544 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 545 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 546 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 547 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 548 // CHECK1: omp.inner.for.cond.cleanup: 549 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 550 // CHECK1: omp.inner.for.body: 551 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 552 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 553 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 554 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 555 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 556 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 557 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 558 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 559 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 560 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 561 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 562 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 563 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 564 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 565 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 566 // CHECK1: omp.body.continue: 567 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 568 // CHECK1: omp.inner.for.inc: 569 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 570 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 571 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 572 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 573 // CHECK1: omp.inner.for.end: 574 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 575 // CHECK1: omp.loop.exit: 576 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 577 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 578 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 579 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 580 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 581 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 582 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 583 // CHECK1: arraydestroy.body: 584 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 585 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 586 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 587 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 588 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 589 // CHECK1: arraydestroy.done8: 590 // CHECK1-NEXT: ret void 591 // 592 // 593 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 594 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 595 // CHECK1-NEXT: entry: 596 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 597 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 598 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 599 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 600 // CHECK1-NEXT: ret void 601 // 602 // 603 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 604 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 605 // CHECK1-NEXT: entry: 606 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 607 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 608 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 609 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 610 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 611 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 612 // CHECK1-NEXT: ret void 613 // 614 // 615 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 616 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 617 // CHECK1-NEXT: entry: 618 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 619 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 620 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 621 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 622 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 623 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 624 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 625 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 626 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 627 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 628 // CHECK1-NEXT: ret void 629 // 630 // 631 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 632 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 633 // CHECK1-NEXT: entry: 634 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 635 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 636 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 637 // CHECK1-NEXT: ret void 638 // 639 // 640 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 641 // CHECK1-SAME: () #[[ATTR0]] { 642 // CHECK1-NEXT: entry: 643 // CHECK1-NEXT: call void @__cxx_global_var_init() 644 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 645 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 646 // CHECK1-NEXT: ret void 647 // 648 // 649 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 650 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 651 // CHECK3-NEXT: entry: 652 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 653 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 654 // CHECK3-NEXT: ret void 655 // 656 // 657 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 658 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 659 // CHECK3-NEXT: entry: 660 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 661 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 662 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 663 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 664 // CHECK3-NEXT: ret void 665 // 666 // 667 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 668 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 669 // CHECK3-NEXT: entry: 670 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 671 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 672 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 673 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 674 // CHECK3-NEXT: ret void 675 // 676 // 677 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 678 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 679 // CHECK3-NEXT: entry: 680 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 681 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 682 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 683 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 684 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 685 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 686 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 687 // CHECK3-NEXT: ret void 688 // 689 // 690 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 691 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 692 // CHECK3-NEXT: entry: 693 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 694 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 695 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 696 // CHECK3-NEXT: ret void 697 // 698 // 699 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 700 // CHECK3-SAME: () #[[ATTR0]] { 701 // CHECK3-NEXT: entry: 702 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 703 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 704 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 705 // CHECK3-NEXT: ret void 706 // 707 // 708 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 709 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 710 // CHECK3-NEXT: entry: 711 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 712 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 713 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 714 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 715 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 716 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 717 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 718 // CHECK3-NEXT: ret void 719 // 720 // 721 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 722 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 723 // CHECK3-NEXT: entry: 724 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 725 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 726 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 727 // CHECK3: arraydestroy.body: 728 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 729 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 730 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 731 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 732 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 733 // CHECK3: arraydestroy.done1: 734 // CHECK3-NEXT: ret void 735 // 736 // 737 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 738 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 739 // CHECK3-NEXT: entry: 740 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 741 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 742 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 743 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 744 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 745 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 746 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 747 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 748 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 749 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 750 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 751 // CHECK3-NEXT: ret void 752 // 753 // 754 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 755 // CHECK3-SAME: () #[[ATTR0]] { 756 // CHECK3-NEXT: entry: 757 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 758 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 759 // CHECK3-NEXT: ret void 760 // 761 // 762 // CHECK3-LABEL: define {{[^@]+}}@main 763 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 764 // CHECK3-NEXT: entry: 765 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 766 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 767 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 768 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 769 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 770 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 771 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 772 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 773 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 774 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 775 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 776 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 777 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 778 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 779 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 780 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 781 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 782 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 783 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 784 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 785 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 786 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 787 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 788 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 789 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 790 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 791 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 792 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 793 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 794 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 795 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]]) 796 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 797 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 798 // CHECK3: omp_offload.failed: 799 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] 800 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 801 // CHECK3: omp_offload.cont: 802 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 803 // CHECK3-NEXT: ret i32 [[CALL]] 804 // 805 // 806 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 807 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 808 // CHECK3-NEXT: entry: 809 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined) 810 // CHECK3-NEXT: ret void 811 // 812 // 813 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined 814 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 815 // CHECK3-NEXT: entry: 816 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 817 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 818 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 819 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 820 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 821 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 822 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 823 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 824 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 825 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 826 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 827 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 828 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 829 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 830 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 831 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 832 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 833 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 834 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 835 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 836 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 837 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 838 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 839 // CHECK3: arrayctor.loop: 840 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 841 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 842 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 843 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 844 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 845 // CHECK3: arrayctor.cont: 846 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 847 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 848 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 849 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 850 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 851 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 852 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 853 // CHECK3: cond.true: 854 // CHECK3-NEXT: br label [[COND_END:%.*]] 855 // CHECK3: cond.false: 856 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 857 // CHECK3-NEXT: br label [[COND_END]] 858 // CHECK3: cond.end: 859 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 860 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 861 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 862 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 863 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 864 // CHECK3: omp.inner.for.cond: 865 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 866 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 867 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 868 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 869 // CHECK3: omp.inner.for.cond.cleanup: 870 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 871 // CHECK3: omp.inner.for.body: 872 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 873 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 874 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 875 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 876 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 877 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 878 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 879 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 880 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 881 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 882 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) 883 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 884 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 885 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 886 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 887 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 888 // CHECK3: omp.body.continue: 889 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 890 // CHECK3: omp.inner.for.inc: 891 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 892 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 893 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 894 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 895 // CHECK3: omp.inner.for.end: 896 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 897 // CHECK3: omp.loop.exit: 898 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 899 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 900 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 901 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 902 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 903 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 904 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 905 // CHECK3: arraydestroy.body: 906 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 907 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 908 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 909 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 910 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 911 // CHECK3: arraydestroy.done6: 912 // CHECK3-NEXT: ret void 913 // 914 // 915 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 916 // CHECK3-SAME: () #[[ATTR1]] comdat { 917 // CHECK3-NEXT: entry: 918 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 919 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 920 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 921 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 922 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 923 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 924 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 925 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 926 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 927 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 928 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 929 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 930 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) 931 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 932 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 933 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 934 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 935 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 936 // CHECK3-NEXT: store i32 3, ptr [[TMP0]], align 4 937 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 938 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 939 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 940 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 941 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 942 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 943 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 944 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 945 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 946 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 947 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 948 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 949 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 950 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 951 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 952 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 953 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 954 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 955 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 956 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 957 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 958 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 959 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 960 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 961 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 962 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 963 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 964 // CHECK3: omp_offload.failed: 965 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 966 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 967 // CHECK3: omp_offload.cont: 968 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 969 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 970 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 971 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 972 // CHECK3: arraydestroy.body: 973 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 974 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 975 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 976 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 977 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 978 // CHECK3: arraydestroy.done2: 979 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 980 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 981 // CHECK3-NEXT: ret i32 [[TMP16]] 982 // 983 // 984 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 985 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 986 // CHECK3-NEXT: entry: 987 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 988 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 989 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 990 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 991 // CHECK3-NEXT: ret void 992 // 993 // 994 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 995 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 996 // CHECK3-NEXT: entry: 997 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 998 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 999 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1000 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1001 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1002 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1003 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1004 // CHECK3-NEXT: ret void 1005 // 1006 // 1007 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1008 // CHECK3-SAME: () #[[ATTR4]] { 1009 // CHECK3-NEXT: entry: 1010 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 1011 // CHECK3-NEXT: ret void 1012 // 1013 // 1014 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1015 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1016 // CHECK3-NEXT: entry: 1017 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1018 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1019 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1020 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1021 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1022 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1023 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1024 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1025 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1026 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1027 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1028 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1029 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1030 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1031 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1032 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1033 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1034 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1035 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1036 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1037 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1038 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1039 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1040 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1041 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1042 // CHECK3: arrayctor.loop: 1043 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1044 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1045 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1046 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1047 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1048 // CHECK3: arrayctor.cont: 1049 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1050 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1051 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1052 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1053 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1054 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1055 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1056 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1057 // CHECK3: cond.true: 1058 // CHECK3-NEXT: br label [[COND_END:%.*]] 1059 // CHECK3: cond.false: 1060 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1061 // CHECK3-NEXT: br label [[COND_END]] 1062 // CHECK3: cond.end: 1063 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1064 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1065 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1066 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1067 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1068 // CHECK3: omp.inner.for.cond: 1069 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1070 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1071 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1072 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1073 // CHECK3: omp.inner.for.cond.cleanup: 1074 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1075 // CHECK3: omp.inner.for.body: 1076 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1077 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1078 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1079 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1080 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 1081 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 1082 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1083 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 1084 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 1085 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 1086 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 1087 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) 1088 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1089 // CHECK3: omp.body.continue: 1090 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1091 // CHECK3: omp.inner.for.inc: 1092 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1093 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 1094 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1095 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1096 // CHECK3: omp.inner.for.end: 1097 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1098 // CHECK3: omp.loop.exit: 1099 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1100 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1101 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1102 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1103 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1104 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1105 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1106 // CHECK3: arraydestroy.body: 1107 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1108 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1109 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1110 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1111 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1112 // CHECK3: arraydestroy.done7: 1113 // CHECK3-NEXT: ret void 1114 // 1115 // 1116 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1117 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1118 // CHECK3-NEXT: entry: 1119 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1120 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1121 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1122 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1123 // CHECK3-NEXT: ret void 1124 // 1125 // 1126 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1127 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1128 // CHECK3-NEXT: entry: 1129 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1130 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1131 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1132 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1133 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1134 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1135 // CHECK3-NEXT: ret void 1136 // 1137 // 1138 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1139 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1140 // CHECK3-NEXT: entry: 1141 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1142 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1143 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1144 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1145 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1146 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1147 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1148 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1149 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1150 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1151 // CHECK3-NEXT: ret void 1152 // 1153 // 1154 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1155 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1156 // CHECK3-NEXT: entry: 1157 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1158 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1159 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1160 // CHECK3-NEXT: ret void 1161 // 1162 // 1163 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 1164 // CHECK3-SAME: () #[[ATTR0]] { 1165 // CHECK3-NEXT: entry: 1166 // CHECK3-NEXT: call void @__cxx_global_var_init() 1167 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1168 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1169 // CHECK3-NEXT: ret void 1170 // 1171 // 1172 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1173 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1174 // CHECK9-NEXT: entry: 1175 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1176 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1177 // CHECK9-NEXT: ret void 1178 // 1179 // 1180 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1181 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 1182 // CHECK9-NEXT: entry: 1183 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1184 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1185 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1186 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1187 // CHECK9-NEXT: ret void 1188 // 1189 // 1190 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1191 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1192 // CHECK9-NEXT: entry: 1193 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1194 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1195 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1196 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1197 // CHECK9-NEXT: ret void 1198 // 1199 // 1200 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1201 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1202 // CHECK9-NEXT: entry: 1203 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1204 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1205 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1206 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1207 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1208 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1209 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 1210 // CHECK9-NEXT: ret void 1211 // 1212 // 1213 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1214 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1215 // CHECK9-NEXT: entry: 1216 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1217 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1218 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1219 // CHECK9-NEXT: ret void 1220 // 1221 // 1222 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1223 // CHECK9-SAME: () #[[ATTR0]] { 1224 // CHECK9-NEXT: entry: 1225 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1226 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1227 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1228 // CHECK9-NEXT: ret void 1229 // 1230 // 1231 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1232 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1233 // CHECK9-NEXT: entry: 1234 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1235 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1236 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1237 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1238 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1239 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1240 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1241 // CHECK9-NEXT: ret void 1242 // 1243 // 1244 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1245 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1246 // CHECK9-NEXT: entry: 1247 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1248 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1249 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1250 // CHECK9: arraydestroy.body: 1251 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1252 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1253 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1254 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1255 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1256 // CHECK9: arraydestroy.done1: 1257 // CHECK9-NEXT: ret void 1258 // 1259 // 1260 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1261 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1262 // CHECK9-NEXT: entry: 1263 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1264 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1265 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1266 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1267 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1268 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1269 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1270 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1271 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1272 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1273 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 1274 // CHECK9-NEXT: ret void 1275 // 1276 // 1277 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1278 // CHECK9-SAME: () #[[ATTR0]] { 1279 // CHECK9-NEXT: entry: 1280 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1281 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1282 // CHECK9-NEXT: ret void 1283 // 1284 // 1285 // CHECK9-LABEL: define {{[^@]+}}@main 1286 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1287 // CHECK9-NEXT: entry: 1288 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1289 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1290 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 1291 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1292 // CHECK9-NEXT: ret i32 0 1293 // 1294 // 1295 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 1296 // CHECK9-SAME: () #[[ATTR4:[0-9]+]] { 1297 // CHECK9-NEXT: entry: 1298 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined) 1299 // CHECK9-NEXT: ret void 1300 // 1301 // 1302 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined 1303 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1304 // CHECK9-NEXT: entry: 1305 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1306 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1307 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1308 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1309 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1310 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1311 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1312 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1313 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1314 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1315 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1316 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 1317 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1318 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1319 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1320 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1321 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1322 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1323 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1324 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1325 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1326 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1327 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 1328 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1329 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1330 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1331 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1332 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1333 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1334 // CHECK9: cond.true: 1335 // CHECK9-NEXT: br label [[COND_END:%.*]] 1336 // CHECK9: cond.false: 1337 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1338 // CHECK9-NEXT: br label [[COND_END]] 1339 // CHECK9: cond.end: 1340 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1341 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1342 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1343 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1344 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1345 // CHECK9: omp.inner.for.cond: 1346 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1347 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1348 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1349 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1350 // CHECK9: omp.inner.for.body: 1351 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1352 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1353 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1354 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1355 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 1356 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 1357 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 1358 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 1359 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 1360 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 1361 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 1362 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 1363 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 1364 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 1365 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 1366 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1367 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1368 // CHECK9: omp.body.continue: 1369 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1370 // CHECK9: omp.inner.for.inc: 1371 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1372 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 1373 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 1374 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1375 // CHECK9: omp.inner.for.end: 1376 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1377 // CHECK9: omp.loop.exit: 1378 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1379 // CHECK9-NEXT: ret void 1380 // 1381 // 1382 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_private_codegen.cpp 1383 // CHECK9-SAME: () #[[ATTR0]] { 1384 // CHECK9-NEXT: entry: 1385 // CHECK9-NEXT: call void @__cxx_global_var_init() 1386 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1387 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1388 // CHECK9-NEXT: ret void 1389 // 1390