xref: /llvm-project/clang/test/OpenMP/irbuilder_simd_aligned.cpp (revision d3eb65f15dfda454424125b2fa675378bd350889) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_  size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
3 // expected-no-diagnostics
4 
5 struct S {
6   int a, b;
7 };
8 
9 struct P {
10   int a, b;
11 };
12 
13 #define N 32
14 
15 void simple(float *a, float *b, int *c) {
16   S s, *p;
17   int D[N];
18   for (int i = 0; i <N; ++i)
19     D[i] = i;
20   P pp;
21 #pragma omp simd aligned (a:128) aligned(p:64) aligned(D)
22   for (int i = 3; i < N; i += 5) {
23     a[i] = b[i] + s.a + p->a + D[i];
24   }
25 
26 #pragma omp simd
27   for (int j = 3; j < N; j += 5) {
28     c[j] = pp.a;
29   }
30 }
31 // CHECK-LABEL: define {{[^@]+}}@_Z6simplePfS_Pi
32 // CHECK-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] {
33 // CHECK-NEXT:  entry:
34 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
35 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
36 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
37 // CHECK-NEXT:    [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 4
38 // CHECK-NEXT:    [[P:%.*]] = alloca ptr, align 8
39 // CHECK-NEXT:    [[D:%.*]] = alloca [32 x i32], align 16
40 // CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
41 // CHECK-NEXT:    [[PP:%.*]] = alloca [[STRUCT_P:%.*]], align 4
42 // CHECK-NEXT:    [[I1:%.*]] = alloca i32, align 4
43 // CHECK-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
44 // CHECK-NEXT:    [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
45 // CHECK-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
46 // CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
47 // CHECK-NEXT:    [[AGG_CAPTURED15:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
48 // CHECK-NEXT:    [[AGG_CAPTURED16:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
49 // CHECK-NEXT:    [[DOTCOUNT_ADDR17:%.*]] = alloca i32, align 4
50 // CHECK-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
51 // CHECK-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
52 // CHECK-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
53 // CHECK-NEXT:    store i32 0, ptr [[I]], align 4
54 // CHECK-NEXT:    br label [[FOR_COND:%.*]]
55 // CHECK:       for.cond:
56 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I]], align 4
57 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32
58 // CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
59 // CHECK:       for.body:
60 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[I]], align 4
61 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 4
62 // CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64
63 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], i64 0, i64 [[IDXPROM]]
64 // CHECK-NEXT:    store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4
65 // CHECK-NEXT:    br label [[FOR_INC:%.*]]
66 // CHECK:       for.inc:
67 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[I]], align 4
68 // CHECK-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP3]], 1
69 // CHECK-NEXT:    store i32 [[INC]], ptr [[I]], align 4
70 // CHECK-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
71 // CHECK:       for.end:
72 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8
73 // CHECK-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP4]], i64 128) ]
74 // CHECK-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[P]], align 8
75 // CHECK-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP5]], i64 64) ]
76 // CHECK-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], i64 0, i64 0
77 // CHECK-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
78 // CHECK-NEXT:    store i32 3, ptr [[I1]], align 4
79 // CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
80 // CHECK-NEXT:    store ptr [[I1]], ptr [[TMP6]], align 8
81 // CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED2]], i32 0, i32 0
82 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I1]], align 4
83 // CHECK-NEXT:    store i32 [[TMP8]], ptr [[TMP7]], align 4
84 // CHECK-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
85 // CHECK-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
86 // CHECK-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
87 // CHECK:       omp_loop.preheader:
88 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER:%.*]]
89 // CHECK:       omp_loop.header:
90 // CHECK-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
91 // CHECK-NEXT:    br label [[OMP_LOOP_COND:%.*]]
92 // CHECK:       omp_loop.cond:
93 // CHECK-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]]
94 // CHECK-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
95 // CHECK:       omp_loop.body:
96 // CHECK-NEXT:    call void @__captured_stmt.1(ptr [[I1]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED2]]), !llvm.access.group [[ACC_GRP5:![0-9]+]]
97 // CHECK-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP5]]
98 // CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I1]], align 4, !llvm.access.group [[ACC_GRP5]]
99 // CHECK-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP10]] to i64
100 // CHECK-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM3]]
101 // CHECK-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
102 // CHECK-NEXT:    [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[S]], i32 0, i32 0
103 // CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP5]]
104 // CHECK-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to float
105 // CHECK-NEXT:    [[ADD:%.*]] = fadd float [[TMP11]], [[CONV]]
106 // CHECK-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[P]], align 8, !llvm.access.group [[ACC_GRP5]]
107 // CHECK-NEXT:    [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP13]], i32 0, i32 0
108 // CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[A6]], align 4, !llvm.access.group [[ACC_GRP5]]
109 // CHECK-NEXT:    [[CONV7:%.*]] = sitofp i32 [[TMP14]] to float
110 // CHECK-NEXT:    [[ADD8:%.*]] = fadd float [[ADD]], [[CONV7]]
111 // CHECK-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I1]], align 4, !llvm.access.group [[ACC_GRP5]]
112 // CHECK-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64
113 // CHECK-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], i64 0, i64 [[IDXPROM9]]
114 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP5]]
115 // CHECK-NEXT:    [[CONV11:%.*]] = sitofp i32 [[TMP16]] to float
116 // CHECK-NEXT:    [[ADD12:%.*]] = fadd float [[ADD8]], [[CONV11]]
117 // CHECK-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP5]]
118 // CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I1]], align 4, !llvm.access.group [[ACC_GRP5]]
119 // CHECK-NEXT:    [[IDXPROM13:%.*]] = sext i32 [[TMP18]] to i64
120 // CHECK-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM13]]
121 // CHECK-NEXT:    store float [[ADD12]], ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP5]]
122 // CHECK-NEXT:    br label [[OMP_LOOP_INC]]
123 // CHECK:       omp_loop.inc:
124 // CHECK-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
125 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER]], !llvm.loop [[LOOP6:![0-9]+]]
126 // CHECK:       omp_loop.exit:
127 // CHECK-NEXT:    br label [[OMP_LOOP_AFTER:%.*]]
128 // CHECK:       omp_loop.after:
129 // CHECK-NEXT:    store i32 3, ptr [[J]], align 4
130 // CHECK-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED15]], i32 0, i32 0
131 // CHECK-NEXT:    store ptr [[J]], ptr [[TMP19]], align 8
132 // CHECK-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED16]], i32 0, i32 0
133 // CHECK-NEXT:    [[TMP21:%.*]] = load i32, ptr [[J]], align 4
134 // CHECK-NEXT:    store i32 [[TMP21]], ptr [[TMP20]], align 4
135 // CHECK-NEXT:    call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR17]], ptr [[AGG_CAPTURED15]])
136 // CHECK-NEXT:    [[DOTCOUNT18:%.*]] = load i32, ptr [[DOTCOUNT_ADDR17]], align 4
137 // CHECK-NEXT:    br label [[OMP_LOOP_PREHEADER19:%.*]]
138 // CHECK:       omp_loop.preheader19:
139 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER20:%.*]]
140 // CHECK:       omp_loop.header20:
141 // CHECK-NEXT:    [[OMP_LOOP_IV26:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER19]] ], [ [[OMP_LOOP_NEXT28:%.*]], [[OMP_LOOP_INC23:%.*]] ]
142 // CHECK-NEXT:    br label [[OMP_LOOP_COND21:%.*]]
143 // CHECK:       omp_loop.cond21:
144 // CHECK-NEXT:    [[OMP_LOOP_CMP27:%.*]] = icmp ult i32 [[OMP_LOOP_IV26]], [[DOTCOUNT18]]
145 // CHECK-NEXT:    br i1 [[OMP_LOOP_CMP27]], label [[OMP_LOOP_BODY22:%.*]], label [[OMP_LOOP_EXIT24:%.*]]
146 // CHECK:       omp_loop.body22:
147 // CHECK-NEXT:    call void @__captured_stmt.3(ptr [[J]], i32 [[OMP_LOOP_IV26]], ptr [[AGG_CAPTURED16]]), !llvm.access.group [[ACC_GRP9:![0-9]+]]
148 // CHECK-NEXT:    [[A29:%.*]] = getelementptr inbounds nuw [[STRUCT_P]], ptr [[PP]], i32 0, i32 0
149 // CHECK-NEXT:    [[TMP22:%.*]] = load i32, ptr [[A29]], align 4, !llvm.access.group [[ACC_GRP9]]
150 // CHECK-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP9]]
151 // CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]]
152 // CHECK-NEXT:    [[IDXPROM30:%.*]] = sext i32 [[TMP24]] to i64
153 // CHECK-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds i32, ptr [[TMP23]], i64 [[IDXPROM30]]
154 // CHECK-NEXT:    store i32 [[TMP22]], ptr [[ARRAYIDX31]], align 4, !llvm.access.group [[ACC_GRP9]]
155 // CHECK-NEXT:    br label [[OMP_LOOP_INC23]]
156 // CHECK:       omp_loop.inc23:
157 // CHECK-NEXT:    [[OMP_LOOP_NEXT28]] = add nuw i32 [[OMP_LOOP_IV26]], 1
158 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER20]], !llvm.loop [[LOOP10:![0-9]+]]
159 // CHECK:       omp_loop.exit24:
160 // CHECK-NEXT:    br label [[OMP_LOOP_AFTER25:%.*]]
161 // CHECK:       omp_loop.after25:
162 // CHECK-NEXT:    ret void
163 //
164 //
165 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt
166 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] {
167 // CHECK-NEXT:  entry:
168 // CHECK-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
169 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
170 // CHECK-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
171 // CHECK-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
172 // CHECK-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
173 // CHECK-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
174 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
175 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
176 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0
177 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
178 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
179 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
180 // CHECK-NEXT:    store i32 32, ptr [[DOTSTOP]], align 4
181 // CHECK-NEXT:    store i32 5, ptr [[DOTSTEP]], align 4
182 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
183 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
184 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
185 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
186 // CHECK:       cond.true:
187 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
188 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
189 // CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
190 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
191 // CHECK-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
192 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
193 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
194 // CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
195 // CHECK-NEXT:    br label [[COND_END:%.*]]
196 // CHECK:       cond.false:
197 // CHECK-NEXT:    br label [[COND_END]]
198 // CHECK:       cond.end:
199 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
200 // CHECK-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
201 // CHECK-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
202 // CHECK-NEXT:    ret void
203 //
204 //
205 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1
206 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {
207 // CHECK-NEXT:  entry:
208 // CHECK-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
209 // CHECK-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
210 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
211 // CHECK-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
212 // CHECK-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
213 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
214 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
215 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0
216 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
217 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
218 // CHECK-NEXT:    [[MUL:%.*]] = mul i32 5, [[TMP3]]
219 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
220 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
221 // CHECK-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
222 // CHECK-NEXT:    ret void
223 //
224 //
225 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.2
226 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {
227 // CHECK-NEXT:  entry:
228 // CHECK-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
229 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
230 // CHECK-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
231 // CHECK-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
232 // CHECK-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
233 // CHECK-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
234 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
235 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
236 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0
237 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
238 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
239 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
240 // CHECK-NEXT:    store i32 32, ptr [[DOTSTOP]], align 4
241 // CHECK-NEXT:    store i32 5, ptr [[DOTSTEP]], align 4
242 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
243 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
244 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
245 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
246 // CHECK:       cond.true:
247 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
248 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
249 // CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
250 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
251 // CHECK-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
252 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
253 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
254 // CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
255 // CHECK-NEXT:    br label [[COND_END:%.*]]
256 // CHECK:       cond.false:
257 // CHECK-NEXT:    br label [[COND_END]]
258 // CHECK:       cond.end:
259 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
260 // CHECK-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
261 // CHECK-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
262 // CHECK-NEXT:    ret void
263 //
264 //
265 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.3
266 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {
267 // CHECK-NEXT:  entry:
268 // CHECK-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
269 // CHECK-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
270 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
271 // CHECK-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
272 // CHECK-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
273 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
274 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
275 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0
276 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
277 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
278 // CHECK-NEXT:    [[MUL:%.*]] = mul i32 5, [[TMP3]]
279 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
280 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
281 // CHECK-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
282 // CHECK-NEXT:    ret void
283 //
284 //.
285 // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
286 // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
287 // CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
288 //.
289 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
290 // CHECK: [[META1:![0-9]+]] = !{i32 7, !"openmp", i32 50}
291 // CHECK: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
292 // CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]}
293 // CHECK: [[META4]] = !{!"llvm.loop.mustprogress"}
294 // CHECK: [[ACC_GRP5]] = distinct !{}
295 // CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META8:![0-9]+]]}
296 // CHECK: [[META7]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP5]]}
297 // CHECK: [[META8]] = !{!"llvm.loop.vectorize.enable", i1 true}
298 // CHECK: [[ACC_GRP9]] = distinct !{}
299 // CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META11:![0-9]+]], [[META8]]}
300 // CHECK: [[META11]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP9]]}
301 //.
302