xref: /llvm-project/clang/test/OpenMP/generic_loop_codegen.cpp (revision c74730070a0261d582e01ee7e5eef2e7c39fb11f) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name tmp2 --version 2
2 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp %s
3 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR
4 
5 // Check same results after serialization round-trip
6 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
7 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH
8 
9 // expected-no-diagnostics
10 
11 #ifndef HEADER
12 #define HEADER
13 
14 void foo(int t) {
15 
16   int i, j, z;
17   #pragma omp loop collapse(2) reduction(+:z) lastprivate(j) bind(thread)
18   for (int i = 0; i<t; ++i)
19     for (j = 0; j<t; ++j)
20       z += i+j;
21 }
22 #endif
23 // IR-LABEL: define dso_local void @_Z3fooi
24 // IR-SAME: (i32 noundef [[T:%.*]]) #[[ATTR0:[0-9]+]] {
25 // IR-NEXT:  entry:
26 // IR-NEXT:    [[T_ADDR:%.*]] = alloca i32, align 4
27 // IR-NEXT:    [[I:%.*]] = alloca i32, align 4
28 // IR-NEXT:    [[J:%.*]] = alloca i32, align 4
29 // IR-NEXT:    [[Z:%.*]] = alloca i32, align 4
30 // IR-NEXT:    [[TMP:%.*]] = alloca i32, align 4
31 // IR-NEXT:    [[TMP2TMP1:%.*]] = alloca i32, align 4
32 // IR-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
33 // IR-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
34 // IR-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
35 // IR-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
36 // IR-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
37 // IR-NEXT:    [[I8:%.*]] = alloca i32, align 4
38 // IR-NEXT:    [[J9:%.*]] = alloca i32, align 4
39 // IR-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
40 // IR-NEXT:    [[I11:%.*]] = alloca i32, align 4
41 // IR-NEXT:    [[J12:%.*]] = alloca i32, align 4
42 // IR-NEXT:    [[Z13:%.*]] = alloca i32, align 4
43 // IR-NEXT:    store i32 [[T]], ptr [[T_ADDR]], align 4
44 // IR-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_ADDR]], align 4
45 // IR-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
46 // IR-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
47 // IR-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_2]], align 4
48 // IR-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
49 // IR-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
50 // IR-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
51 // IR-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
52 // IR-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
53 // IR-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP3]], 0
54 // IR-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
55 // IR-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
56 // IR-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
57 // IR-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
58 // IR-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
59 // IR-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
60 // IR-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
61 // IR-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8
62 // IR-NEXT:    store i32 0, ptr [[I8]], align 4
63 // IR-NEXT:    store i32 0, ptr [[J9]], align 4
64 // IR-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
65 // IR-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
66 // IR-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
67 // IR:       land.lhs.true:
68 // IR-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
69 // IR-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP6]]
70 // IR-NEXT:    br i1 [[CMP10]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
71 // IR:       simd.if.then:
72 // IR-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
73 // IR-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
74 // IR-NEXT:    store i32 0, ptr [[Z13]], align 4
75 // IR-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
76 // IR:       omp.inner.for.cond:
77 // IR-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]]
78 // IR-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]]
79 // IR-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]
80 // IR-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
81 // IR:       omp.inner.for.body:
82 // IR-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
83 // IR-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
84 // IR-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP11]], 0
85 // IR-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
86 // IR-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
87 // IR-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
88 // IR-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP10]], [[CONV18]]
89 // IR-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
90 // IR-NEXT:    [[ADD21:%.*]] = add nsw i64 0, [[MUL20]]
91 // IR-NEXT:    [[CONV22:%.*]] = trunc i64 [[ADD21]] to i32
92 // IR-NEXT:    store i32 [[CONV22]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP3]]
93 // IR-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
94 // IR-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
95 // IR-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
96 // IR-NEXT:    [[SUB23:%.*]] = sub nsw i32 [[TMP14]], 0
97 // IR-NEXT:    [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1
98 // IR-NEXT:    [[MUL25:%.*]] = mul nsw i32 1, [[DIV24]]
99 // IR-NEXT:    [[CONV26:%.*]] = sext i32 [[MUL25]] to i64
100 // IR-NEXT:    [[DIV27:%.*]] = sdiv i64 [[TMP13]], [[CONV26]]
101 // IR-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
102 // IR-NEXT:    [[SUB28:%.*]] = sub nsw i32 [[TMP15]], 0
103 // IR-NEXT:    [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1
104 // IR-NEXT:    [[MUL30:%.*]] = mul nsw i32 1, [[DIV29]]
105 // IR-NEXT:    [[CONV31:%.*]] = sext i32 [[MUL30]] to i64
106 // IR-NEXT:    [[MUL32:%.*]] = mul nsw i64 [[DIV27]], [[CONV31]]
107 // IR-NEXT:    [[SUB33:%.*]] = sub nsw i64 [[TMP12]], [[MUL32]]
108 // IR-NEXT:    [[MUL34:%.*]] = mul nsw i64 [[SUB33]], 1
109 // IR-NEXT:    [[ADD35:%.*]] = add nsw i64 0, [[MUL34]]
110 // IR-NEXT:    [[CONV36:%.*]] = trunc i64 [[ADD35]] to i32
111 // IR-NEXT:    store i32 [[CONV36]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP3]]
112 // IR-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP3]]
113 // IR-NEXT:    [[TMP17:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP3]]
114 // IR-NEXT:    [[ADD37:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
115 // IR-NEXT:    [[TMP18:%.*]] = load i32, ptr [[Z13]], align 4, !llvm.access.group [[ACC_GRP3]]
116 // IR-NEXT:    [[ADD38:%.*]] = add nsw i32 [[TMP18]], [[ADD37]]
117 // IR-NEXT:    store i32 [[ADD38]], ptr [[Z13]], align 4, !llvm.access.group [[ACC_GRP3]]
118 // IR-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
119 // IR:       omp.body.continue:
120 // IR-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
121 // IR:       omp.inner.for.inc:
122 // IR-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
123 // IR-NEXT:    [[ADD39:%.*]] = add nsw i64 [[TMP19]], 1
124 // IR-NEXT:    store i64 [[ADD39]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
125 // IR-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
126 // IR:       omp.inner.for.end:
127 // IR-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
128 // IR-NEXT:    [[SUB40:%.*]] = sub nsw i32 [[TMP20]], 0
129 // IR-NEXT:    [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
130 // IR-NEXT:    [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
131 // IR-NEXT:    [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
132 // IR-NEXT:    store i32 [[ADD43]], ptr [[I11]], align 4
133 // IR-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
134 // IR-NEXT:    [[SUB44:%.*]] = sub nsw i32 [[TMP21]], 0
135 // IR-NEXT:    [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1
136 // IR-NEXT:    [[MUL46:%.*]] = mul nsw i32 [[DIV45]], 1
137 // IR-NEXT:    [[ADD47:%.*]] = add nsw i32 0, [[MUL46]]
138 // IR-NEXT:    store i32 [[ADD47]], ptr [[J]], align 4
139 // IR-NEXT:    [[TMP22:%.*]] = load i32, ptr [[Z]], align 4
140 // IR-NEXT:    [[TMP23:%.*]] = load i32, ptr [[Z13]], align 4
141 // IR-NEXT:    [[ADD48:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
142 // IR-NEXT:    store i32 [[ADD48]], ptr [[Z]], align 4
143 // IR-NEXT:    br label [[SIMD_IF_END]]
144 // IR:       simd.if.end:
145 // IR-NEXT:    ret void
146 //
147 //
148 // IR-PCH-LABEL: define dso_local void @_Z3fooi
149 // IR-PCH-SAME: (i32 noundef [[T:%.*]]) #[[ATTR0:[0-9]+]] {
150 // IR-PCH-NEXT:  entry:
151 // IR-PCH-NEXT:    [[T_ADDR:%.*]] = alloca i32, align 4
152 // IR-PCH-NEXT:    [[I:%.*]] = alloca i32, align 4
153 // IR-PCH-NEXT:    [[J:%.*]] = alloca i32, align 4
154 // IR-PCH-NEXT:    [[Z:%.*]] = alloca i32, align 4
155 // IR-PCH-NEXT:    [[TMP:%.*]] = alloca i32, align 4
156 // IR-PCH-NEXT:    [[TMP2TMP1:%.*]] = alloca i32, align 4
157 // IR-PCH-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
158 // IR-PCH-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
159 // IR-PCH-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
160 // IR-PCH-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
161 // IR-PCH-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
162 // IR-PCH-NEXT:    [[I8:%.*]] = alloca i32, align 4
163 // IR-PCH-NEXT:    [[J9:%.*]] = alloca i32, align 4
164 // IR-PCH-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
165 // IR-PCH-NEXT:    [[I11:%.*]] = alloca i32, align 4
166 // IR-PCH-NEXT:    [[J12:%.*]] = alloca i32, align 4
167 // IR-PCH-NEXT:    [[Z13:%.*]] = alloca i32, align 4
168 // IR-PCH-NEXT:    store i32 [[T]], ptr [[T_ADDR]], align 4
169 // IR-PCH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_ADDR]], align 4
170 // IR-PCH-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
171 // IR-PCH-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
172 // IR-PCH-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_2]], align 4
173 // IR-PCH-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
174 // IR-PCH-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
175 // IR-PCH-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
176 // IR-PCH-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
177 // IR-PCH-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
178 // IR-PCH-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP3]], 0
179 // IR-PCH-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
180 // IR-PCH-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
181 // IR-PCH-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
182 // IR-PCH-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
183 // IR-PCH-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
184 // IR-PCH-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
185 // IR-PCH-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
186 // IR-PCH-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8
187 // IR-PCH-NEXT:    store i32 0, ptr [[I8]], align 4
188 // IR-PCH-NEXT:    store i32 0, ptr [[J9]], align 4
189 // IR-PCH-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
190 // IR-PCH-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
191 // IR-PCH-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
192 // IR-PCH:       land.lhs.true:
193 // IR-PCH-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
194 // IR-PCH-NEXT:    [[CMP10:%.*]] = icmp slt i32 0, [[TMP6]]
195 // IR-PCH-NEXT:    br i1 [[CMP10]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
196 // IR-PCH:       simd.if.then:
197 // IR-PCH-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
198 // IR-PCH-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
199 // IR-PCH-NEXT:    store i32 0, ptr [[Z13]], align 4
200 // IR-PCH-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
201 // IR-PCH:       omp.inner.for.cond:
202 // IR-PCH-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]]
203 // IR-PCH-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]]
204 // IR-PCH-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]
205 // IR-PCH-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
206 // IR-PCH:       omp.inner.for.body:
207 // IR-PCH-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
208 // IR-PCH-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
209 // IR-PCH-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP11]], 0
210 // IR-PCH-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
211 // IR-PCH-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
212 // IR-PCH-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
213 // IR-PCH-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP10]], [[CONV18]]
214 // IR-PCH-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
215 // IR-PCH-NEXT:    [[ADD21:%.*]] = add nsw i64 0, [[MUL20]]
216 // IR-PCH-NEXT:    [[CONV22:%.*]] = trunc i64 [[ADD21]] to i32
217 // IR-PCH-NEXT:    store i32 [[CONV22]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP3]]
218 // IR-PCH-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
219 // IR-PCH-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
220 // IR-PCH-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
221 // IR-PCH-NEXT:    [[SUB23:%.*]] = sub nsw i32 [[TMP14]], 0
222 // IR-PCH-NEXT:    [[DIV24:%.*]] = sdiv i32 [[SUB23]], 1
223 // IR-PCH-NEXT:    [[MUL25:%.*]] = mul nsw i32 1, [[DIV24]]
224 // IR-PCH-NEXT:    [[CONV26:%.*]] = sext i32 [[MUL25]] to i64
225 // IR-PCH-NEXT:    [[DIV27:%.*]] = sdiv i64 [[TMP13]], [[CONV26]]
226 // IR-PCH-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
227 // IR-PCH-NEXT:    [[SUB28:%.*]] = sub nsw i32 [[TMP15]], 0
228 // IR-PCH-NEXT:    [[DIV29:%.*]] = sdiv i32 [[SUB28]], 1
229 // IR-PCH-NEXT:    [[MUL30:%.*]] = mul nsw i32 1, [[DIV29]]
230 // IR-PCH-NEXT:    [[CONV31:%.*]] = sext i32 [[MUL30]] to i64
231 // IR-PCH-NEXT:    [[MUL32:%.*]] = mul nsw i64 [[DIV27]], [[CONV31]]
232 // IR-PCH-NEXT:    [[SUB33:%.*]] = sub nsw i64 [[TMP12]], [[MUL32]]
233 // IR-PCH-NEXT:    [[MUL34:%.*]] = mul nsw i64 [[SUB33]], 1
234 // IR-PCH-NEXT:    [[ADD35:%.*]] = add nsw i64 0, [[MUL34]]
235 // IR-PCH-NEXT:    [[CONV36:%.*]] = trunc i64 [[ADD35]] to i32
236 // IR-PCH-NEXT:    store i32 [[CONV36]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP3]]
237 // IR-PCH-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP3]]
238 // IR-PCH-NEXT:    [[TMP17:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP3]]
239 // IR-PCH-NEXT:    [[ADD37:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
240 // IR-PCH-NEXT:    [[TMP18:%.*]] = load i32, ptr [[Z13]], align 4, !llvm.access.group [[ACC_GRP3]]
241 // IR-PCH-NEXT:    [[ADD38:%.*]] = add nsw i32 [[TMP18]], [[ADD37]]
242 // IR-PCH-NEXT:    store i32 [[ADD38]], ptr [[Z13]], align 4, !llvm.access.group [[ACC_GRP3]]
243 // IR-PCH-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
244 // IR-PCH:       omp.body.continue:
245 // IR-PCH-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
246 // IR-PCH:       omp.inner.for.inc:
247 // IR-PCH-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
248 // IR-PCH-NEXT:    [[ADD39:%.*]] = add nsw i64 [[TMP19]], 1
249 // IR-PCH-NEXT:    store i64 [[ADD39]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
250 // IR-PCH-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
251 // IR-PCH:       omp.inner.for.end:
252 // IR-PCH-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
253 // IR-PCH-NEXT:    [[SUB40:%.*]] = sub nsw i32 [[TMP20]], 0
254 // IR-PCH-NEXT:    [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
255 // IR-PCH-NEXT:    [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
256 // IR-PCH-NEXT:    [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
257 // IR-PCH-NEXT:    store i32 [[ADD43]], ptr [[I11]], align 4
258 // IR-PCH-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
259 // IR-PCH-NEXT:    [[SUB44:%.*]] = sub nsw i32 [[TMP21]], 0
260 // IR-PCH-NEXT:    [[DIV45:%.*]] = sdiv i32 [[SUB44]], 1
261 // IR-PCH-NEXT:    [[MUL46:%.*]] = mul nsw i32 [[DIV45]], 1
262 // IR-PCH-NEXT:    [[ADD47:%.*]] = add nsw i32 0, [[MUL46]]
263 // IR-PCH-NEXT:    store i32 [[ADD47]], ptr [[J]], align 4
264 // IR-PCH-NEXT:    [[TMP22:%.*]] = load i32, ptr [[Z]], align 4
265 // IR-PCH-NEXT:    [[TMP23:%.*]] = load i32, ptr [[Z13]], align 4
266 // IR-PCH-NEXT:    [[ADD48:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
267 // IR-PCH-NEXT:    store i32 [[ADD48]], ptr [[Z]], align 4
268 // IR-PCH-NEXT:    br label [[SIMD_IF_END]]
269 // IR-PCH:       simd.if.end:
270 // IR-PCH-NEXT:    ret void
271 //
272