1 // REQUIRES: arm-registered-target 2 // RUN: %clang --target=arm-linux-gnu --print-supported-extensions | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s 3 4 // CHECK: All available -march extensions for ARM 5 // CHECK-EMPTY: 6 // CHECK-NEXT: Name Description 7 // CHECK-NEXT: crc Enable support for CRC instructions 8 // CHECK-NEXT: crypto Enable support for Cryptography extensions 9 // CHECK-NEXT: sha2 Enable SHA1 and SHA256 support 10 // CHECK-NEXT: aes Enable AES support 11 // CHECK-NEXT: dotprod Enable support for dot product instructions 12 // CHECK-NEXT: dsp Supports DSP instructions in ARM and/or Thumb2 13 // CHECK-NEXT: mve Support M-Class Vector Extension with integer ops 14 // CHECK-NEXT: mve.fp Support M-Class Vector Extension with integer and floating ops 15 // CHECK-NEXT: fp16 Enable half-precision floating point 16 // CHECK-NEXT: ras Enable Reliability, Availability and Serviceability extensions 17 // CHECK-NEXT: fp16fml Enable full half-precision floating point fml instructions 18 // CHECK-NEXT: bf16 Enable support for BFloat16 instructions 19 // CHECK-NEXT: sb Enable v8.5a Speculation Barrier 20 // CHECK-NEXT: i8mm Enable Matrix Multiply Int8 Extension 21 // CHECK-NEXT: lob Enable Low Overhead Branch extensions 22 // CHECK-NEXT: cdecp0 Coprocessor 0 ISA is CDEv1 23 // CHECK-NEXT: cdecp1 Coprocessor 1 ISA is CDEv1 24 // CHECK-NEXT: cdecp2 Coprocessor 2 ISA is CDEv1 25 // CHECK-NEXT: cdecp3 Coprocessor 3 ISA is CDEv1 26 // CHECK-NEXT: cdecp4 Coprocessor 4 ISA is CDEv1 27 // CHECK-NEXT: cdecp5 Coprocessor 5 ISA is CDEv1 28 // CHECK-NEXT: cdecp6 Coprocessor 6 ISA is CDEv1 29 // CHECK-NEXT: cdecp7 Coprocessor 7 ISA is CDEv1 30 // CHECK-NEXT: pacbti Enable Pointer Authentication and Branch Target Identification 31