xref: /llvm-project/clang/test/Driver/print-enabled-extensions/riscv-rocket-rv64.c (revision d280a9c5e22662fd24708245add50b152ab10fc8)
1 // REQUIRES: riscv-registered-target
2 // RUN: %clang --target=riscv64 --print-enabled-extensions -mcpu=rocket-rv64 | FileCheck --strict-whitespace %s
3 
4 // Simple litmus test to check the frontend handling of this option is
5 // enabled.
6 
7 // CHECK: Extensions enabled for the given RISC-V target
8 // CHECK-EMPTY:
9 // CHECK-NEXT: Name                 Version   Description
10 // CHECK-NEXT:     i                    2.1       'I' (Base Integer Instruction Set)
11 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
12 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
13 // CHECK-EMPTY:
14