xref: /llvm-project/clang/test/CodeGenHLSL/builtins/step.hlsl (revision 762f1b17b2815ccdfb4e5cb5412cb6210db92f73)
1// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
2// RUN:   dxil-pc-shadermodel6.3-library %s -fnative-half-type \
3// RUN:   -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
4// RUN:   --check-prefixes=CHECK,NATIVE_HALF \
5// RUN:   -DFNATTRS="noundef nofpclass(nan inf)" -DTARGET=dx
6// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
7// RUN:   dxil-pc-shadermodel6.3-library %s -emit-llvm -disable-llvm-passes \
8// RUN:   -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF \
9// RUN:   -DFNATTRS="noundef nofpclass(nan inf)" -DTARGET=dx
10// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
11// RUN:   spirv-unknown-vulkan-compute %s -fnative-half-type \
12// RUN:   -emit-llvm -disable-llvm-passes -o - | FileCheck %s \
13// RUN:   --check-prefixes=CHECK,NATIVE_HALF \
14// RUN:   -DFNATTRS="spir_func noundef nofpclass(nan inf)" -DTARGET=spv
15// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
16// RUN:   spirv-unknown-vulkan-compute %s -emit-llvm -disable-llvm-passes \
17// RUN:   -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF \
18// RUN:   -DFNATTRS="spir_func noundef nofpclass(nan inf)" -DTARGET=spv
19
20// NATIVE_HALF: define [[FNATTRS]] half @
21// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn half @llvm.[[TARGET]].step.f16(half
22// NO_HALF: call reassoc nnan ninf nsz arcp afn float @llvm.[[TARGET]].step.f32(float
23// NATIVE_HALF: ret half
24// NO_HALF: ret float
25half test_step_half(half p0, half p1)
26{
27    return step(p0, p1);
28}
29// NATIVE_HALF: define [[FNATTRS]] <2 x half> @
30// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <2 x half> @llvm.[[TARGET]].step.v2f16(<2 x half>
31// NO_HALF: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.[[TARGET]].step.v2f32(<2 x float>
32// NATIVE_HALF: ret <2 x half> %hlsl.step
33// NO_HALF: ret <2 x float> %hlsl.step
34half2 test_step_half2(half2 p0, half2 p1)
35{
36    return step(p0, p1);
37}
38// NATIVE_HALF: define [[FNATTRS]] <3 x half> @
39// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <3 x half> @llvm.[[TARGET]].step.v3f16(<3 x half>
40// NO_HALF: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.[[TARGET]].step.v3f32(<3 x float>
41// NATIVE_HALF: ret <3 x half> %hlsl.step
42// NO_HALF: ret <3 x float> %hlsl.step
43half3 test_step_half3(half3 p0, half3 p1)
44{
45    return step(p0, p1);
46}
47// NATIVE_HALF: define [[FNATTRS]] <4 x half> @
48// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.[[TARGET]].step.v4f16(<4 x half>
49// NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].step.v4f32(<4 x float>
50// NATIVE_HALF: ret <4 x half> %hlsl.step
51// NO_HALF: ret <4 x float> %hlsl.step
52half4 test_step_half4(half4 p0, half4 p1)
53{
54    return step(p0, p1);
55}
56
57// CHECK: define [[FNATTRS]] float @
58// CHECK: call reassoc nnan ninf nsz arcp afn float @llvm.[[TARGET]].step.f32(float
59// CHECK: ret float
60float test_step_float(float p0, float p1)
61{
62    return step(p0, p1);
63}
64// CHECK: define [[FNATTRS]] <2 x float> @
65// CHECK: %hlsl.step = call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.[[TARGET]].step.v2f32(
66// CHECK: ret <2 x float> %hlsl.step
67float2 test_step_float2(float2 p0, float2 p1)
68{
69    return step(p0, p1);
70}
71// CHECK: define [[FNATTRS]] <3 x float> @
72// CHECK: %hlsl.step = call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.[[TARGET]].step.v3f32(
73// CHECK: ret <3 x float> %hlsl.step
74float3 test_step_float3(float3 p0, float3 p1)
75{
76    return step(p0, p1);
77}
78// CHECK: define [[FNATTRS]] <4 x float> @
79// CHECK: %hlsl.step = call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].step.v4f32(
80// CHECK: ret <4 x float> %hlsl.step
81float4 test_step_float4(float4 p0, float4 p1)
82{
83    return step(p0, p1);
84}
85