1 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ 2 // RUN: -target-feature +f -target-feature +d \ 3 // RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \ 4 // RUN: | FileCheck %s --check-prefix=CHECK-64 5 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ 6 // RUN: -target-feature +f -target-feature +d \ 7 // RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \ 8 // RUN: | FileCheck %s --check-prefix=CHECK-128 9 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ 10 // RUN: -target-feature +f -target-feature +d \ 11 // RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \ 12 // RUN: | FileCheck %s --check-prefix=CHECK-256 13 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ 14 // RUN: -target-feature +f -target-feature +d \ 15 // RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \ 16 // RUN: | FileCheck %s --check-prefix=CHECK-512 17 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ 18 // RUN: -target-feature +f -target-feature +d \ 19 // RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \ 20 // RUN: | FileCheck %s --check-prefix=CHECK-1024 21 22 typedef __rvv_int8mf8_t vint8mf8_t; 23 typedef __rvv_uint8mf8_t vuint8mf8_t; 24 25 typedef __rvv_int8mf4_t vint8mf4_t; 26 typedef __rvv_uint8mf4_t vuint8mf4_t; 27 typedef __rvv_int16mf4_t vint16mf4_t; 28 typedef __rvv_uint16mf4_t vuint16mf4_t; 29 30 typedef __rvv_int8mf2_t vint8mf2_t; 31 typedef __rvv_uint8mf2_t vuint8mf2_t; 32 typedef __rvv_int16mf2_t vint16mf2_t; 33 typedef __rvv_uint16mf2_t vuint16mf2_t; 34 typedef __rvv_int32mf2_t vint32mf2_t; 35 typedef __rvv_uint32mf2_t vuint32mf2_t; 36 typedef __rvv_float32mf2_t vfloat32mf2_t; 37 38 typedef __rvv_int8m1_t vint8m1_t; 39 typedef __rvv_uint8m1_t vuint8m1_t; 40 typedef __rvv_int16m1_t vint16m1_t; 41 typedef __rvv_uint16m1_t vuint16m1_t; 42 typedef __rvv_int32m1_t vint32m1_t; 43 typedef __rvv_uint32m1_t vuint32m1_t; 44 typedef __rvv_int64m1_t vint64m1_t; 45 typedef __rvv_uint64m1_t vuint64m1_t; 46 typedef __rvv_float32m1_t vfloat32m1_t; 47 typedef __rvv_float64m1_t vfloat64m1_t; 48 49 typedef __rvv_int8m2_t vint8m2_t; 50 typedef __rvv_uint8m2_t vuint8m2_t; 51 typedef __rvv_int16m2_t vint16m2_t; 52 typedef __rvv_uint16m2_t vuint16m2_t; 53 typedef __rvv_int32m2_t vint32m2_t; 54 typedef __rvv_uint32m2_t vuint32m2_t; 55 typedef __rvv_int64m2_t vint64m2_t; 56 typedef __rvv_uint64m2_t vuint64m2_t; 57 typedef __rvv_float32m2_t vfloat32m2_t; 58 typedef __rvv_float64m2_t vfloat64m2_t; 59 60 typedef __rvv_int8m4_t vint8m4_t; 61 typedef __rvv_uint8m4_t vuint8m4_t; 62 typedef __rvv_int16m4_t vint16m4_t; 63 typedef __rvv_uint16m4_t vuint16m4_t; 64 typedef __rvv_int32m4_t vint32m4_t; 65 typedef __rvv_uint32m4_t vuint32m4_t; 66 typedef __rvv_int64m4_t vint64m4_t; 67 typedef __rvv_uint64m4_t vuint64m4_t; 68 typedef __rvv_float32m4_t vfloat32m4_t; 69 typedef __rvv_float64m4_t vfloat64m4_t; 70 71 typedef __rvv_int8m8_t vint8m8_t; 72 typedef __rvv_uint8m8_t vuint8m8_t; 73 typedef __rvv_int16m8_t vint16m8_t; 74 typedef __rvv_uint16m8_t vuint16m8_t; 75 typedef __rvv_int32m8_t vint32m8_t; 76 typedef __rvv_uint32m8_t vuint32m8_t; 77 typedef __rvv_int64m8_t vint64m8_t; 78 typedef __rvv_uint64m8_t vuint64m8_t; 79 typedef __rvv_float32m8_t vfloat32m8_t; 80 typedef __rvv_float64m8_t vfloat64m8_t; 81 82 typedef vint8mf8_t fixed_int8mf8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/8))); 83 84 typedef vuint8mf8_t fixed_uint8mf8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/8))); 85 86 typedef vint8mf4_t fixed_int8mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); 87 typedef vint16mf4_t fixed_int16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); 88 89 typedef vuint8mf4_t fixed_uint8mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); 90 typedef vuint16mf4_t fixed_uint16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); 91 92 typedef vint8mf2_t fixed_int8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 93 typedef vint16mf2_t fixed_int16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 94 typedef vint32mf2_t fixed_int32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 95 96 typedef vuint8mf2_t fixed_uint8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 97 typedef vuint16mf2_t fixed_uint16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 98 typedef vuint32mf2_t fixed_uint32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 99 100 typedef vfloat32mf2_t fixed_float32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); 101 102 typedef vint8m1_t fixed_int8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 103 typedef vint16m1_t fixed_int16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 104 typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 105 typedef vint64m1_t fixed_int64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 106 107 typedef vuint8m1_t fixed_uint8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 108 typedef vuint16m1_t fixed_uint16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 109 typedef vuint32m1_t fixed_uint32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 110 typedef vuint64m1_t fixed_uint64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 111 112 typedef vfloat32m1_t fixed_float32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 113 typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); 114 115 typedef vint8m2_t fixed_int8m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 116 typedef vint16m2_t fixed_int16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 117 typedef vint32m2_t fixed_int32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 118 typedef vint64m2_t fixed_int64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 119 120 typedef vuint8m2_t fixed_uint8m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 121 typedef vuint16m2_t fixed_uint16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 122 typedef vuint32m2_t fixed_uint32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 123 typedef vuint64m2_t fixed_uint64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 124 125 typedef vfloat32m2_t fixed_float32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 126 typedef vfloat64m2_t fixed_float64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); 127 128 typedef vint8m4_t fixed_int8m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 129 typedef vint16m4_t fixed_int16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 130 typedef vint32m4_t fixed_int32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 131 typedef vint64m4_t fixed_int64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 132 133 typedef vuint8m4_t fixed_uint8m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 134 typedef vuint16m4_t fixed_uint16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 135 typedef vuint32m4_t fixed_uint32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 136 typedef vuint64m4_t fixed_uint64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 137 138 typedef vfloat32m4_t fixed_float32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 139 typedef vfloat64m4_t fixed_float64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); 140 141 typedef vint8m8_t fixed_int8m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 142 typedef vint16m8_t fixed_int16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 143 typedef vint32m8_t fixed_int32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 144 typedef vint64m8_t fixed_int64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 145 146 typedef vuint8m8_t fixed_uint8m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 147 typedef vuint16m8_t fixed_uint16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 148 typedef vuint32m8_t fixed_uint32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 149 typedef vuint64m8_t fixed_uint64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 150 151 typedef vfloat32m8_t fixed_float32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 152 typedef vfloat64m8_t fixed_float64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); 153 154 namespace std { 155 class type_info; 156 }; 157 158 auto &fs8 = typeid(fixed_int8m1_t); 159 auto &fs16 = typeid(fixed_int16m1_t); 160 auto &fs32 = typeid(fixed_int32m1_t); 161 auto &fs64 = typeid(fixed_int64m1_t); 162 163 auto &fu8 = typeid(fixed_uint8m1_t); 164 auto &fu16 = typeid(fixed_uint16m1_t); 165 auto &fu32 = typeid(fixed_uint32m1_t); 166 auto &fu64 = typeid(fixed_uint64m1_t); 167 168 auto &ff32 = typeid(fixed_float32m1_t); 169 auto &ff64 = typeid(fixed_float64m1_t); 170 171 auto &fs8m2 = typeid(fixed_int8m2_t); 172 auto &fs16m2 = typeid(fixed_int16m2_t); 173 auto &fs32m2 = typeid(fixed_int32m2_t); 174 auto &fs64m2 = typeid(fixed_int64m2_t); 175 176 auto &fu8m2 = typeid(fixed_uint8m2_t); 177 auto &fu16m2 = typeid(fixed_uint16m2_t); 178 auto &fu32m2 = typeid(fixed_uint32m2_t); 179 auto &fu64m2 = typeid(fixed_uint64m2_t); 180 181 auto &ff32m2 = typeid(fixed_float32m2_t); 182 auto &ff64m2 = typeid(fixed_float64m2_t); 183 184 auto &fs8m4 = typeid(fixed_int8m4_t); 185 auto &fs16m4 = typeid(fixed_int16m4_t); 186 auto &fs32m4 = typeid(fixed_int32m4_t); 187 auto &fs64m4 = typeid(fixed_int64m4_t); 188 189 auto &fu8m4 = typeid(fixed_uint8m4_t); 190 auto &fu16m4 = typeid(fixed_uint16m4_t); 191 auto &fu32m4 = typeid(fixed_uint32m4_t); 192 auto &fu64m4 = typeid(fixed_uint64m4_t); 193 194 auto &ff32m4 = typeid(fixed_float32m4_t); 195 auto &ff64m4 = typeid(fixed_float64m4_t); 196 197 auto &fs8m8 = typeid(fixed_int8m8_t); 198 auto &fs16m8 = typeid(fixed_int16m8_t); 199 auto &fs32m8 = typeid(fixed_int32m8_t); 200 auto &fs64m8 = typeid(fixed_int64m8_t); 201 202 auto &fu8m8 = typeid(fixed_uint8m8_t); 203 auto &fu16m8 = typeid(fixed_uint16m8_t); 204 auto &fu32m8 = typeid(fixed_uint32m8_t); 205 auto &fu64m8 = typeid(fixed_uint64m8_t); 206 207 auto &ff32m8 = typeid(fixed_float32m8_t); 208 auto &ff64m8 = typeid(fixed_float64m8_t); 209 210 auto &fs8mf2 = typeid(fixed_int8mf2_t); 211 auto &fs16mf2 = typeid(fixed_int16mf2_t); 212 auto &fs32mf2 = typeid(fixed_int32mf2_t); 213 214 auto &fu8mf2 = typeid(fixed_uint8mf2_t); 215 auto &fu16mf2 = typeid(fixed_uint16mf2_t); 216 auto &fu32mf2 = typeid(fixed_uint32mf2_t); 217 218 auto &ff32mf2 = typeid(fixed_float32mf2_t); 219 220 auto &fs8mf4 = typeid(fixed_int8mf4_t); 221 auto &fs16mf4 = typeid(fixed_int16mf4_t); 222 223 auto &fu8mf4 = typeid(fixed_uint8mf4_t); 224 auto &fu16mf4 = typeid(fixed_uint16mf4_t); 225 226 auto &fs8mf8 = typeid(fixed_int8mf8_t); 227 228 auto &fu8mf8 = typeid(fixed_uint8mf8_t); 229 230 // CHECK-64: @_ZTI9__RVV_VLSIu14__rvv_int8m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m1_tLj64EE 231 // CHECK-128: @_ZTI9__RVV_VLSIu14__rvv_int8m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m1_tLj128EE 232 // CHECK-256: @_ZTI9__RVV_VLSIu14__rvv_int8m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m1_tLj256EE 233 // CHECK-512: @_ZTI9__RVV_VLSIu14__rvv_int8m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m1_tLj512EE 234 // CHECK-1024: @_ZTI9__RVV_VLSIu14__rvv_int8m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m1_tLj1024EE 235 236 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int16m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m1_tLj64EE 237 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int16m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m1_tLj128EE 238 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int16m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m1_tLj256EE 239 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int16m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m1_tLj512EE 240 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int16m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m1_tLj1024EE 241 242 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int32m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m1_tLj64EE 243 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int32m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m1_tLj128EE 244 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int32m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m1_tLj256EE 245 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int32m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m1_tLj512EE 246 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int32m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m1_tLj1024EE 247 248 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int64m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m1_tLj64EE 249 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int64m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m1_tLj128EE 250 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int64m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m1_tLj256EE 251 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int64m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m1_tLj512EE 252 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int64m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m1_tLj1024EE 253 254 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_uint8m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m1_tLj64EE 255 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_uint8m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m1_tLj128EE 256 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_uint8m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m1_tLj256EE 257 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_uint8m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m1_tLj512EE 258 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_uint8m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m1_tLj1024EE 259 260 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint16m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m1_tLj64EE 261 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint16m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m1_tLj128EE 262 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint16m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m1_tLj256EE 263 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint16m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m1_tLj512EE 264 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint16m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m1_tLj1024EE 265 266 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint32m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m1_tLj64EE 267 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint32m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m1_tLj128EE 268 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint32m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m1_tLj256EE 269 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint32m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m1_tLj512EE 270 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint32m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m1_tLj1024EE 271 272 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint64m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m1_tLj64EE 273 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint64m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m1_tLj128EE 274 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint64m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m1_tLj256EE 275 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint64m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m1_tLj512EE 276 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint64m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m1_tLj1024EE 277 278 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float32m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m1_tLj64EE 279 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float32m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m1_tLj128EE 280 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float32m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m1_tLj256EE 281 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float32m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m1_tLj512EE 282 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float32m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m1_tLj1024EE 283 284 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float64m1_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m1_tLj64EE 285 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float64m1_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m1_tLj128EE 286 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float64m1_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m1_tLj256EE 287 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float64m1_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m1_tLj512EE 288 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float64m1_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m1_tLj1024EE 289 290 // CHECK-64: @_ZTI9__RVV_VLSIu14__rvv_int8m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m2_tLj128EE 291 // CHECK-128: @_ZTI9__RVV_VLSIu14__rvv_int8m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m2_tLj256EE 292 // CHECK-256: @_ZTI9__RVV_VLSIu14__rvv_int8m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m2_tLj512EE 293 // CHECK-512: @_ZTI9__RVV_VLSIu14__rvv_int8m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m2_tLj1024EE 294 // CHECK-1024: @_ZTI9__RVV_VLSIu14__rvv_int8m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m2_tLj2048EE 295 296 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int16m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m2_tLj128EE 297 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int16m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m2_tLj256EE 298 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int16m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m2_tLj512EE 299 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int16m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m2_tLj1024EE 300 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int16m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m2_tLj2048EE 301 302 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int32m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m2_tLj128EE 303 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int32m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m2_tLj256EE 304 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int32m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m2_tLj512EE 305 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int32m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m2_tLj1024EE 306 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int32m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m2_tLj2048EE 307 308 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int64m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m2_tLj128EE 309 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int64m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m2_tLj256EE 310 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int64m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m2_tLj512EE 311 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int64m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m2_tLj1024EE 312 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int64m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m2_tLj2048EE 313 314 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_uint8m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m2_tLj128EE 315 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_uint8m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m2_tLj256EE 316 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_uint8m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m2_tLj512EE 317 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_uint8m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m2_tLj1024EE 318 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_uint8m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m2_tLj2048EE 319 320 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint16m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m2_tLj128EE 321 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint16m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m2_tLj256EE 322 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint16m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m2_tLj512EE 323 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint16m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m2_tLj1024EE 324 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint16m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m2_tLj2048EE 325 326 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint32m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m2_tLj128EE 327 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint32m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m2_tLj256EE 328 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint32m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m2_tLj512EE 329 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint32m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m2_tLj1024EE 330 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint32m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m2_tLj2048EE 331 332 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint64m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m2_tLj128EE 333 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint64m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m2_tLj256EE 334 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint64m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m2_tLj512EE 335 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint64m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m2_tLj1024EE 336 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint64m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m2_tLj2048EE 337 338 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float32m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m2_tLj128EE 339 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float32m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m2_tLj256EE 340 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float32m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m2_tLj512EE 341 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float32m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m2_tLj1024EE 342 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float32m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m2_tLj2048EE 343 344 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float64m2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m2_tLj128EE 345 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float64m2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m2_tLj256EE 346 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float64m2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m2_tLj512EE 347 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float64m2_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m2_tLj1024EE 348 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float64m2_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m2_tLj2048EE 349 350 // CHECK-64: @_ZTI9__RVV_VLSIu14__rvv_int8m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m4_tLj256EE 351 // CHECK-128: @_ZTI9__RVV_VLSIu14__rvv_int8m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m4_tLj512EE 352 // CHECK-256: @_ZTI9__RVV_VLSIu14__rvv_int8m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m4_tLj1024EE 353 // CHECK-512: @_ZTI9__RVV_VLSIu14__rvv_int8m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m4_tLj2048EE 354 // CHECK-1024: @_ZTI9__RVV_VLSIu14__rvv_int8m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m4_tLj4096EE 355 356 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int16m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m4_tLj256EE 357 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int16m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m4_tLj512EE 358 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int16m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m4_tLj1024EE 359 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int16m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m4_tLj2048EE 360 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int16m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m4_tLj4096EE 361 362 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int32m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m4_tLj256EE 363 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int32m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m4_tLj512EE 364 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int32m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m4_tLj1024EE 365 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int32m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m4_tLj2048EE 366 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int32m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m4_tLj4096EE 367 368 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int64m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m4_tLj256EE 369 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int64m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m4_tLj512EE 370 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int64m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m4_tLj1024EE 371 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int64m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m4_tLj2048EE 372 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int64m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m4_tLj4096EE 373 374 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_uint8m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m4_tLj256EE 375 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_uint8m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m4_tLj512EE 376 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_uint8m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m4_tLj1024EE 377 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_uint8m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m4_tLj2048EE 378 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_uint8m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m4_tLj4096EE 379 380 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint16m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m4_tLj256EE 381 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint16m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m4_tLj512EE 382 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint16m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m4_tLj1024EE 383 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint16m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m4_tLj2048EE 384 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint16m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m4_tLj4096EE 385 386 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint32m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m4_tLj256EE 387 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint32m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m4_tLj512EE 388 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint32m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m4_tLj1024EE 389 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint32m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m4_tLj2048EE 390 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint32m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m4_tLj4096EE 391 392 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint64m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m4_tLj256EE 393 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint64m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m4_tLj512EE 394 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint64m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m4_tLj1024EE 395 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint64m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m4_tLj2048EE 396 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint64m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m4_tLj4096EE 397 398 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float32m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m4_tLj256EE 399 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float32m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m4_tLj512EE 400 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float32m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m4_tLj1024EE 401 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float32m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m4_tLj2048EE 402 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float32m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m4_tLj4096EE 403 404 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float64m4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m4_tLj256EE 405 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float64m4_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m4_tLj512EE 406 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float64m4_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m4_tLj1024EE 407 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float64m4_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m4_tLj2048EE 408 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float64m4_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m4_tLj4096EE 409 410 // CHECK-64: @_ZTI9__RVV_VLSIu14__rvv_int8m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m8_tLj512EE 411 // CHECK-128: @_ZTI9__RVV_VLSIu14__rvv_int8m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m8_tLj1024EE 412 // CHECK-256: @_ZTI9__RVV_VLSIu14__rvv_int8m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m8_tLj2048EE 413 // CHECK-512: @_ZTI9__RVV_VLSIu14__rvv_int8m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m8_tLj4096EE 414 // CHECK-1024: @_ZTI9__RVV_VLSIu14__rvv_int8m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu14__rvv_int8m8_tLj8192EE 415 416 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int16m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m8_tLj512EE 417 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int16m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m8_tLj1024EE 418 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int16m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m8_tLj2048EE 419 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int16m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m8_tLj4096EE 420 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int16m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int16m8_tLj8192EE 421 422 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int32m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m8_tLj512EE 423 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int32m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m8_tLj1024EE 424 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int32m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m8_tLj2048EE 425 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int32m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m8_tLj4096EE 426 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int32m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int32m8_tLj8192EE 427 428 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int64m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m8_tLj512EE 429 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int64m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m8_tLj1024EE 430 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int64m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m8_tLj2048EE 431 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int64m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m8_tLj4096EE 432 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int64m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int64m8_tLj8192EE 433 434 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_uint8m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m8_tLj512EE 435 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_uint8m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m8_tLj1024EE 436 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_uint8m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m8_tLj2048EE 437 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_uint8m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m8_tLj4096EE 438 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_uint8m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_uint8m8_tLj8192EE 439 440 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint16m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m8_tLj512EE 441 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint16m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m8_tLj1024EE 442 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint16m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m8_tLj2048EE 443 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint16m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m8_tLj4096EE 444 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint16m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint16m8_tLj8192EE 445 446 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint32m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m8_tLj512EE 447 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint32m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m8_tLj1024EE 448 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint32m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m8_tLj2048EE 449 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint32m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m8_tLj4096EE 450 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint32m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint32m8_tLj8192EE 451 452 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint64m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m8_tLj512EE 453 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint64m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m8_tLj1024EE 454 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint64m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m8_tLj2048EE 455 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint64m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m8_tLj4096EE 456 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint64m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint64m8_tLj8192EE 457 458 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float32m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m8_tLj512EE 459 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float32m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m8_tLj1024EE 460 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float32m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m8_tLj2048EE 461 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float32m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m8_tLj4096EE 462 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float32m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float32m8_tLj8192EE 463 464 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_float64m8_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m8_tLj512EE 465 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_float64m8_tLj1024EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m8_tLj1024EE 466 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_float64m8_tLj2048EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m8_tLj2048EE 467 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_float64m8_tLj4096EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m8_tLj4096EE 468 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_float64m8_tLj8192EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_float64m8_tLj8192EE 469 // 470 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int8mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf2_tLj32EE 471 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int8mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf2_tLj64EE 472 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int8mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf2_tLj128EE 473 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int8mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf2_tLj256EE 474 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int8mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf2_tLj512EE 475 476 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_int16mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf2_tLj32EE 477 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_int16mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf2_tLj64EE 478 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_int16mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf2_tLj128EE 479 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_int16mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf2_tLj256EE 480 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_int16mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf2_tLj512EE 481 482 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_int32mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int32mf2_tLj32EE 483 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_int32mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int32mf2_tLj64EE 484 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_int32mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int32mf2_tLj128EE 485 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_int32mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int32mf2_tLj256EE 486 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_int32mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int32mf2_tLj512EE 487 488 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint8mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf2_tLj32EE 489 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint8mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf2_tLj64EE 490 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint8mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf2_tLj128EE 491 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint8mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf2_tLj256EE 492 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint8mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf2_tLj512EE 493 494 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_uint16mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf2_tLj32EE 495 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_uint16mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf2_tLj64EE 496 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_uint16mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf2_tLj128EE 497 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_uint16mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf2_tLj256EE 498 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_uint16mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf2_tLj512EE 499 500 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_uint32mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint32mf2_tLj32EE 501 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_uint32mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint32mf2_tLj64EE 502 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_uint32mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint32mf2_tLj128EE 503 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_uint32mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint32mf2_tLj256EE 504 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_uint32mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint32mf2_tLj512EE 505 506 // CHECK-64: @_ZTI9__RVV_VLSIu18__rvv_float32mf2_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu18__rvv_float32mf2_tLj32EE 507 // CHECK-128: @_ZTI9__RVV_VLSIu18__rvv_float32mf2_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu18__rvv_float32mf2_tLj64EE 508 // CHECK-256: @_ZTI9__RVV_VLSIu18__rvv_float32mf2_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu18__rvv_float32mf2_tLj128EE 509 // CHECK-512: @_ZTI9__RVV_VLSIu18__rvv_float32mf2_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu18__rvv_float32mf2_tLj256EE 510 // CHECK-1024: @_ZTI9__RVV_VLSIu18__rvv_float32mf2_tLj512EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu18__rvv_float32mf2_tLj512EE 511 // 512 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int8mf4_tLj16EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf4_tLj16EE 513 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int8mf4_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf4_tLj32EE 514 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int8mf4_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf4_tLj64EE 515 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int8mf4_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf4_tLj128EE 516 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int8mf4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf4_tLj256EE 517 518 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_int16mf4_tLj16EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf4_tLj16EE 519 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_int16mf4_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf4_tLj32EE 520 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_int16mf4_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf4_tLj64EE 521 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_int16mf4_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf4_tLj128EE 522 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_int16mf4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_int16mf4_tLj256EE 523 524 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint8mf4_tLj16EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf4_tLj16EE 525 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint8mf4_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf4_tLj32EE 526 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint8mf4_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf4_tLj64EE 527 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint8mf4_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf4_tLj128EE 528 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint8mf4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf4_tLj256EE 529 530 // CHECK-64: @_ZTI9__RVV_VLSIu17__rvv_uint16mf4_tLj16EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf4_tLj16EE 531 // CHECK-128: @_ZTI9__RVV_VLSIu17__rvv_uint16mf4_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf4_tLj32EE 532 // CHECK-256: @_ZTI9__RVV_VLSIu17__rvv_uint16mf4_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf4_tLj64EE 533 // CHECK-512: @_ZTI9__RVV_VLSIu17__rvv_uint16mf4_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf4_tLj128EE 534 // CHECK-1024: @_ZTI9__RVV_VLSIu17__rvv_uint16mf4_tLj256EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu17__rvv_uint16mf4_tLj256EE 535 // 536 // CHECK-64: @_ZTI9__RVV_VLSIu15__rvv_int8mf8_tLj8EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf8_tLj8EE 537 // CHECK-128: @_ZTI9__RVV_VLSIu15__rvv_int8mf8_tLj16EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf8_tLj16EE 538 // CHECK-256: @_ZTI9__RVV_VLSIu15__rvv_int8mf8_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf8_tLj32EE 539 // CHECK-512: @_ZTI9__RVV_VLSIu15__rvv_int8mf8_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf8_tLj64EE 540 // CHECK-1024: @_ZTI9__RVV_VLSIu15__rvv_int8mf8_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu15__rvv_int8mf8_tLj128EE 541 542 // CHECK-64: @_ZTI9__RVV_VLSIu16__rvv_uint8mf8_tLj8EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf8_tLj8EE 543 // CHECK-128: @_ZTI9__RVV_VLSIu16__rvv_uint8mf8_tLj16EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf8_tLj16EE 544 // CHECK-256: @_ZTI9__RVV_VLSIu16__rvv_uint8mf8_tLj32EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf8_tLj32EE 545 // CHECK-512: @_ZTI9__RVV_VLSIu16__rvv_uint8mf8_tLj64EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf8_tLj64EE 546 // CHECK-1024: @_ZTI9__RVV_VLSIu16__rvv_uint8mf8_tLj128EE = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTS9__RVV_VLSIu16__rvv_uint8mf8_tLj128EE 547