xref: /llvm-project/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp (revision 635d20e9e72e25966b196bb012a90e750ae00c6d) 
1 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
2 // RUN:  -target-feature +f -target-feature +d -target-feature +zfh \
3 // RUN:  -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \
4 // RUN:   -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64
5 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
6 // RUN:  -target-feature +f -target-feature +d -target-feature +zfh \
7 // RUN:  -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \
8 // RUN:  -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128
9 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
10 // RUN:  -target-feature +f -target-feature +d -target-feature +zfh \
11 // RUN:  -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \
12 // RUN:  -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256
13 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
14 // RUN:  -target-feature +f -target-feature +d -target-feature +zfh \
15 // RUN:  -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \
16 // RUN:  -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512
17 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
18 // RUN:  -target-feature +f -target-feature +d -target-feature +zfh \
19 // RUN:  -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \
20 // RUN:  -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024
21 
22 typedef __rvv_int8mf8_t vint8mf8_t;
23 typedef __rvv_uint8mf8_t vuint8mf8_t;
24 
25 typedef __rvv_int8mf4_t vint8mf4_t;
26 typedef __rvv_uint8mf4_t vuint8mf4_t;
27 typedef __rvv_int16mf4_t vint16mf4_t;
28 typedef __rvv_uint16mf4_t vuint16mf4_t;
29 typedef __rvv_float16mf4_t vfloat16mf4_t;
30 
31 typedef __rvv_int8mf2_t vint8mf2_t;
32 typedef __rvv_uint8mf2_t vuint8mf2_t;
33 typedef __rvv_int16mf2_t vint16mf2_t;
34 typedef __rvv_uint16mf2_t vuint16mf2_t;
35 typedef __rvv_int32mf2_t vint32mf2_t;
36 typedef __rvv_uint32mf2_t vuint32mf2_t;
37 typedef __rvv_float16mf2_t vfloat16mf2_t;
38 typedef __rvv_float32mf2_t vfloat32mf2_t;
39 
40 typedef __rvv_int8m1_t vint8m1_t;
41 typedef __rvv_uint8m1_t vuint8m1_t;
42 typedef __rvv_int16m1_t vint16m1_t;
43 typedef __rvv_uint16m1_t vuint16m1_t;
44 typedef __rvv_int32m1_t vint32m1_t;
45 typedef __rvv_uint32m1_t vuint32m1_t;
46 typedef __rvv_int64m1_t vint64m1_t;
47 typedef __rvv_uint64m1_t vuint64m1_t;
48 typedef __rvv_float16m1_t vfloat16m1_t;
49 typedef __rvv_float32m1_t vfloat32m1_t;
50 typedef __rvv_float64m1_t vfloat64m1_t;
51 
52 typedef __rvv_int8m2_t vint8m2_t;
53 typedef __rvv_uint8m2_t vuint8m2_t;
54 typedef __rvv_int16m2_t vint16m2_t;
55 typedef __rvv_uint16m2_t vuint16m2_t;
56 typedef __rvv_int32m2_t vint32m2_t;
57 typedef __rvv_uint32m2_t vuint32m2_t;
58 typedef __rvv_int64m2_t vint64m2_t;
59 typedef __rvv_uint64m2_t vuint64m2_t;
60 typedef __rvv_float16m2_t vfloat16m2_t;
61 typedef __rvv_float32m2_t vfloat32m2_t;
62 typedef __rvv_float64m2_t vfloat64m2_t;
63 
64 typedef __rvv_int8m4_t vint8m4_t;
65 typedef __rvv_uint8m4_t vuint8m4_t;
66 typedef __rvv_int16m4_t vint16m4_t;
67 typedef __rvv_uint16m4_t vuint16m4_t;
68 typedef __rvv_int32m4_t vint32m4_t;
69 typedef __rvv_uint32m4_t vuint32m4_t;
70 typedef __rvv_int64m4_t vint64m4_t;
71 typedef __rvv_uint64m4_t vuint64m4_t;
72 typedef __rvv_float16m4_t vfloat16m4_t;
73 typedef __rvv_float32m4_t vfloat32m4_t;
74 typedef __rvv_float64m4_t vfloat64m4_t;
75 
76 typedef __rvv_int8m8_t vint8m8_t;
77 typedef __rvv_uint8m8_t vuint8m8_t;
78 typedef __rvv_int16m8_t vint16m8_t;
79 typedef __rvv_uint16m8_t vuint16m8_t;
80 typedef __rvv_int32m8_t vint32m8_t;
81 typedef __rvv_uint32m8_t vuint32m8_t;
82 typedef __rvv_int64m8_t vint64m8_t;
83 typedef __rvv_uint64m8_t vuint64m8_t;
84 typedef __rvv_float16m8_t vfloat16m8_t;
85 typedef __rvv_float32m8_t vfloat32m8_t;
86 typedef __rvv_float64m8_t vfloat64m8_t;
87 
88 typedef __rvv_bool1_t vbool1_t;
89 typedef __rvv_bool2_t vbool2_t;
90 typedef __rvv_bool4_t vbool4_t;
91 typedef __rvv_bool8_t vbool8_t;
92 typedef __rvv_bool16_t vbool16_t;
93 typedef __rvv_bool32_t vbool32_t;
94 typedef __rvv_bool64_t vbool64_t;
95 
96 typedef vint8mf8_t fixed_int8mf8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/8)));
97 
98 typedef vuint8mf8_t fixed_uint8mf8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/8)));
99 
100 typedef vint8mf4_t fixed_int8mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
101 typedef vint16mf4_t fixed_int16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
102 
103 typedef vuint8mf4_t fixed_uint8mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
104 typedef vuint16mf4_t fixed_uint16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
105 
106 typedef vfloat16mf4_t fixed_float16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
107 
108 typedef vint8mf2_t fixed_int8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
109 typedef vint16mf2_t fixed_int16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
110 typedef vint32mf2_t fixed_int32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
111 
112 typedef vuint8mf2_t fixed_uint8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
113 typedef vuint16mf2_t fixed_uint16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
114 typedef vuint32mf2_t fixed_uint32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
115 
116 typedef vfloat16mf2_t fixed_float16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
117 typedef vfloat32mf2_t fixed_float32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
118 
119 typedef vint8m1_t fixed_int8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
120 typedef vint16m1_t fixed_int16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
121 typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
122 typedef vint64m1_t fixed_int64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
123 
124 typedef vuint8m1_t fixed_uint8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
125 typedef vuint16m1_t fixed_uint16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
126 typedef vuint32m1_t fixed_uint32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
127 typedef vuint64m1_t fixed_uint64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
128 
129 typedef vfloat16m1_t fixed_float16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
130 typedef vfloat32m1_t fixed_float32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
131 typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
132 
133 typedef vint8m2_t fixed_int8m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
134 typedef vint16m2_t fixed_int16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
135 typedef vint32m2_t fixed_int32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
136 typedef vint64m2_t fixed_int64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
137 
138 typedef vuint8m2_t fixed_uint8m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
139 typedef vuint16m2_t fixed_uint16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
140 typedef vuint32m2_t fixed_uint32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
141 typedef vuint64m2_t fixed_uint64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
142 
143 typedef vfloat16m2_t fixed_float16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
144 typedef vfloat32m2_t fixed_float32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
145 typedef vfloat64m2_t fixed_float64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
146 
147 typedef vint8m4_t fixed_int8m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
148 typedef vint16m4_t fixed_int16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
149 typedef vint32m4_t fixed_int32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
150 typedef vint64m4_t fixed_int64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
151 
152 typedef vuint8m4_t fixed_uint8m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
153 typedef vuint16m4_t fixed_uint16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
154 typedef vuint32m4_t fixed_uint32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
155 typedef vuint64m4_t fixed_uint64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
156 
157 typedef vfloat16m4_t fixed_float16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
158 typedef vfloat32m4_t fixed_float32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
159 typedef vfloat64m4_t fixed_float64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
160 
161 typedef vint8m8_t fixed_int8m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
162 typedef vint16m8_t fixed_int16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
163 typedef vint32m8_t fixed_int32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
164 typedef vint64m8_t fixed_int64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
165 
166 typedef vuint8m8_t fixed_uint8m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
167 typedef vuint16m8_t fixed_uint16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
168 typedef vuint32m8_t fixed_uint32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
169 typedef vuint64m8_t fixed_uint64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
170 
171 typedef vfloat16m8_t fixed_float16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
172 typedef vfloat32m8_t fixed_float32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
173 typedef vfloat64m8_t fixed_float64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
174 
175 typedef vbool1_t fixed_bool1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
176 typedef vbool2_t fixed_bool2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
177 typedef vbool4_t fixed_bool4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
178 typedef vbool8_t fixed_bool8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/8)));
179 typedef vbool16_t fixed_bool16_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/16)));
180 typedef vbool32_t fixed_bool32_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/32)));
181 typedef vbool64_t fixed_bool64_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/64)));
182 
183 template <typename T> struct S {};
184 
185 // CHECK-64: _Z2f11SI9__RVV_VLSIu14__rvv_int8m1_tLj64EEE
186 // CHECK-128: _Z2f11SI9__RVV_VLSIu14__rvv_int8m1_tLj128EEE
187 // CHECK-256: _Z2f11SI9__RVV_VLSIu14__rvv_int8m1_tLj256EEE
188 // CHECK-512: _Z2f11SI9__RVV_VLSIu14__rvv_int8m1_tLj512EEE
189 // CHECK-1024: _Z2f11SI9__RVV_VLSIu14__rvv_int8m1_tLj1024EEE
190 void f1(S<fixed_int8m1_t>) {}
191 
192 // CHECK-64: _Z2f21SI9__RVV_VLSIu15__rvv_int16m1_tLj64EEE
193 // CHECK-128: _Z2f21SI9__RVV_VLSIu15__rvv_int16m1_tLj128EEE
194 // CHECK-256: _Z2f21SI9__RVV_VLSIu15__rvv_int16m1_tLj256EEE
195 // CHECK-512: _Z2f21SI9__RVV_VLSIu15__rvv_int16m1_tLj512EEE
196 // CHECK-1024: _Z2f21SI9__RVV_VLSIu15__rvv_int16m1_tLj1024EEE
197 void f2(S<fixed_int16m1_t>) {}
198 
199 // CHECK-64: _Z2f31SI9__RVV_VLSIu15__rvv_int32m1_tLj64EEE
200 // CHECK-128: _Z2f31SI9__RVV_VLSIu15__rvv_int32m1_tLj128EEE
201 // CHECK-256: _Z2f31SI9__RVV_VLSIu15__rvv_int32m1_tLj256EEE
202 // CHECK-512: _Z2f31SI9__RVV_VLSIu15__rvv_int32m1_tLj512EEE
203 // CHECK-1024: _Z2f31SI9__RVV_VLSIu15__rvv_int32m1_tLj1024EEE
204 void f3(S<fixed_int32m1_t>) {}
205 
206 // CHECK-64: _Z2f41SI9__RVV_VLSIu15__rvv_int64m1_tLj64EEE
207 // CHECK-128: _Z2f41SI9__RVV_VLSIu15__rvv_int64m1_tLj128EEE
208 // CHECK-256: _Z2f41SI9__RVV_VLSIu15__rvv_int64m1_tLj256EEE
209 // CHECK-512: _Z2f41SI9__RVV_VLSIu15__rvv_int64m1_tLj512EEE
210 // CHECK-1024: _Z2f41SI9__RVV_VLSIu15__rvv_int64m1_tLj1024EEE
211 void f4(S<fixed_int64m1_t>) {}
212 
213 // CHECK-64: _Z2f51SI9__RVV_VLSIu15__rvv_uint8m1_tLj64EEE
214 // CHECK-128: _Z2f51SI9__RVV_VLSIu15__rvv_uint8m1_tLj128EEE
215 // CHECK-256: _Z2f51SI9__RVV_VLSIu15__rvv_uint8m1_tLj256EEE
216 // CHECK-512: _Z2f51SI9__RVV_VLSIu15__rvv_uint8m1_tLj512EEE
217 // CHECK-1024: _Z2f51SI9__RVV_VLSIu15__rvv_uint8m1_tLj1024EEE
218 void f5(S<fixed_uint8m1_t>) {}
219 
220 // CHECK-64: _Z2f61SI9__RVV_VLSIu16__rvv_uint16m1_tLj64EEE
221 // CHECK-128: _Z2f61SI9__RVV_VLSIu16__rvv_uint16m1_tLj128EEE
222 // CHECK-256: _Z2f61SI9__RVV_VLSIu16__rvv_uint16m1_tLj256EEE
223 // CHECK-512: _Z2f61SI9__RVV_VLSIu16__rvv_uint16m1_tLj512EEE
224 // CHECK-1024: _Z2f61SI9__RVV_VLSIu16__rvv_uint16m1_tLj1024EEE
225 void f6(S<fixed_uint16m1_t>) {}
226 
227 // CHECK-64: _Z2f71SI9__RVV_VLSIu16__rvv_uint32m1_tLj64EEE
228 // CHECK-128: _Z2f71SI9__RVV_VLSIu16__rvv_uint32m1_tLj128EEE
229 // CHECK-256: _Z2f71SI9__RVV_VLSIu16__rvv_uint32m1_tLj256EEE
230 // CHECK-512: _Z2f71SI9__RVV_VLSIu16__rvv_uint32m1_tLj512EEE
231 // CHECK-1024: _Z2f71SI9__RVV_VLSIu16__rvv_uint32m1_tLj1024EEE
232 void f7(S<fixed_uint32m1_t>) {}
233 
234 // CHECK-64: _Z2f81SI9__RVV_VLSIu16__rvv_uint64m1_tLj64EEE
235 // CHECK-128: _Z2f81SI9__RVV_VLSIu16__rvv_uint64m1_tLj128EEE
236 // CHECK-256: _Z2f81SI9__RVV_VLSIu16__rvv_uint64m1_tLj256EEE
237 // CHECK-512: _Z2f81SI9__RVV_VLSIu16__rvv_uint64m1_tLj512EEE
238 // CHECK-1024: _Z2f81SI9__RVV_VLSIu16__rvv_uint64m1_tLj1024EEE
239 void f8(S<fixed_uint64m1_t>) {}
240 
241 // CHECK-64: _Z2f91SI9__RVV_VLSIu17__rvv_float32m1_tLj64EEE
242 // CHECK-128: _Z2f91SI9__RVV_VLSIu17__rvv_float32m1_tLj128EEE
243 // CHECK-256: _Z2f91SI9__RVV_VLSIu17__rvv_float32m1_tLj256EEE
244 // CHECK-512: _Z2f91SI9__RVV_VLSIu17__rvv_float32m1_tLj512EEE
245 // CHECK-1024: _Z2f91SI9__RVV_VLSIu17__rvv_float32m1_tLj1024EEE
246 void f9(S<fixed_float32m1_t>) {}
247 
248 // CHECK-64: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj64EEE
249 // CHECK-128: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj128EEE
250 // CHECK-256: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj256EEE
251 // CHECK-512: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj512EEE
252 // CHECK-1024: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj1024EEE
253 void f10(S<fixed_float64m1_t>) {}
254 
255 // CHECK-64: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj64EEE
256 // CHECK-128: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj128EEE
257 // CHECK-256: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj256EEE
258 // CHECK-512: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj512EEE
259 // CHECK-1024: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj1024EEE
260 void f11(S<fixed_float16m1_t>) {}
261 
262 // CHECK-64: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj128EEE
263 // CHECK-128: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj256EEE
264 // CHECK-256: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj512EEE
265 // CHECK-512: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj1024EEE
266 // CHECK-1024: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj2048EEE
267 void m2f1(S<fixed_int8m2_t>) {}
268 
269 // CHECK-64: _Z4m2f21SI9__RVV_VLSIu15__rvv_int16m2_tLj128EEE
270 // CHECK-128: _Z4m2f21SI9__RVV_VLSIu15__rvv_int16m2_tLj256EEE
271 // CHECK-256: _Z4m2f21SI9__RVV_VLSIu15__rvv_int16m2_tLj512EEE
272 // CHECK-512: _Z4m2f21SI9__RVV_VLSIu15__rvv_int16m2_tLj1024EEE
273 // CHECK-1024: _Z4m2f21SI9__RVV_VLSIu15__rvv_int16m2_tLj2048EEE
274 void m2f2(S<fixed_int16m2_t>) {}
275 
276 // CHECK-64: _Z4m2f31SI9__RVV_VLSIu15__rvv_int32m2_tLj128EEE
277 // CHECK-128: _Z4m2f31SI9__RVV_VLSIu15__rvv_int32m2_tLj256EEE
278 // CHECK-256: _Z4m2f31SI9__RVV_VLSIu15__rvv_int32m2_tLj512EEE
279 // CHECK-512: _Z4m2f31SI9__RVV_VLSIu15__rvv_int32m2_tLj1024EEE
280 // CHECK-1024: _Z4m2f31SI9__RVV_VLSIu15__rvv_int32m2_tLj2048EEE
281 void m2f3(S<fixed_int32m2_t>) {}
282 
283 // CHECK-64: _Z4m2f41SI9__RVV_VLSIu15__rvv_int64m2_tLj128EEE
284 // CHECK-128: _Z4m2f41SI9__RVV_VLSIu15__rvv_int64m2_tLj256EEE
285 // CHECK-256: _Z4m2f41SI9__RVV_VLSIu15__rvv_int64m2_tLj512EEE
286 // CHECK-512: _Z4m2f41SI9__RVV_VLSIu15__rvv_int64m2_tLj1024EEE
287 // CHECK-1024: _Z4m2f41SI9__RVV_VLSIu15__rvv_int64m2_tLj2048EEE
288 void m2f4(S<fixed_int64m2_t>) {}
289 
290 // CHECK-64: _Z4m2f51SI9__RVV_VLSIu15__rvv_uint8m2_tLj128EEE
291 // CHECK-128: _Z4m2f51SI9__RVV_VLSIu15__rvv_uint8m2_tLj256EEE
292 // CHECK-256: _Z4m2f51SI9__RVV_VLSIu15__rvv_uint8m2_tLj512EEE
293 // CHECK-512: _Z4m2f51SI9__RVV_VLSIu15__rvv_uint8m2_tLj1024EEE
294 // CHECK-1024: _Z4m2f51SI9__RVV_VLSIu15__rvv_uint8m2_tLj2048EEE
295 void m2f5(S<fixed_uint8m2_t>) {}
296 
297 // CHECK-64: _Z4m2f61SI9__RVV_VLSIu16__rvv_uint16m2_tLj128EEE
298 // CHECK-128: _Z4m2f61SI9__RVV_VLSIu16__rvv_uint16m2_tLj256EEE
299 // CHECK-256: _Z4m2f61SI9__RVV_VLSIu16__rvv_uint16m2_tLj512EEE
300 // CHECK-512: _Z4m2f61SI9__RVV_VLSIu16__rvv_uint16m2_tLj1024EEE
301 // CHECK-1024: _Z4m2f61SI9__RVV_VLSIu16__rvv_uint16m2_tLj2048EEE
302 void m2f6(S<fixed_uint16m2_t>) {}
303 
304 // CHECK-64: _Z4m2f71SI9__RVV_VLSIu16__rvv_uint32m2_tLj128EEE
305 // CHECK-128: _Z4m2f71SI9__RVV_VLSIu16__rvv_uint32m2_tLj256EEE
306 // CHECK-256: _Z4m2f71SI9__RVV_VLSIu16__rvv_uint32m2_tLj512EEE
307 // CHECK-512: _Z4m2f71SI9__RVV_VLSIu16__rvv_uint32m2_tLj1024EEE
308 // CHECK-1024: _Z4m2f71SI9__RVV_VLSIu16__rvv_uint32m2_tLj2048EEE
309 void m2f7(S<fixed_uint32m2_t>) {}
310 
311 // CHECK-64: _Z4m2f81SI9__RVV_VLSIu16__rvv_uint64m2_tLj128EEE
312 // CHECK-128: _Z4m2f81SI9__RVV_VLSIu16__rvv_uint64m2_tLj256EEE
313 // CHECK-256: _Z4m2f81SI9__RVV_VLSIu16__rvv_uint64m2_tLj512EEE
314 // CHECK-512: _Z4m2f81SI9__RVV_VLSIu16__rvv_uint64m2_tLj1024EEE
315 // CHECK-1024: _Z4m2f81SI9__RVV_VLSIu16__rvv_uint64m2_tLj2048EEE
316 void m2f8(S<fixed_uint64m2_t>) {}
317 
318 // CHECK-64: _Z4m2f91SI9__RVV_VLSIu17__rvv_float32m2_tLj128EEE
319 // CHECK-128: _Z4m2f91SI9__RVV_VLSIu17__rvv_float32m2_tLj256EEE
320 // CHECK-256: _Z4m2f91SI9__RVV_VLSIu17__rvv_float32m2_tLj512EEE
321 // CHECK-512: _Z4m2f91SI9__RVV_VLSIu17__rvv_float32m2_tLj1024EEE
322 // CHECK-1024: _Z4m2f91SI9__RVV_VLSIu17__rvv_float32m2_tLj2048EEE
323 void m2f9(S<fixed_float32m2_t>) {}
324 
325 // CHECK-64: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj128EEE
326 // CHECK-128: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj256EEE
327 // CHECK-256: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj512EEE
328 // CHECK-512: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj1024EEE
329 // CHECK-1024: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj2048EEE
330 void m2f10(S<fixed_float64m2_t>) {}
331 
332 // CHECK-64: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj128EEE
333 // CHECK-128: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj256EEE
334 // CHECK-256: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj512EEE
335 // CHECK-512: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj1024EEE
336 // CHECK-1024: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj2048EEE
337 void m2f11(S<fixed_float16m2_t>) {}
338 
339 // CHECK-64: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj256EEE
340 // CHECK-128: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj512EEE
341 // CHECK-256: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj1024EEE
342 // CHECK-512: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj2048EEE
343 // CHECK-1024: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj4096EEE
344 void m4f1(S<fixed_int8m4_t>) {}
345 
346 // CHECK-64: _Z4m4f21SI9__RVV_VLSIu15__rvv_int16m4_tLj256EEE
347 // CHECK-128: _Z4m4f21SI9__RVV_VLSIu15__rvv_int16m4_tLj512EEE
348 // CHECK-256: _Z4m4f21SI9__RVV_VLSIu15__rvv_int16m4_tLj1024EEE
349 // CHECK-512: _Z4m4f21SI9__RVV_VLSIu15__rvv_int16m4_tLj2048EEE
350 // CHECK-1024: _Z4m4f21SI9__RVV_VLSIu15__rvv_int16m4_tLj4096EEE
351 void m4f2(S<fixed_int16m4_t>) {}
352 
353 // CHECK-64: _Z4m4f31SI9__RVV_VLSIu15__rvv_int32m4_tLj256EEE
354 // CHECK-128: _Z4m4f31SI9__RVV_VLSIu15__rvv_int32m4_tLj512EEE
355 // CHECK-256: _Z4m4f31SI9__RVV_VLSIu15__rvv_int32m4_tLj1024EEE
356 // CHECK-512: _Z4m4f31SI9__RVV_VLSIu15__rvv_int32m4_tLj2048EEE
357 // CHECK-1024: _Z4m4f31SI9__RVV_VLSIu15__rvv_int32m4_tLj4096EEE
358 void m4f3(S<fixed_int32m4_t>) {}
359 
360 // CHECK-64: _Z4m4f41SI9__RVV_VLSIu15__rvv_int64m4_tLj256EEE
361 // CHECK-128: _Z4m4f41SI9__RVV_VLSIu15__rvv_int64m4_tLj512EEE
362 // CHECK-256: _Z4m4f41SI9__RVV_VLSIu15__rvv_int64m4_tLj1024EEE
363 // CHECK-512: _Z4m4f41SI9__RVV_VLSIu15__rvv_int64m4_tLj2048EEE
364 // CHECK-1024: _Z4m4f41SI9__RVV_VLSIu15__rvv_int64m4_tLj4096EEE
365 void m4f4(S<fixed_int64m4_t>) {}
366 
367 // CHECK-64: _Z4m4f51SI9__RVV_VLSIu15__rvv_uint8m4_tLj256EEE
368 // CHECK-128: _Z4m4f51SI9__RVV_VLSIu15__rvv_uint8m4_tLj512EEE
369 // CHECK-256: _Z4m4f51SI9__RVV_VLSIu15__rvv_uint8m4_tLj1024EEE
370 // CHECK-512: _Z4m4f51SI9__RVV_VLSIu15__rvv_uint8m4_tLj2048EEE
371 // CHECK-1024: _Z4m4f51SI9__RVV_VLSIu15__rvv_uint8m4_tLj4096EEE
372 void m4f5(S<fixed_uint8m4_t>) {}
373 
374 // CHECK-64: _Z4m4f61SI9__RVV_VLSIu16__rvv_uint16m4_tLj256EEE
375 // CHECK-128: _Z4m4f61SI9__RVV_VLSIu16__rvv_uint16m4_tLj512EEE
376 // CHECK-256: _Z4m4f61SI9__RVV_VLSIu16__rvv_uint16m4_tLj1024EEE
377 // CHECK-512: _Z4m4f61SI9__RVV_VLSIu16__rvv_uint16m4_tLj2048EEE
378 // CHECK-1024: _Z4m4f61SI9__RVV_VLSIu16__rvv_uint16m4_tLj4096EEE
379 void m4f6(S<fixed_uint16m4_t>) {}
380 
381 // CHECK-64: _Z4m4f71SI9__RVV_VLSIu16__rvv_uint32m4_tLj256EEE
382 // CHECK-128: _Z4m4f71SI9__RVV_VLSIu16__rvv_uint32m4_tLj512EEE
383 // CHECK-256: _Z4m4f71SI9__RVV_VLSIu16__rvv_uint32m4_tLj1024EEE
384 // CHECK-512: _Z4m4f71SI9__RVV_VLSIu16__rvv_uint32m4_tLj2048EEE
385 // CHECK-1024: _Z4m4f71SI9__RVV_VLSIu16__rvv_uint32m4_tLj4096EEE
386 void m4f7(S<fixed_uint32m4_t>) {}
387 
388 // CHECK-64: _Z4m4f81SI9__RVV_VLSIu16__rvv_uint64m4_tLj256EEE
389 // CHECK-128: _Z4m4f81SI9__RVV_VLSIu16__rvv_uint64m4_tLj512EEE
390 // CHECK-256: _Z4m4f81SI9__RVV_VLSIu16__rvv_uint64m4_tLj1024EEE
391 // CHECK-512: _Z4m4f81SI9__RVV_VLSIu16__rvv_uint64m4_tLj2048EEE
392 // CHECK-1024: _Z4m4f81SI9__RVV_VLSIu16__rvv_uint64m4_tLj4096EEE
393 void m4f8(S<fixed_uint64m4_t>) {}
394 
395 // CHECK-64: _Z4m4f91SI9__RVV_VLSIu17__rvv_float32m4_tLj256EEE
396 // CHECK-128: _Z4m4f91SI9__RVV_VLSIu17__rvv_float32m4_tLj512EEE
397 // CHECK-256: _Z4m4f91SI9__RVV_VLSIu17__rvv_float32m4_tLj1024EEE
398 // CHECK-512: _Z4m4f91SI9__RVV_VLSIu17__rvv_float32m4_tLj2048EEE
399 // CHECK-1024: _Z4m4f91SI9__RVV_VLSIu17__rvv_float32m4_tLj4096EEE
400 void m4f9(S<fixed_float32m4_t>) {}
401 
402 // CHECK-64: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj256EEE
403 // CHECK-128: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj512EEE
404 // CHECK-256: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj1024EEE
405 // CHECK-512: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj2048EEE
406 // CHECK-1024: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj4096EEE
407 void m4f10(S<fixed_float64m4_t>) {}
408 
409 // CHECK-64: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj256EEE
410 // CHECK-128: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj512EEE
411 // CHECK-256: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj1024EEE
412 // CHECK-512: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj2048EEE
413 // CHECK-1024: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj4096EEE
414 void m4f11(S<fixed_float16m4_t>) {}
415 
416 // CHECK-64: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj512EEE
417 // CHECK-128: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj1024EEE
418 // CHECK-256: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj2048EEE
419 // CHECK-512: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj4096EEE
420 // CHECK-1024: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj8192EEE
421 void m8f1(S<fixed_int8m8_t>) {}
422 
423 // CHECK-64: _Z4m8f21SI9__RVV_VLSIu15__rvv_int16m8_tLj512EEE
424 // CHECK-128: _Z4m8f21SI9__RVV_VLSIu15__rvv_int16m8_tLj1024EEE
425 // CHECK-256: _Z4m8f21SI9__RVV_VLSIu15__rvv_int16m8_tLj2048EEE
426 // CHECK-512: _Z4m8f21SI9__RVV_VLSIu15__rvv_int16m8_tLj4096EEE
427 // CHECK-1024: _Z4m8f21SI9__RVV_VLSIu15__rvv_int16m8_tLj8192EEE
428 void m8f2(S<fixed_int16m8_t>) {}
429 
430 // CHECK-64: _Z4m8f31SI9__RVV_VLSIu15__rvv_int32m8_tLj512EEE
431 // CHECK-128: _Z4m8f31SI9__RVV_VLSIu15__rvv_int32m8_tLj1024EEE
432 // CHECK-256: _Z4m8f31SI9__RVV_VLSIu15__rvv_int32m8_tLj2048EEE
433 // CHECK-512: _Z4m8f31SI9__RVV_VLSIu15__rvv_int32m8_tLj4096EEE
434 // CHECK-1024: _Z4m8f31SI9__RVV_VLSIu15__rvv_int32m8_tLj8192EEE
435 void m8f3(S<fixed_int32m8_t>) {}
436 
437 // CHECK-64: _Z4m8f41SI9__RVV_VLSIu15__rvv_int64m8_tLj512EEE
438 // CHECK-128: _Z4m8f41SI9__RVV_VLSIu15__rvv_int64m8_tLj1024EEE
439 // CHECK-256: _Z4m8f41SI9__RVV_VLSIu15__rvv_int64m8_tLj2048EEE
440 // CHECK-512: _Z4m8f41SI9__RVV_VLSIu15__rvv_int64m8_tLj4096EEE
441 // CHECK-1024: _Z4m8f41SI9__RVV_VLSIu15__rvv_int64m8_tLj8192EEE
442 void m8f4(S<fixed_int64m8_t>) {}
443 
444 // CHECK-64: _Z4m8f51SI9__RVV_VLSIu15__rvv_uint8m8_tLj512EEE
445 // CHECK-128: _Z4m8f51SI9__RVV_VLSIu15__rvv_uint8m8_tLj1024EEE
446 // CHECK-256: _Z4m8f51SI9__RVV_VLSIu15__rvv_uint8m8_tLj2048EEE
447 // CHECK-512: _Z4m8f51SI9__RVV_VLSIu15__rvv_uint8m8_tLj4096EEE
448 // CHECK-1024: _Z4m8f51SI9__RVV_VLSIu15__rvv_uint8m8_tLj8192EEE
449 void m8f5(S<fixed_uint8m8_t>) {}
450 
451 // CHECK-64: _Z4m8f61SI9__RVV_VLSIu16__rvv_uint16m8_tLj512EEE
452 // CHECK-128: _Z4m8f61SI9__RVV_VLSIu16__rvv_uint16m8_tLj1024EEE
453 // CHECK-256: _Z4m8f61SI9__RVV_VLSIu16__rvv_uint16m8_tLj2048EEE
454 // CHECK-512: _Z4m8f61SI9__RVV_VLSIu16__rvv_uint16m8_tLj4096EEE
455 // CHECK-1024: _Z4m8f61SI9__RVV_VLSIu16__rvv_uint16m8_tLj8192EEE
456 void m8f6(S<fixed_uint16m8_t>) {}
457 
458 // CHECK-64: _Z4m8f71SI9__RVV_VLSIu16__rvv_uint32m8_tLj512EEE
459 // CHECK-128: _Z4m8f71SI9__RVV_VLSIu16__rvv_uint32m8_tLj1024EEE
460 // CHECK-256: _Z4m8f71SI9__RVV_VLSIu16__rvv_uint32m8_tLj2048EEE
461 // CHECK-512: _Z4m8f71SI9__RVV_VLSIu16__rvv_uint32m8_tLj4096EEE
462 // CHECK-1024: _Z4m8f71SI9__RVV_VLSIu16__rvv_uint32m8_tLj8192EEE
463 void m8f7(S<fixed_uint32m8_t>) {}
464 
465 // CHECK-64: _Z4m8f81SI9__RVV_VLSIu16__rvv_uint64m8_tLj512EEE
466 // CHECK-128: _Z4m8f81SI9__RVV_VLSIu16__rvv_uint64m8_tLj1024EEE
467 // CHECK-256: _Z4m8f81SI9__RVV_VLSIu16__rvv_uint64m8_tLj2048EEE
468 // CHECK-512: _Z4m8f81SI9__RVV_VLSIu16__rvv_uint64m8_tLj4096EEE
469 // CHECK-1024: _Z4m8f81SI9__RVV_VLSIu16__rvv_uint64m8_tLj8192EEE
470 void m8f8(S<fixed_uint64m8_t>) {}
471 
472 // CHECK-64: _Z4m8f91SI9__RVV_VLSIu17__rvv_float32m8_tLj512EEE
473 // CHECK-128: _Z4m8f91SI9__RVV_VLSIu17__rvv_float32m8_tLj1024EEE
474 // CHECK-256: _Z4m8f91SI9__RVV_VLSIu17__rvv_float32m8_tLj2048EEE
475 // CHECK-512: _Z4m8f91SI9__RVV_VLSIu17__rvv_float32m8_tLj4096EEE
476 // CHECK-1024: _Z4m8f91SI9__RVV_VLSIu17__rvv_float32m8_tLj8192EEE
477 void m8f9(S<fixed_float32m8_t>) {}
478 
479 // CHECK-64: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj512EEE
480 // CHECK-128: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj1024EEE
481 // CHECK-256: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj2048EEE
482 // CHECK-512: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj4096EEE
483 // CHECK-1024: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj8192EEE
484 void m8f10(S<fixed_float64m8_t>) {}
485 
486 // CHECK-64: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj512EEE
487 // CHECK-128: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj1024EEE
488 // CHECK-256: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj2048EEE
489 // CHECK-512: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj4096EEE
490 // CHECK-1024: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj8192EEE
491 void m8f11(S<fixed_float16m8_t>) {}
492 
493 // CHECK-64: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj32EEE
494 // CHECK-128: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj64EEE
495 // CHECK-256: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj128EEE
496 // CHECK-512: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj256EEE
497 // CHECK-1024: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj512EEE
498 void mf2f1(S<fixed_int8mf2_t>) {}
499 
500 // CHECK-64: _Z5mf2f21SI9__RVV_VLSIu16__rvv_int16mf2_tLj32EEE
501 // CHECK-128: _Z5mf2f21SI9__RVV_VLSIu16__rvv_int16mf2_tLj64EEE
502 // CHECK-256: _Z5mf2f21SI9__RVV_VLSIu16__rvv_int16mf2_tLj128EEE
503 // CHECK-512: _Z5mf2f21SI9__RVV_VLSIu16__rvv_int16mf2_tLj256EEE
504 // CHECK-1024: _Z5mf2f21SI9__RVV_VLSIu16__rvv_int16mf2_tLj512EEE
505 void mf2f2(S<fixed_int16mf2_t>) {}
506 
507 // CHECK-64: _Z5mf2f31SI9__RVV_VLSIu16__rvv_int32mf2_tLj32EEE
508 // CHECK-128: _Z5mf2f31SI9__RVV_VLSIu16__rvv_int32mf2_tLj64EEE
509 // CHECK-256: _Z5mf2f31SI9__RVV_VLSIu16__rvv_int32mf2_tLj128EEE
510 // CHECK-512: _Z5mf2f31SI9__RVV_VLSIu16__rvv_int32mf2_tLj256EEE
511 // CHECK-1024: _Z5mf2f31SI9__RVV_VLSIu16__rvv_int32mf2_tLj512EEE
512 void mf2f3(S<fixed_int32mf2_t>) {}
513 
514 // CHECK-64: _Z5mf2f51SI9__RVV_VLSIu16__rvv_uint8mf2_tLj32EEE
515 // CHECK-128: _Z5mf2f51SI9__RVV_VLSIu16__rvv_uint8mf2_tLj64EEE
516 // CHECK-256: _Z5mf2f51SI9__RVV_VLSIu16__rvv_uint8mf2_tLj128EEE
517 // CHECK-512: _Z5mf2f51SI9__RVV_VLSIu16__rvv_uint8mf2_tLj256EEE
518 // CHECK-1024: _Z5mf2f51SI9__RVV_VLSIu16__rvv_uint8mf2_tLj512EEE
519 void mf2f5(S<fixed_uint8mf2_t>) {}
520 
521 // CHECK-64: _Z5mf2f61SI9__RVV_VLSIu17__rvv_uint16mf2_tLj32EEE
522 // CHECK-128: _Z5mf2f61SI9__RVV_VLSIu17__rvv_uint16mf2_tLj64EEE
523 // CHECK-256: _Z5mf2f61SI9__RVV_VLSIu17__rvv_uint16mf2_tLj128EEE
524 // CHECK-512: _Z5mf2f61SI9__RVV_VLSIu17__rvv_uint16mf2_tLj256EEE
525 // CHECK-1024: _Z5mf2f61SI9__RVV_VLSIu17__rvv_uint16mf2_tLj512EEE
526 void mf2f6(S<fixed_uint16mf2_t>) {}
527 
528 // CHECK-64: _Z5mf2f71SI9__RVV_VLSIu17__rvv_uint32mf2_tLj32EEE
529 // CHECK-128: _Z5mf2f71SI9__RVV_VLSIu17__rvv_uint32mf2_tLj64EEE
530 // CHECK-256: _Z5mf2f71SI9__RVV_VLSIu17__rvv_uint32mf2_tLj128EEE
531 // CHECK-512: _Z5mf2f71SI9__RVV_VLSIu17__rvv_uint32mf2_tLj256EEE
532 // CHECK-1024: _Z5mf2f71SI9__RVV_VLSIu17__rvv_uint32mf2_tLj512EEE
533 void mf2f7(S<fixed_uint32mf2_t>) {}
534 
535 // CHECK-64: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj32EEE
536 // CHECK-128: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj64EEE
537 // CHECK-256: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj128EEE
538 // CHECK-512: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj256EEE
539 // CHECK-1024: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj512EEE
540 void mf2f9(S<fixed_float32mf2_t>) {}
541 
542 // CHECK-64: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj32EEE
543 // CHECK-128: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj64EEE
544 // CHECK-256: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj128EEE
545 // CHECK-512: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj256EEE
546 // CHECK-1024: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj512EEE
547 void mf2f10(S<fixed_float16mf2_t>) {}
548 
549 // CHECK-64: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj16EEE
550 // CHECK-128: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj32EEE
551 // CHECK-256: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj64EEE
552 // CHECK-512: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj128EEE
553 // CHECK-1024: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj256EEE
554 void mf4f1(S<fixed_int8mf4_t>) {}
555 
556 // CHECK-64: _Z5mf4f21SI9__RVV_VLSIu16__rvv_int16mf4_tLj16EEE
557 // CHECK-128: _Z5mf4f21SI9__RVV_VLSIu16__rvv_int16mf4_tLj32EEE
558 // CHECK-256: _Z5mf4f21SI9__RVV_VLSIu16__rvv_int16mf4_tLj64EEE
559 // CHECK-512: _Z5mf4f21SI9__RVV_VLSIu16__rvv_int16mf4_tLj128EEE
560 // CHECK-1024: _Z5mf4f21SI9__RVV_VLSIu16__rvv_int16mf4_tLj256EEE
561 void mf4f2(S<fixed_int16mf4_t>) {}
562 
563 // CHECK-64: _Z5mf4f51SI9__RVV_VLSIu16__rvv_uint8mf4_tLj16EEE
564 // CHECK-128: _Z5mf4f51SI9__RVV_VLSIu16__rvv_uint8mf4_tLj32EEE
565 // CHECK-256: _Z5mf4f51SI9__RVV_VLSIu16__rvv_uint8mf4_tLj64EEE
566 // CHECK-512: _Z5mf4f51SI9__RVV_VLSIu16__rvv_uint8mf4_tLj128EEE
567 // CHECK-1024: _Z5mf4f51SI9__RVV_VLSIu16__rvv_uint8mf4_tLj256EEE
568 void mf4f5(S<fixed_uint8mf4_t>) {}
569 
570 // CHECK-64: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj16EEE
571 // CHECK-128: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj32EEE
572 // CHECK-256: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj64EEE
573 // CHECK-512: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj128EEE
574 // CHECK-1024: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj256EEE
575 void mf4f6(S<fixed_uint16mf4_t>) {}
576 
577 // CHECK-64: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj16EEE
578 // CHECK-128: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj32EEE
579 // CHECK-256: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj64EEE
580 // CHECK-512: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj128EEE
581 // CHECK-1024: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj256EEE
582 void mf4f7(S<fixed_float16mf4_t>) {}
583 
584 // CHECK-64: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj8EEE
585 // CHECK-128: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj16EEE
586 // CHECK-256: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj32EEE
587 // CHECK-512: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj64EEE
588 // CHECK-1024: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj128EEE
589 void mf8f1(S<fixed_int8mf8_t>) {}
590 
591 // CHECK-64: _Z5mf8f51SI9__RVV_VLSIu16__rvv_uint8mf8_tLj8EEE
592 // CHECK-128: _Z5mf8f51SI9__RVV_VLSIu16__rvv_uint8mf8_tLj16EEE
593 // CHECK-256: _Z5mf8f51SI9__RVV_VLSIu16__rvv_uint8mf8_tLj32EEE
594 // CHECK-512: _Z5mf8f51SI9__RVV_VLSIu16__rvv_uint8mf8_tLj64EEE
595 // CHECK-1024: _Z5mf8f51SI9__RVV_VLSIu16__rvv_uint8mf8_tLj128EEE
596 void mf8f5(S<fixed_uint8mf8_t>) {}
597 
598 // CHECK-64: _Z5bool11SI9__RVV_VLSIu13__rvv_bool1_tLj64EEE
599 // CHECK-128: _Z5bool11SI9__RVV_VLSIu13__rvv_bool1_tLj128EEE
600 // CHECK-256: _Z5bool11SI9__RVV_VLSIu13__rvv_bool1_tLj256EEE
601 // CHECK-512: _Z5bool11SI9__RVV_VLSIu13__rvv_bool1_tLj512EEE
602 // CHECK-1024: _Z5bool11SI9__RVV_VLSIu13__rvv_bool1_tLj1024EEE
603 void bool1(S<fixed_bool1_t>) {}
604 
605 // CHECK-64: _Z5bool21SI9__RVV_VLSIu13__rvv_bool2_tLj32EEE
606 // CHECK-128: _Z5bool21SI9__RVV_VLSIu13__rvv_bool2_tLj64EEE
607 // CHECK-256: _Z5bool21SI9__RVV_VLSIu13__rvv_bool2_tLj128EEE
608 // CHECK-512: _Z5bool21SI9__RVV_VLSIu13__rvv_bool2_tLj256EEE
609 // CHECK-1024: _Z5bool21SI9__RVV_VLSIu13__rvv_bool2_tLj512EEE
610 void bool2(S<fixed_bool2_t>) {}
611 
612 // CHECK-64: _Z5bool41SI9__RVV_VLSIu13__rvv_bool4_tLj16EEE
613 // CHECK-128: _Z5bool41SI9__RVV_VLSIu13__rvv_bool4_tLj32EEE
614 // CHECK-256: _Z5bool41SI9__RVV_VLSIu13__rvv_bool4_tLj64EEE
615 // CHECK-512: _Z5bool41SI9__RVV_VLSIu13__rvv_bool4_tLj128EEE
616 // CHECK-1024: _Z5bool41SI9__RVV_VLSIu13__rvv_bool4_tLj256EEE
617 void bool4(S<fixed_bool4_t>) {}
618 
619 // CHECK-64: _Z5bool81SI9__RVV_VLSIu13__rvv_bool8_tLj8EEE
620 // CHECK-128: _Z5bool81SI9__RVV_VLSIu13__rvv_bool8_tLj16EEE
621 // CHECK-256: _Z5bool81SI9__RVV_VLSIu13__rvv_bool8_tLj32EEE
622 // CHECK-512: _Z5bool81SI9__RVV_VLSIu13__rvv_bool8_tLj64EEE
623 // CHECK-1024: _Z5bool81SI9__RVV_VLSIu13__rvv_bool8_tLj128EEE
624 void bool8(S<fixed_bool8_t>) {}
625 
626 // CHECK-64: _Z6bool161SI9__RVV_VLSIu14__rvv_bool16_tLj4EEE
627 // CHECK-128: _Z6bool161SI9__RVV_VLSIu14__rvv_bool16_tLj8EEE
628 // CHECK-256: _Z6bool161SI9__RVV_VLSIu14__rvv_bool16_tLj16EEE
629 // CHECK-512: _Z6bool161SI9__RVV_VLSIu14__rvv_bool16_tLj32EEE
630 // CHECK-1024: _Z6bool161SI9__RVV_VLSIu14__rvv_bool16_tLj64EEE
631 //
632 void bool16(S<fixed_bool16_t>) {}
633 
634 // CHECK-64: _Z6bool321SI9__RVV_VLSIu14__rvv_bool32_tLj2EEE
635 // CHECK-128: _Z6bool321SI9__RVV_VLSIu14__rvv_bool32_tLj4EEE
636 // CHECK-256: _Z6bool321SI9__RVV_VLSIu14__rvv_bool32_tLj8EEE
637 // CHECK-512: _Z6bool321SI9__RVV_VLSIu14__rvv_bool32_tLj16EEE
638 // CHECK-1024: _Z6bool321SI9__RVV_VLSIu14__rvv_bool32_tLj32EEE
639 void bool32(S<fixed_bool32_t>) {}
640 
641 // CHECK-64: _Z6bool641SI9__RVV_VLSIu14__rvv_bool64_tLj1EEE
642 // CHECK-128: _Z6bool641SI9__RVV_VLSIu14__rvv_bool64_tLj2EEE
643 // CHECK-256: _Z6bool641SI9__RVV_VLSIu14__rvv_bool64_tLj4EEE
644 // CHECK-512: _Z6bool641SI9__RVV_VLSIu14__rvv_bool64_tLj8EEE
645 // CHECK-1024: _Z6bool641SI9__RVV_VLSIu14__rvv_bool64_tLj16EEE
646 void bool64(S<fixed_bool64_t>) {}
647