1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4 2 // RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s 3 4 __attribute__((target_version("arch=+v"))) int foo1(void) { return 1; } 5 __attribute__((target_version("default"))) int foo1(void) { return 1; } 6 7 __attribute__((target_version("arch=+zbb"))) int foo2(void) { return 1; } 8 __attribute__((target_version("arch=+m"))) int foo2(void) { return 1; } 9 __attribute__((target_version("default"))) int foo2(void) { return 1; } 10 11 __attribute__((target_version("arch=+zbb,+c"))) int foo3(void) { return 1; } 12 __attribute__((target_version("arch=+m"))) int foo3(void) { return 1; } 13 __attribute__((target_version("default"))) int foo3(void) { return 1; } 14 15 __attribute__((target_version("arch=+zba"))) int foo4(void) { return 1; } 16 __attribute__((target_version("arch=+zbb"))) int foo4(void) { return 1; } 17 __attribute__((target_version("arch=+zbb,+zba"))) int foo4(void) { return 1; } 18 __attribute__((target_version("default"))) int foo4(void) { return 1; } 19 20 __attribute__((target_version("arch=+zba"))) int foo5(void) { return 1; } 21 __attribute__((target_version("arch=+zbb,+zba"))) int foo5(void) { return 1; } 22 __attribute__((target_version("arch=+zbb"))) int foo5(void) { return 1; } 23 __attribute__((target_version("default"))) int foo5(void) { return 1; } 24 25 __attribute__((target_version("arch=+zba"))) int foo6(void) { return 1; } 26 __attribute__((target_version("arch=+zbb"))) int foo6(void) { return 1; } 27 __attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo6(void) { return 1; } 28 __attribute__((target_version("default"))) int foo6(void) { return 1; } 29 30 __attribute__((target_version("priority=8;arch=+zba"))) int foo7(void) { return 1; } 31 __attribute__((target_version("arch=+zbb;priority=9"))) int foo7(void) { return 1; } 32 __attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo7(void) { return 1; } 33 __attribute__((target_version("default"))) int foo7(void) { return 1; } 34 35 int bar() { return foo1() + foo2() + foo3(); } 36 //. 37 // CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] } 38 // CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver 39 // CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver 40 // CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver 41 // CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver 42 // CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver 43 // CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver 44 // CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver 45 //. 46 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._v( 47 // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 48 // CHECK-NEXT: entry: 49 // CHECK-NEXT: ret i32 1 50 // 51 // 52 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default( 53 // CHECK-SAME: ) #[[ATTR1:[0-9]+]] { 54 // CHECK-NEXT: entry: 55 // CHECK-NEXT: ret i32 1 56 // 57 // 58 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb( 59 // CHECK-SAME: ) #[[ATTR2:[0-9]+]] { 60 // CHECK-NEXT: entry: 61 // CHECK-NEXT: ret i32 1 62 // 63 // 64 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m( 65 // CHECK-SAME: ) #[[ATTR1]] { 66 // CHECK-NEXT: entry: 67 // CHECK-NEXT: ret i32 1 68 // 69 // 70 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default( 71 // CHECK-SAME: ) #[[ATTR1]] { 72 // CHECK-NEXT: entry: 73 // CHECK-NEXT: ret i32 1 74 // 75 // 76 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb( 77 // CHECK-SAME: ) #[[ATTR3:[0-9]+]] { 78 // CHECK-NEXT: entry: 79 // CHECK-NEXT: ret i32 1 80 // 81 // 82 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._m( 83 // CHECK-SAME: ) #[[ATTR1]] { 84 // CHECK-NEXT: entry: 85 // CHECK-NEXT: ret i32 1 86 // 87 // 88 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default( 89 // CHECK-SAME: ) #[[ATTR1]] { 90 // CHECK-NEXT: entry: 91 // CHECK-NEXT: ret i32 1 92 // 93 // 94 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba( 95 // CHECK-SAME: ) #[[ATTR4:[0-9]+]] { 96 // CHECK-NEXT: entry: 97 // CHECK-NEXT: ret i32 1 98 // 99 // 100 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zbb( 101 // CHECK-SAME: ) #[[ATTR2]] { 102 // CHECK-NEXT: entry: 103 // CHECK-NEXT: ret i32 1 104 // 105 // 106 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba_zbb( 107 // CHECK-SAME: ) #[[ATTR5:[0-9]+]] { 108 // CHECK-NEXT: entry: 109 // CHECK-NEXT: ret i32 1 110 // 111 // 112 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default( 113 // CHECK-SAME: ) #[[ATTR1]] { 114 // CHECK-NEXT: entry: 115 // CHECK-NEXT: ret i32 1 116 // 117 // 118 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba( 119 // CHECK-SAME: ) #[[ATTR4]] { 120 // CHECK-NEXT: entry: 121 // CHECK-NEXT: ret i32 1 122 // 123 // 124 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba_zbb( 125 // CHECK-SAME: ) #[[ATTR5]] { 126 // CHECK-NEXT: entry: 127 // CHECK-NEXT: ret i32 1 128 // 129 // 130 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zbb( 131 // CHECK-SAME: ) #[[ATTR2]] { 132 // CHECK-NEXT: entry: 133 // CHECK-NEXT: ret i32 1 134 // 135 // 136 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default( 137 // CHECK-SAME: ) #[[ATTR1]] { 138 // CHECK-NEXT: entry: 139 // CHECK-NEXT: ret i32 1 140 // 141 // 142 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba( 143 // CHECK-SAME: ) #[[ATTR4]] { 144 // CHECK-NEXT: entry: 145 // CHECK-NEXT: ret i32 1 146 // 147 // 148 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zbb( 149 // CHECK-SAME: ) #[[ATTR2]] { 150 // CHECK-NEXT: entry: 151 // CHECK-NEXT: ret i32 1 152 // 153 // 154 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba_zbb( 155 // CHECK-SAME: ) #[[ATTR5]] { 156 // CHECK-NEXT: entry: 157 // CHECK-NEXT: ret i32 1 158 // 159 // 160 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default( 161 // CHECK-SAME: ) #[[ATTR1]] { 162 // CHECK-NEXT: entry: 163 // CHECK-NEXT: ret i32 1 164 // 165 // 166 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba( 167 // CHECK-SAME: ) #[[ATTR4]] { 168 // CHECK-NEXT: entry: 169 // CHECK-NEXT: ret i32 1 170 // 171 // 172 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb( 173 // CHECK-SAME: ) #[[ATTR2]] { 174 // CHECK-NEXT: entry: 175 // CHECK-NEXT: ret i32 1 176 // 177 // 178 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb( 179 // CHECK-SAME: ) #[[ATTR5]] { 180 // CHECK-NEXT: entry: 181 // CHECK-NEXT: ret i32 1 182 // 183 // 184 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default( 185 // CHECK-SAME: ) #[[ATTR1]] { 186 // CHECK-NEXT: entry: 187 // CHECK-NEXT: ret i32 1 188 // 189 // 190 // CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv( 191 // CHECK-SAME: ) #[[ATTR1]] { 192 // CHECK-NEXT: entry: 193 // CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v() 194 // CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v() 195 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 196 // CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v() 197 // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 198 // CHECK-NEXT: ret i32 [[ADD3]] 199 // 200 // 201 // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat { 202 // CHECK-NEXT: resolver_entry: 203 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 204 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 205 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2097152 206 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2097152 207 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 208 // CHECK: resolver_return: 209 // CHECK-NEXT: ret ptr @_Z4foo1v._v 210 // CHECK: resolver_else: 211 // CHECK-NEXT: ret ptr @_Z4foo1v.default 212 // 213 // 214 // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat { 215 // CHECK-NEXT: resolver_entry: 216 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 217 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 218 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456 219 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456 220 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 221 // CHECK: resolver_return: 222 // CHECK-NEXT: ret ptr @_Z4foo2v._zbb 223 // CHECK: resolver_else: 224 // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 225 // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096 226 // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096 227 // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 228 // CHECK: resolver_return1: 229 // CHECK-NEXT: ret ptr @_Z4foo2v._m 230 // CHECK: resolver_else2: 231 // CHECK-NEXT: ret ptr @_Z4foo2v.default 232 // 233 // 234 // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat { 235 // CHECK-NEXT: resolver_entry: 236 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 237 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 238 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460 239 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460 240 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 241 // CHECK: resolver_return: 242 // CHECK-NEXT: ret ptr @_Z4foo3v._c_zbb 243 // CHECK: resolver_else: 244 // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 245 // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096 246 // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096 247 // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 248 // CHECK: resolver_return1: 249 // CHECK-NEXT: ret ptr @_Z4foo3v._m 250 // CHECK: resolver_else2: 251 // CHECK-NEXT: ret ptr @_Z4foo3v.default 252 // 253 // 254 // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat { 255 // CHECK-NEXT: resolver_entry: 256 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 257 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 258 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728 259 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728 260 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 261 // CHECK: resolver_return: 262 // CHECK-NEXT: ret ptr @_Z4foo4v._zba 263 // CHECK: resolver_else: 264 // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 265 // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456 266 // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456 267 // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 268 // CHECK: resolver_return1: 269 // CHECK-NEXT: ret ptr @_Z4foo4v._zbb 270 // CHECK: resolver_else2: 271 // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 272 // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184 273 // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184 274 // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 275 // CHECK: resolver_return3: 276 // CHECK-NEXT: ret ptr @_Z4foo4v._zba_zbb 277 // CHECK: resolver_else4: 278 // CHECK-NEXT: ret ptr @_Z4foo4v.default 279 // 280 // 281 // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat { 282 // CHECK-NEXT: resolver_entry: 283 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 284 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 285 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728 286 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728 287 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 288 // CHECK: resolver_return: 289 // CHECK-NEXT: ret ptr @_Z4foo5v._zba 290 // CHECK: resolver_else: 291 // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 292 // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 402653184 293 // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 402653184 294 // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 295 // CHECK: resolver_return1: 296 // CHECK-NEXT: ret ptr @_Z4foo5v._zba_zbb 297 // CHECK: resolver_else2: 298 // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 299 // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456 300 // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456 301 // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 302 // CHECK: resolver_return3: 303 // CHECK-NEXT: ret ptr @_Z4foo5v._zbb 304 // CHECK: resolver_else4: 305 // CHECK-NEXT: ret ptr @_Z4foo5v.default 306 // 307 // 308 // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat { 309 // CHECK-NEXT: resolver_entry: 310 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 311 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 312 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184 313 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184 314 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 315 // CHECK: resolver_return: 316 // CHECK-NEXT: ret ptr @_Z4foo6v._zba_zbb 317 // CHECK: resolver_else: 318 // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 319 // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728 320 // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728 321 // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 322 // CHECK: resolver_return1: 323 // CHECK-NEXT: ret ptr @_Z4foo6v._zba 324 // CHECK: resolver_else2: 325 // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 326 // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456 327 // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456 328 // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 329 // CHECK: resolver_return3: 330 // CHECK-NEXT: ret ptr @_Z4foo6v._zbb 331 // CHECK: resolver_else4: 332 // CHECK-NEXT: ret ptr @_Z4foo6v.default 333 // 334 // 335 // CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver() comdat { 336 // CHECK-NEXT: resolver_entry: 337 // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) 338 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 339 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184 340 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184 341 // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 342 // CHECK: resolver_return: 343 // CHECK-NEXT: ret ptr @_Z4foo7v._zba_zbb 344 // CHECK: resolver_else: 345 // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 346 // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456 347 // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456 348 // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 349 // CHECK: resolver_return1: 350 // CHECK-NEXT: ret ptr @_Z4foo7v._zbb 351 // CHECK: resolver_else2: 352 // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 353 // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728 354 // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728 355 // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 356 // CHECK: resolver_return3: 357 // CHECK-NEXT: ret ptr @_Z4foo7v._zba 358 // CHECK: resolver_else4: 359 // CHECK-NEXT: ret ptr @_Z4foo7v.default 360 // 361 //. 362 // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } 363 // CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" } 364 // CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" } 365 // CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" } 366 // CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zmmul" } 367 // CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zbb,+zmmul" } 368 //. 369 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 370 // CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"} 371 // CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]} 372 // CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"} 373 // CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0} 374 // CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 375 //. 376