1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" 2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s 3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV 4 5 int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; } 6 int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; } 7 int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; } 8 int __attribute__((target_version("dotprod+wfxt"))) fmv(void) { return 4; } 9 int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; } 10 int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; } 11 int __attribute__((target_version("crc+wfxt"))) fmv(void) { return 7; } 12 int __attribute__((target_version("bti"))) fmv(void) { return 8; } 13 int __attribute__((target_version("sme2"))) fmv(void) { return 9; } 14 int __attribute__((target_version("default"))) fmv(void) { return 0; } 15 int __attribute__((target_version("wfxt+simd"))) fmv_one(void) { return 1; } 16 int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; } 17 int __attribute__((target_version("default"))) fmv_one(void) { return 0; } 18 int __attribute__((target_version("fp"))) fmv_two(void) { return 1; } 19 int __attribute__((target_version("simd"))) fmv_two(void) { return 2; } 20 int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; } 21 int __attribute__((target_version("default"))) fmv_two(void) { return 0; } 22 int foo() { 23 return fmv()+fmv_one()+fmv_two(); 24 } 25 26 inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; } 27 inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; } 28 inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; } 29 inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; } 30 inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; } 31 inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; } 32 inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; } 33 inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; } 34 inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; } 35 inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; } 36 inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; } 37 inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; } 38 inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; } 39 inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; } 40 inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; } 41 inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; } 42 inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; } 43 44 __attribute__((target_version("wfxt"))) int fmv_e(void); 45 int fmv_e(void) { return 20; } 46 47 static __attribute__((target_version("sb"))) inline int fmv_d(void); 48 static __attribute__((target_version("default"))) inline int fmv_d(void); 49 50 int __attribute__((target_version("default"))) fmv_default(void) { return 111; } 51 int fmv_default(void); 52 53 void fmv_c(void); 54 void __attribute__((target_version("ssbs"))) fmv_c(void){}; 55 void __attribute__((target_version("default"))) fmv_c(void){}; 56 57 int goo() { 58 fmv_inline(); 59 fmv_e(); 60 fmv_d(); 61 fmv_c(); 62 return fmv_default(); 63 } 64 static inline int __attribute__((target_version("sb"))) fmv_d(void) { return 0; } 65 static inline int __attribute__((target_version(" default "))) fmv_d(void) { return 1; } 66 67 static void func(void) {} 68 inline __attribute__((target_version("default"))) void recb(void) { func(); } 69 inline __attribute__((target_version("default"))) void reca(void) { recb(); } 70 void recur(void) { reca(); } 71 72 int __attribute__((target_version("default"))) main(void) { 73 recur(); 74 return goo(); 75 } 76 77 typedef int (*Fptr)(); 78 void f(Fptr); 79 int hoo(void) { 80 f(fmv); 81 Fptr fp1 = &fmv; 82 Fptr fp2 = fmv; 83 return fp1() + fp2(); 84 } 85 86 // This should generate one target version but no resolver. 87 __attribute__((target_version("default"))) int unused_with_forward_default_decl(void); 88 __attribute__((target_version("mops"))) int unused_with_forward_default_decl(void) { return 0; } 89 90 // This should also generate one target version but no resolver. 91 extern int unused_with_implicit_extern_forward_default_decl(void); 92 __attribute__((target_version("dotprod"))) 93 int unused_with_implicit_extern_forward_default_decl(void) { return 0; } 94 95 // This should also generate one target version but no resolver. 96 __attribute__((target_version("aes"))) int unused_with_default_decl(void) { return 0; } 97 __attribute__((target_version("default"))) int unused_with_default_decl(void); 98 99 // This should generate two target versions and the resolver. 100 __attribute__((target_version("sve"))) int unused_with_default_def(void) { return 0; } 101 __attribute__((target_version("default"))) int unused_with_default_def(void) { return 1; } 102 103 // This should also generate two target versions and the resolver. 104 __attribute__((target_version("fp16"))) int unused_with_implicit_default_def(void) { return 0; } 105 int unused_with_implicit_default_def(void) { return 1; } 106 107 // This should also generate two target versions and the resolver. 108 int unused_with_implicit_forward_default_def(void) { return 0; } 109 __attribute__((target_version("lse"))) int unused_with_implicit_forward_default_def(void) { return 1; } 110 111 // This should generate a target version despite the default not being declared. 112 __attribute__((target_version("rdm"))) int unused_without_default(void) { return 0; } 113 114 // These shouldn't generate anything. 115 int unused_version_declarations(void); 116 __attribute__((target_version("jscvt"))) int unused_version_declarations(void); 117 __attribute__((target_version("rdma"))) int unused_version_declarations(void); 118 119 // These should generate the default (mangled) version and the resolver. 120 int default_def_with_version_decls(void) { return 0; } 121 __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void); 122 __attribute__((target_version("rdma"))) int default_def_with_version_decls(void); 123 124 // The following is guarded because in NOFMV we get errors for calling undeclared functions. 125 #ifdef __HAVE_FUNCTION_MULTI_VERSIONING 126 // This should generate a default declaration, two target versions but no resolver. 127 __attribute__((target_version("jscvt"))) int used_def_without_default_decl(void) { return 1; } 128 __attribute__((target_version("rdma"))) int used_def_without_default_decl(void) { return 2; } 129 130 // This should generate a default declaration but no resolver. 131 __attribute__((target_version("jscvt"))) int used_decl_without_default_decl(void); 132 __attribute__((target_version("rdma"))) int used_decl_without_default_decl(void); 133 134 int caller(void) { return used_def_without_default_decl() + used_decl_without_default_decl(); } 135 #endif 136 137 //. 138 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } 139 // CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver 140 // CHECK: @fmv_one = weak_odr ifunc i32 (), ptr @fmv_one.resolver 141 // CHECK: @fmv_two = weak_odr ifunc i32 (), ptr @fmv_two.resolver 142 // CHECK: @fmv_e = weak_odr ifunc i32 (), ptr @fmv_e.resolver 143 // CHECK: @fmv_d = internal ifunc i32 (), ptr @fmv_d.resolver 144 // CHECK: @fmv_default = weak_odr ifunc i32 (), ptr @fmv_default.resolver 145 // CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver 146 // CHECK: @fmv_inline = weak_odr ifunc i32 (), ptr @fmv_inline.resolver 147 // CHECK: @reca = weak_odr ifunc void (), ptr @reca.resolver 148 // CHECK: @unused_with_default_def = weak_odr ifunc i32 (), ptr @unused_with_default_def.resolver 149 // CHECK: @unused_with_implicit_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_default_def.resolver 150 // CHECK: @unused_with_implicit_forward_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_forward_default_def.resolver 151 // CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver 152 // CHECK: @recb = weak_odr ifunc void (), ptr @recb.resolver 153 //. 154 // CHECK: Function Attrs: noinline nounwind optnone 155 // CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng 156 // CHECK-SAME: () #[[ATTR0:[0-9]+]] { 157 // CHECK-NEXT: entry: 158 // CHECK-NEXT: ret i32 1 159 // 160 // 161 // CHECK: Function Attrs: noinline nounwind optnone 162 // CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2Msme-i16i64 163 // CHECK-SAME: () #[[ATTR1:[0-9]+]] { 164 // CHECK-NEXT: entry: 165 // CHECK-NEXT: ret i32 2 166 // 167 // 168 // CHECK: Function Attrs: noinline nounwind optnone 169 // CHECK-LABEL: define {{[^@]+}}@fmv._MlseMsha2 170 // CHECK-SAME: () #[[ATTR2:[0-9]+]] { 171 // CHECK-NEXT: entry: 172 // CHECK-NEXT: ret i32 3 173 // 174 // 175 // CHECK: Function Attrs: noinline nounwind optnone 176 // CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMwfxt 177 // CHECK-SAME: () #[[ATTR3:[0-9]+]] { 178 // CHECK-NEXT: entry: 179 // CHECK-NEXT: ret i32 4 180 // 181 // 182 // CHECK: Function Attrs: noinline nounwind optnone 183 // CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fmlMmemtag 184 // CHECK-SAME: () #[[ATTR4:[0-9]+]] { 185 // CHECK-NEXT: entry: 186 // CHECK-NEXT: ret i32 5 187 // 188 // 189 // CHECK: Function Attrs: noinline nounwind optnone 190 // CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp 191 // CHECK-SAME: () #[[ATTR5:[0-9]+]] { 192 // CHECK-NEXT: entry: 193 // CHECK-NEXT: ret i32 6 194 // 195 // 196 // CHECK: Function Attrs: noinline nounwind optnone 197 // CHECK-LABEL: define {{[^@]+}}@fmv._McrcMwfxt 198 // CHECK-SAME: () #[[ATTR6:[0-9]+]] { 199 // CHECK-NEXT: entry: 200 // CHECK-NEXT: ret i32 7 201 // 202 // 203 // CHECK: Function Attrs: noinline nounwind optnone 204 // CHECK-LABEL: define {{[^@]+}}@fmv._Mbti 205 // CHECK-SAME: () #[[ATTR7:[0-9]+]] { 206 // CHECK-NEXT: entry: 207 // CHECK-NEXT: ret i32 8 208 // 209 // 210 // CHECK: Function Attrs: noinline nounwind optnone 211 // CHECK-LABEL: define {{[^@]+}}@fmv._Msme2 212 // CHECK-SAME: () #[[ATTR8:[0-9]+]] { 213 // CHECK-NEXT: entry: 214 // CHECK-NEXT: ret i32 9 215 // 216 // 217 // CHECK: Function Attrs: noinline nounwind optnone 218 // CHECK-LABEL: define {{[^@]+}}@fmv.default 219 // CHECK-SAME: () #[[ATTR9:[0-9]+]] { 220 // CHECK-NEXT: entry: 221 // CHECK-NEXT: ret i32 0 222 // 223 // 224 // CHECK: Function Attrs: noinline nounwind optnone 225 // CHECK-LABEL: define {{[^@]+}}@fmv_one._MsimdMwfxt 226 // CHECK-SAME: () #[[ATTR10:[0-9]+]] { 227 // CHECK-NEXT: entry: 228 // CHECK-NEXT: ret i32 1 229 // 230 // 231 // CHECK: Function Attrs: noinline nounwind optnone 232 // CHECK-LABEL: define {{[^@]+}}@fmv_one._Mdpb 233 // CHECK-SAME: () #[[ATTR11:[0-9]+]] { 234 // CHECK-NEXT: entry: 235 // CHECK-NEXT: ret i32 2 236 // 237 // 238 // CHECK: Function Attrs: noinline nounwind optnone 239 // CHECK-LABEL: define {{[^@]+}}@fmv_one.default 240 // CHECK-SAME: () #[[ATTR9]] { 241 // CHECK-NEXT: entry: 242 // CHECK-NEXT: ret i32 0 243 // 244 // 245 // CHECK: Function Attrs: noinline nounwind optnone 246 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp 247 // CHECK-SAME: () #[[ATTR12:[0-9]+]] { 248 // CHECK-NEXT: entry: 249 // CHECK-NEXT: ret i32 1 250 // 251 // 252 // CHECK: Function Attrs: noinline nounwind optnone 253 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd 254 // CHECK-SAME: () #[[ATTR13:[0-9]+]] { 255 // CHECK-NEXT: entry: 256 // CHECK-NEXT: ret i32 2 257 // 258 // 259 // CHECK: Function Attrs: noinline nounwind optnone 260 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd 261 // CHECK-SAME: () #[[ATTR14:[0-9]+]] { 262 // CHECK-NEXT: entry: 263 // CHECK-NEXT: ret i32 4 264 // 265 // 266 // CHECK: Function Attrs: noinline nounwind optnone 267 // CHECK-LABEL: define {{[^@]+}}@fmv_two.default 268 // CHECK-SAME: () #[[ATTR9]] { 269 // CHECK-NEXT: entry: 270 // CHECK-NEXT: ret i32 0 271 // 272 // 273 // CHECK: Function Attrs: noinline nounwind optnone 274 // CHECK-LABEL: define {{[^@]+}}@foo 275 // CHECK-SAME: () #[[ATTR15:[0-9]+]] { 276 // CHECK-NEXT: entry: 277 // CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv() 278 // CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_one() 279 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 280 // CHECK-NEXT: [[CALL2:%.*]] = call i32 @fmv_two() 281 // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 282 // CHECK-NEXT: ret i32 [[ADD3]] 283 // 284 // 285 // CHECK: Function Attrs: noinline nounwind optnone 286 // CHECK-LABEL: define {{[^@]+}}@fmv_e.default 287 // CHECK-SAME: () #[[ATTR9]] { 288 // CHECK-NEXT: entry: 289 // CHECK-NEXT: ret i32 20 290 // 291 // 292 // CHECK: Function Attrs: noinline nounwind optnone 293 // CHECK-LABEL: define {{[^@]+}}@fmv_default.default 294 // CHECK-SAME: () #[[ATTR9]] { 295 // CHECK-NEXT: entry: 296 // CHECK-NEXT: ret i32 111 297 // 298 // 299 // CHECK: Function Attrs: noinline nounwind optnone 300 // CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs 301 // CHECK-SAME: () #[[ATTR16:[0-9]+]] { 302 // CHECK-NEXT: entry: 303 // CHECK-NEXT: ret void 304 // 305 // 306 // CHECK: Function Attrs: noinline nounwind optnone 307 // CHECK-LABEL: define {{[^@]+}}@fmv_c.default 308 // CHECK-SAME: () #[[ATTR9]] { 309 // CHECK-NEXT: entry: 310 // CHECK-NEXT: ret void 311 // 312 // 313 // CHECK: Function Attrs: noinline nounwind optnone 314 // CHECK-LABEL: define {{[^@]+}}@goo 315 // CHECK-SAME: () #[[ATTR15]] { 316 // CHECK-NEXT: entry: 317 // CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv_inline() 318 // CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_e() 319 // CHECK-NEXT: [[CALL2:%.*]] = call i32 @fmv_d() 320 // CHECK-NEXT: call void @fmv_c() 321 // CHECK-NEXT: [[CALL3:%.*]] = call i32 @fmv_default() 322 // CHECK-NEXT: ret i32 [[CALL3]] 323 // 324 // 325 // CHECK: Function Attrs: noinline nounwind optnone 326 // CHECK-LABEL: define {{[^@]+}}@recur 327 // CHECK-SAME: () #[[ATTR15]] { 328 // CHECK-NEXT: entry: 329 // CHECK-NEXT: call void @reca() 330 // CHECK-NEXT: ret void 331 // 332 // 333 // CHECK: Function Attrs: noinline nounwind optnone 334 // CHECK-LABEL: define {{[^@]+}}@hoo 335 // CHECK-SAME: () #[[ATTR15]] { 336 // CHECK-NEXT: entry: 337 // CHECK-NEXT: [[FP1:%.*]] = alloca ptr, align 8 338 // CHECK-NEXT: [[FP2:%.*]] = alloca ptr, align 8 339 // CHECK-NEXT: call void @f(ptr noundef @fmv) 340 // CHECK-NEXT: store ptr @fmv, ptr [[FP1]], align 8 341 // CHECK-NEXT: store ptr @fmv, ptr [[FP2]], align 8 342 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8 343 // CHECK-NEXT: [[CALL:%.*]] = call i32 [[TMP0]]() 344 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8 345 // CHECK-NEXT: [[CALL1:%.*]] = call i32 [[TMP1]]() 346 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 347 // CHECK-NEXT: ret i32 [[ADD]] 348 // 349 // 350 // CHECK: Function Attrs: noinline nounwind optnone 351 // CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops 352 // CHECK-SAME: () #[[ATTR19:[0-9]+]] { 353 // CHECK-NEXT: entry: 354 // CHECK-NEXT: ret i32 0 355 // 356 // 357 // CHECK: Function Attrs: noinline nounwind optnone 358 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod 359 // CHECK-SAME: () #[[ATTR20:[0-9]+]] { 360 // CHECK-NEXT: entry: 361 // CHECK-NEXT: ret i32 0 362 // 363 // 364 // CHECK: Function Attrs: noinline nounwind optnone 365 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_decl._Maes 366 // CHECK-SAME: () #[[ATTR21:[0-9]+]] { 367 // CHECK-NEXT: entry: 368 // CHECK-NEXT: ret i32 0 369 // 370 // 371 // CHECK: Function Attrs: noinline nounwind optnone 372 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve 373 // CHECK-SAME: () #[[ATTR22:[0-9]+]] { 374 // CHECK-NEXT: entry: 375 // CHECK-NEXT: ret i32 0 376 // 377 // 378 // CHECK: Function Attrs: noinline nounwind optnone 379 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.default 380 // CHECK-SAME: () #[[ATTR9]] { 381 // CHECK-NEXT: entry: 382 // CHECK-NEXT: ret i32 1 383 // 384 // 385 // CHECK: Function Attrs: noinline nounwind optnone 386 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16 387 // CHECK-SAME: () #[[ATTR23:[0-9]+]] { 388 // CHECK-NEXT: entry: 389 // CHECK-NEXT: ret i32 0 390 // 391 // 392 // CHECK: Function Attrs: noinline nounwind optnone 393 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.default 394 // CHECK-SAME: () #[[ATTR9]] { 395 // CHECK-NEXT: entry: 396 // CHECK-NEXT: ret i32 1 397 // 398 // 399 // CHECK: Function Attrs: noinline nounwind optnone 400 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.default 401 // CHECK-SAME: () #[[ATTR15]] { 402 // CHECK-NEXT: entry: 403 // CHECK-NEXT: ret i32 0 404 // 405 // 406 // CHECK: Function Attrs: noinline nounwind optnone 407 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse 408 // CHECK-SAME: () #[[ATTR24:[0-9]+]] { 409 // CHECK-NEXT: entry: 410 // CHECK-NEXT: ret i32 1 411 // 412 // 413 // CHECK: Function Attrs: noinline nounwind optnone 414 // CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm 415 // CHECK-SAME: () #[[ATTR25:[0-9]+]] { 416 // CHECK-NEXT: entry: 417 // CHECK-NEXT: ret i32 0 418 // 419 // 420 // CHECK: Function Attrs: noinline nounwind optnone 421 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default 422 // CHECK-SAME: () #[[ATTR15]] { 423 // CHECK-NEXT: entry: 424 // CHECK-NEXT: ret i32 0 425 // 426 // 427 // CHECK: Function Attrs: noinline nounwind optnone 428 // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt 429 // CHECK-SAME: () #[[ATTR27:[0-9]+]] { 430 // CHECK-NEXT: entry: 431 // CHECK-NEXT: ret i32 1 432 // 433 // 434 // CHECK: Function Attrs: noinline nounwind optnone 435 // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm 436 // CHECK-SAME: () #[[ATTR28:[0-9]+]] { 437 // CHECK-NEXT: entry: 438 // CHECK-NEXT: ret i32 2 439 // 440 // 441 // CHECK: Function Attrs: noinline nounwind optnone 442 // CHECK-LABEL: define {{[^@]+}}@caller 443 // CHECK-SAME: () #[[ATTR15]] { 444 // CHECK-NEXT: entry: 445 // CHECK-NEXT: [[CALL:%.*]] = call i32 @used_def_without_default_decl() 446 // CHECK-NEXT: [[CALL1:%.*]] = call i32 @used_decl_without_default_decl() 447 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 448 // CHECK-NEXT: ret i32 [[ADD]] 449 // 450 // 451 // CHECK: Function Attrs: noinline nounwind optnone 452 // CHECK-LABEL: define {{[^@]+}}@main 453 // CHECK-SAME: () #[[ATTR9]] { 454 // CHECK-NEXT: entry: 455 // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 456 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 457 // CHECK-NEXT: call void @recur() 458 // CHECK-NEXT: [[CALL:%.*]] = call i32 @goo() 459 // CHECK-NEXT: ret i32 [[CALL]] 460 // 461 // 462 // CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat { 463 // CHECK-NEXT: resolver_entry: 464 // CHECK-NEXT: call void @__init_cpu_features_resolver() 465 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 466 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144119586256651008 467 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 144119586256651008 468 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 469 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 470 // CHECK: resolver_return: 471 // CHECK-NEXT: ret ptr @fmv._Msme2 472 // CHECK: resolver_else: 473 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 474 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72061992218723078 475 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 72061992218723078 476 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 477 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 478 // CHECK: resolver_return1: 479 // CHECK-NEXT: ret ptr @fmv._Mflagm2Msme-i16i64 480 // CHECK: resolver_else2: 481 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 482 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 18014398509483008 483 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 18014398509483008 484 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] 485 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 486 // CHECK: resolver_return3: 487 // CHECK-NEXT: ret ptr @fmv._McrcMwfxt 488 // CHECK: resolver_else4: 489 // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 490 // CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 18014398509482768 491 // CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 18014398509482768 492 // CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] 493 // CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] 494 // CHECK: resolver_return5: 495 // CHECK-NEXT: ret ptr @fmv._MdotprodMwfxt 496 // CHECK: resolver_else6: 497 // CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 498 // CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1125899906842624 499 // CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1125899906842624 500 // CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] 501 // CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] 502 // CHECK: resolver_return7: 503 // CHECK-NEXT: ret ptr @fmv._Mbti 504 // CHECK: resolver_else8: 505 // CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 506 // CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 17592186110728 507 // CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 17592186110728 508 // CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] 509 // CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] 510 // CHECK: resolver_return9: 511 // CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag 512 // CHECK: resolver_else10: 513 // CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 514 // CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 66315 515 // CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 66315 516 // CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] 517 // CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] 518 // CHECK: resolver_return11: 519 // CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng 520 // CHECK: resolver_else12: 521 // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 522 // CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 33536 523 // CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 33536 524 // CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] 525 // CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] 526 // CHECK: resolver_return13: 527 // CHECK-NEXT: ret ptr @fmv._MaesMfp 528 // CHECK: resolver_else14: 529 // CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 530 // CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 4992 531 // CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 4992 532 // CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] 533 // CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] 534 // CHECK: resolver_return15: 535 // CHECK-NEXT: ret ptr @fmv._MlseMsha2 536 // CHECK: resolver_else16: 537 // CHECK-NEXT: ret ptr @fmv.default 538 // 539 // 540 // CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat { 541 // CHECK-NEXT: resolver_entry: 542 // CHECK-NEXT: call void @__init_cpu_features_resolver() 543 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 544 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509482752 545 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509482752 546 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 547 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 548 // CHECK: resolver_return: 549 // CHECK-NEXT: ret ptr @fmv_one._MsimdMwfxt 550 // CHECK: resolver_else: 551 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 552 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 262144 553 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 262144 554 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 555 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 556 // CHECK: resolver_return1: 557 // CHECK-NEXT: ret ptr @fmv_one._Mdpb 558 // CHECK: resolver_else2: 559 // CHECK-NEXT: ret ptr @fmv_one.default 560 // 561 // 562 // CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat { 563 // CHECK-NEXT: resolver_entry: 564 // CHECK-NEXT: call void @__init_cpu_features_resolver() 565 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 566 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66304 567 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66304 568 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 569 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 570 // CHECK: resolver_return: 571 // CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd 572 // CHECK: resolver_else: 573 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 574 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 768 575 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 768 576 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 577 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 578 // CHECK: resolver_return1: 579 // CHECK-NEXT: ret ptr @fmv_two._Msimd 580 // CHECK: resolver_else2: 581 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 582 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 256 583 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256 584 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] 585 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 586 // CHECK: resolver_return3: 587 // CHECK-NEXT: ret ptr @fmv_two._Mfp 588 // CHECK: resolver_else4: 589 // CHECK-NEXT: ret ptr @fmv_two.default 590 // 591 // 592 // CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat { 593 // CHECK-NEXT: resolver_entry: 594 // CHECK-NEXT: call void @__init_cpu_features_resolver() 595 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 596 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509481984 597 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509481984 598 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 599 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 600 // CHECK: resolver_return: 601 // CHECK-NEXT: ret ptr @fmv_e._Mwfxt 602 // CHECK: resolver_else: 603 // CHECK-NEXT: ret ptr @fmv_e.default 604 // 605 // 606 // CHECK: Function Attrs: noinline nounwind optnone 607 // CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb 608 // CHECK-SAME: () #[[ATTR30:[0-9]+]] { 609 // CHECK-NEXT: entry: 610 // CHECK-NEXT: ret i32 0 611 // 612 // 613 // CHECK: Function Attrs: noinline nounwind optnone 614 // CHECK-LABEL: define {{[^@]+}}@fmv_d.default 615 // CHECK-SAME: () #[[ATTR9]] { 616 // CHECK-NEXT: entry: 617 // CHECK-NEXT: ret i32 1 618 // 619 // 620 // CHECK-LABEL: define {{[^@]+}}@fmv_d.resolver() { 621 // CHECK-NEXT: resolver_entry: 622 // CHECK-NEXT: call void @__init_cpu_features_resolver() 623 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 624 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664 625 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664 626 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 627 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 628 // CHECK: resolver_return: 629 // CHECK-NEXT: ret ptr @fmv_d._Msb 630 // CHECK: resolver_else: 631 // CHECK-NEXT: ret ptr @fmv_d.default 632 // 633 // 634 // CHECK-LABEL: define {{[^@]+}}@fmv_default.resolver() comdat { 635 // CHECK-NEXT: resolver_entry: 636 // CHECK-NEXT: ret ptr @fmv_default.default 637 // 638 // 639 // CHECK-LABEL: define {{[^@]+}}@fmv_c.resolver() comdat { 640 // CHECK-NEXT: resolver_entry: 641 // CHECK-NEXT: call void @__init_cpu_features_resolver() 642 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 643 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312 644 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312 645 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 646 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 647 // CHECK: resolver_return: 648 // CHECK-NEXT: ret ptr @fmv_c._Mssbs 649 // CHECK: resolver_else: 650 // CHECK-NEXT: ret ptr @fmv_c.default 651 // 652 // 653 // CHECK: Function Attrs: noinline nounwind optnone 654 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMf64mmMsha2 655 // CHECK-SAME: () #[[ATTR31:[0-9]+]] { 656 // CHECK-NEXT: entry: 657 // CHECK-NEXT: ret i32 1 658 // 659 // 660 // CHECK: Function Attrs: noinline nounwind optnone 661 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme 662 // CHECK-SAME: () #[[ATTR32:[0-9]+]] { 663 // CHECK-NEXT: entry: 664 // CHECK-NEXT: ret i32 2 665 // 666 // 667 // CHECK: Function Attrs: noinline nounwind optnone 668 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3 669 // CHECK-SAME: () #[[ATTR33:[0-9]+]] { 670 // CHECK-NEXT: entry: 671 // CHECK-NEXT: ret i32 12 672 // 673 // 674 // CHECK: Function Attrs: noinline nounwind optnone 675 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit 676 // CHECK-SAME: () #[[ATTR34:[0-9]+]] { 677 // CHECK-NEXT: entry: 678 // CHECK-NEXT: ret i32 8 679 // 680 // 681 // CHECK: Function Attrs: noinline nounwind optnone 682 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2 683 // CHECK-SAME: () #[[ATTR35:[0-9]+]] { 684 // CHECK-NEXT: entry: 685 // CHECK-NEXT: ret i32 6 686 // 687 // 688 // CHECK: Function Attrs: noinline nounwind optnone 689 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt 690 // CHECK-SAME: () #[[ATTR36:[0-9]+]] { 691 // CHECK-NEXT: entry: 692 // CHECK-NEXT: ret i32 7 693 // 694 // 695 // CHECK: Function Attrs: noinline nounwind optnone 696 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc 697 // CHECK-SAME: () #[[ATTR37:[0-9]+]] { 698 // CHECK-NEXT: entry: 699 // CHECK-NEXT: ret i32 3 700 // 701 // 702 // CHECK: Function Attrs: noinline nounwind optnone 703 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve 704 // CHECK-SAME: () #[[ATTR38:[0-9]+]] { 705 // CHECK-NEXT: entry: 706 // CHECK-NEXT: ret i32 4 707 // 708 // 709 // CHECK: Function Attrs: noinline nounwind optnone 710 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3 711 // CHECK-SAME: () #[[ATTR39:[0-9]+]] { 712 // CHECK-NEXT: entry: 713 // CHECK-NEXT: ret i32 5 714 // 715 // 716 // CHECK: Function Attrs: noinline nounwind optnone 717 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-aesMsve2-bitperm 718 // CHECK-SAME: () #[[ATTR40:[0-9]+]] { 719 // CHECK-NEXT: entry: 720 // CHECK-NEXT: ret i32 9 721 // 722 // 723 // CHECK: Function Attrs: noinline nounwind optnone 724 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4 725 // CHECK-SAME: () #[[ATTR41:[0-9]+]] { 726 // CHECK-NEXT: entry: 727 // CHECK-NEXT: ret i32 10 728 // 729 // 730 // CHECK: Function Attrs: noinline nounwind optnone 731 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3 732 // CHECK-SAME: () #[[ATTR42:[0-9]+]] { 733 // CHECK-NEXT: entry: 734 // CHECK-NEXT: ret i32 11 735 // 736 // 737 // CHECK: Function Attrs: noinline nounwind optnone 738 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod 739 // CHECK-SAME: () #[[ATTR43:[0-9]+]] { 740 // CHECK-NEXT: entry: 741 // CHECK-NEXT: ret i32 13 742 // 743 // 744 // CHECK: Function Attrs: noinline nounwind optnone 745 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd 746 // CHECK-SAME: () #[[ATTR44:[0-9]+]] { 747 // CHECK-NEXT: entry: 748 // CHECK-NEXT: ret i32 14 749 // 750 // 751 // CHECK: Function Attrs: noinline nounwind optnone 752 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4 753 // CHECK-SAME: () #[[ATTR45:[0-9]+]] { 754 // CHECK-NEXT: entry: 755 // CHECK-NEXT: ret i32 15 756 // 757 // 758 // CHECK: Function Attrs: noinline nounwind optnone 759 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm 760 // CHECK-SAME: () #[[ATTR46:[0-9]+]] { 761 // CHECK-NEXT: entry: 762 // CHECK-NEXT: ret i32 16 763 // 764 // 765 // CHECK: Function Attrs: noinline nounwind optnone 766 // CHECK-LABEL: define {{[^@]+}}@fmv_inline.default 767 // CHECK-SAME: () #[[ATTR9]] { 768 // CHECK-NEXT: entry: 769 // CHECK-NEXT: ret i32 3 770 // 771 // 772 // CHECK-LABEL: define {{[^@]+}}@fmv_inline.resolver() comdat { 773 // CHECK-NEXT: resolver_entry: 774 // CHECK-NEXT: call void @__init_cpu_features_resolver() 775 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 776 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 864708720653762560 777 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 864708720653762560 778 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 779 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 780 // CHECK: resolver_return: 781 // CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3 782 // CHECK: resolver_else: 783 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 784 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 19861002584864 785 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 19861002584864 786 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 787 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 788 // CHECK: resolver_return1: 789 // CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4 790 // CHECK: resolver_else2: 791 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 792 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4398182892352 793 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4398182892352 794 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] 795 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] 796 // CHECK: resolver_return3: 797 // CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme 798 // CHECK: resolver_else4: 799 // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 800 // CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 1444182864640 801 // CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1444182864640 802 // CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] 803 // CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] 804 // CHECK: resolver_return5: 805 // CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3 806 // CHECK: resolver_else6: 807 // CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 808 // CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 894427038464 809 // CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 894427038464 810 // CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] 811 // CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] 812 // CHECK: resolver_return7: 813 // CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm 814 // CHECK: resolver_else8: 815 // CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 816 // CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 35433583360 817 // CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 35433583360 818 // CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] 819 // CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] 820 // CHECK: resolver_return9: 821 // CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2 822 // CHECK: resolver_else10: 823 // CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 824 // CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18320798464 825 // CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18320798464 826 // CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] 827 // CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] 828 // CHECK: resolver_return11: 829 // CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3 830 // CHECK: resolver_else12: 831 // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 832 // CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1208025856 833 // CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1208025856 834 // CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] 835 // CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] 836 // CHECK: resolver_return13: 837 // CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve 838 // CHECK: resolver_else14: 839 // CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 840 // CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 134349568 841 // CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134349568 842 // CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] 843 // CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] 844 // CHECK: resolver_return15: 845 // CHECK-NEXT: ret ptr @fmv_inline._Mbf16Mdit 846 // CHECK: resolver_else16: 847 // CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 848 // CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971776 849 // CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971776 850 // CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]] 851 // CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]] 852 // CHECK: resolver_return17: 853 // CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc 854 // CHECK: resolver_else18: 855 // CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 856 // CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 12845056 857 // CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 12845056 858 // CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]] 859 // CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]] 860 // CHECK: resolver_return19: 861 // CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2 862 // CHECK: resolver_else20: 863 // CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 864 // CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1835264 865 // CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1835264 866 // CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]] 867 // CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]] 868 // CHECK: resolver_return21: 869 // CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt 870 // CHECK: resolver_else22: 871 // CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 872 // CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 66312 873 // CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 66312 874 // CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] 875 // CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] 876 // CHECK: resolver_return23: 877 // CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd 878 // CHECK: resolver_else24: 879 // CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 880 // CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 33552 881 // CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 33552 882 // CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] 883 // CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] 884 // CHECK: resolver_return25: 885 // CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod 886 // CHECK: resolver_else26: 887 // CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 888 // CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 960 889 // CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 960 890 // CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] 891 // CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] 892 // CHECK: resolver_return27: 893 // CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm 894 // CHECK: resolver_else28: 895 // CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 896 // CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 800 897 // CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 800 898 // CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] 899 // CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] 900 // CHECK: resolver_return29: 901 // CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4 902 // CHECK: resolver_else30: 903 // CHECK-NEXT: ret ptr @fmv_inline.default 904 // 905 // 906 // CHECK: Function Attrs: noinline nounwind optnone 907 // CHECK-LABEL: define {{[^@]+}}@reca.default 908 // CHECK-SAME: () #[[ATTR9]] { 909 // CHECK-NEXT: entry: 910 // CHECK-NEXT: call void @recb() 911 // CHECK-NEXT: ret void 912 // 913 // 914 // CHECK-LABEL: define {{[^@]+}}@reca.resolver() comdat { 915 // CHECK-NEXT: resolver_entry: 916 // CHECK-NEXT: ret ptr @reca.default 917 // 918 // 919 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.resolver() comdat { 920 // CHECK-NEXT: resolver_entry: 921 // CHECK-NEXT: call void @__init_cpu_features_resolver() 922 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 923 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1073807616 924 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073807616 925 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 926 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 927 // CHECK: resolver_return: 928 // CHECK-NEXT: ret ptr @unused_with_default_def._Msve 929 // CHECK: resolver_else: 930 // CHECK-NEXT: ret ptr @unused_with_default_def.default 931 // 932 // 933 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.resolver() comdat { 934 // CHECK-NEXT: resolver_entry: 935 // CHECK-NEXT: call void @__init_cpu_features_resolver() 936 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 937 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65792 938 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792 939 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 940 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 941 // CHECK: resolver_return: 942 // CHECK-NEXT: ret ptr @unused_with_implicit_default_def._Mfp16 943 // CHECK: resolver_else: 944 // CHECK-NEXT: ret ptr @unused_with_implicit_default_def.default 945 // 946 // 947 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.resolver() comdat { 948 // CHECK-NEXT: resolver_entry: 949 // CHECK-NEXT: call void @__init_cpu_features_resolver() 950 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 951 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 128 952 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 128 953 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 954 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 955 // CHECK: resolver_return: 956 // CHECK-NEXT: ret ptr @unused_with_implicit_forward_default_def._Mlse 957 // CHECK: resolver_else: 958 // CHECK-NEXT: ret ptr @unused_with_implicit_forward_default_def.default 959 // 960 // 961 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat { 962 // CHECK-NEXT: resolver_entry: 963 // CHECK-NEXT: call void @__init_cpu_features_resolver() 964 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 965 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832 966 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832 967 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] 968 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] 969 // CHECK: resolver_return: 970 // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mjscvt 971 // CHECK: resolver_else: 972 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 973 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832 974 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832 975 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] 976 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] 977 // CHECK: resolver_return1: 978 // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mrdm 979 // CHECK: resolver_else2: 980 // CHECK-NEXT: ret ptr @default_def_with_version_decls.default 981 // 982 // 983 // CHECK: Function Attrs: noinline nounwind optnone 984 // CHECK-LABEL: define {{[^@]+}}@recb.default 985 // CHECK-SAME: () #[[ATTR9]] { 986 // CHECK-NEXT: entry: 987 // CHECK-NEXT: call void @func() 988 // CHECK-NEXT: ret void 989 // 990 // 991 // CHECK: Function Attrs: noinline nounwind optnone 992 // CHECK-LABEL: define {{[^@]+}}@func 993 // CHECK-SAME: () #[[ATTR15]] { 994 // CHECK-NEXT: entry: 995 // CHECK-NEXT: ret void 996 // 997 // 998 // CHECK-LABEL: define {{[^@]+}}@recb.resolver() comdat { 999 // CHECK-NEXT: resolver_entry: 1000 // CHECK-NEXT: ret ptr @recb.default 1001 // 1002 // 1003 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1004 // CHECK-NOFMV-LABEL: define {{[^@]+}}@foo 1005 // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] { 1006 // CHECK-NOFMV-NEXT: entry: 1007 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @fmv() 1008 // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @fmv_one() 1009 // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 1010 // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @fmv_two() 1011 // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] 1012 // CHECK-NOFMV-NEXT: ret i32 [[ADD3]] 1013 // 1014 // 1015 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1016 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv 1017 // CHECK-NOFMV-SAME: () #[[ATTR1:[0-9]+]] { 1018 // CHECK-NOFMV-NEXT: entry: 1019 // CHECK-NOFMV-NEXT: ret i32 0 1020 // 1021 // 1022 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1023 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_one 1024 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1025 // CHECK-NOFMV-NEXT: entry: 1026 // CHECK-NOFMV-NEXT: ret i32 0 1027 // 1028 // 1029 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1030 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_two 1031 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1032 // CHECK-NOFMV-NEXT: entry: 1033 // CHECK-NOFMV-NEXT: ret i32 0 1034 // 1035 // 1036 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1037 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_e 1038 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1039 // CHECK-NOFMV-NEXT: entry: 1040 // CHECK-NOFMV-NEXT: ret i32 20 1041 // 1042 // 1043 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1044 // CHECK-NOFMV-LABEL: define {{[^@]+}}@goo 1045 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1046 // CHECK-NOFMV-NEXT: entry: 1047 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @fmv_inline() 1048 // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @fmv_e() 1049 // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @fmv_d() 1050 // CHECK-NOFMV-NEXT: call void @fmv_c() 1051 // CHECK-NOFMV-NEXT: [[CALL3:%.*]] = call i32 @fmv_default() 1052 // CHECK-NOFMV-NEXT: ret i32 [[CALL3]] 1053 // 1054 // 1055 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1056 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_d 1057 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1058 // CHECK-NOFMV-NEXT: entry: 1059 // CHECK-NOFMV-NEXT: ret i32 1 1060 // 1061 // 1062 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1063 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_c 1064 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1065 // CHECK-NOFMV-NEXT: entry: 1066 // CHECK-NOFMV-NEXT: ret void 1067 // 1068 // 1069 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1070 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_default 1071 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1072 // CHECK-NOFMV-NEXT: entry: 1073 // CHECK-NOFMV-NEXT: ret i32 111 1074 // 1075 // 1076 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1077 // CHECK-NOFMV-LABEL: define {{[^@]+}}@recur 1078 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1079 // CHECK-NOFMV-NEXT: entry: 1080 // CHECK-NOFMV-NEXT: call void @reca() 1081 // CHECK-NOFMV-NEXT: ret void 1082 // 1083 // 1084 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1085 // CHECK-NOFMV-LABEL: define {{[^@]+}}@hoo 1086 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1087 // CHECK-NOFMV-NEXT: entry: 1088 // CHECK-NOFMV-NEXT: [[FP1:%.*]] = alloca ptr, align 8 1089 // CHECK-NOFMV-NEXT: [[FP2:%.*]] = alloca ptr, align 8 1090 // CHECK-NOFMV-NEXT: call void @f(ptr noundef @fmv) 1091 // CHECK-NOFMV-NEXT: store ptr @fmv, ptr [[FP1]], align 8 1092 // CHECK-NOFMV-NEXT: store ptr @fmv, ptr [[FP2]], align 8 1093 // CHECK-NOFMV-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8 1094 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 [[TMP0]]() 1095 // CHECK-NOFMV-NEXT: [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8 1096 // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 [[TMP1]]() 1097 // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] 1098 // CHECK-NOFMV-NEXT: ret i32 [[ADD]] 1099 // 1100 // 1101 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1102 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_default_def 1103 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1104 // CHECK-NOFMV-NEXT: entry: 1105 // CHECK-NOFMV-NEXT: ret i32 1 1106 // 1107 // 1108 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1109 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def 1110 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1111 // CHECK-NOFMV-NEXT: entry: 1112 // CHECK-NOFMV-NEXT: ret i32 0 1113 // 1114 // 1115 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1116 // CHECK-NOFMV-LABEL: define {{[^@]+}}@default_def_with_version_decls 1117 // CHECK-NOFMV-SAME: () #[[ATTR0]] { 1118 // CHECK-NOFMV-NEXT: entry: 1119 // CHECK-NOFMV-NEXT: ret i32 0 1120 // 1121 // 1122 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1123 // CHECK-NOFMV-LABEL: define {{[^@]+}}@main 1124 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1125 // CHECK-NOFMV-NEXT: entry: 1126 // CHECK-NOFMV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1127 // CHECK-NOFMV-NEXT: store i32 0, ptr [[RETVAL]], align 4 1128 // CHECK-NOFMV-NEXT: call void @recur() 1129 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @goo() 1130 // CHECK-NOFMV-NEXT: ret i32 [[CALL]] 1131 // 1132 // 1133 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone 1134 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_default_def 1135 // CHECK-NOFMV-SAME: () #[[ATTR1]] { 1136 // CHECK-NOFMV-NEXT: entry: 1137 // CHECK-NOFMV-NEXT: ret i32 1 1138 // 1139 //. 1140 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 1141 // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 1142 //. 1143 // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 1144 // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 1145 //. 1146