1 // RUN: %clang_cc1 -triple arm-linux-gnueabi -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM
2 // RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC32
3 // RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC64
4 // RUN: %clang_cc1 -triple mipsel-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
5 // RUN: %clang_cc1 -triple mipsisa32r6el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
6 // RUN: %clang_cc1 -triple mips64el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
7 // RUN: %clang_cc1 -triple mips64el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
8 // RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
9 // RUN: %clang_cc1 -triple sparc-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV8 -check-prefix=SPARC
10 // RUN: %clang_cc1 -triple sparcv9-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV9 -check-prefix=SPARC
11 // RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -emit-llvm %s -o - | FileCheck %s -check-prefix=NVPTX
12
13 unsigned char c1, c2;
14 unsigned short s1, s2;
15 unsigned int i1, i2;
16 unsigned long long ll1, ll2;
17 unsigned char a1[100], a2[100];
18
19 enum memory_order {
20 memory_order_relaxed,
21 memory_order_consume,
22 memory_order_acquire,
23 memory_order_release,
24 memory_order_acq_rel,
25 memory_order_seq_cst
26 };
27
test1(void)28 void test1(void) {
29 (void)__atomic_load(&c1, &c2, memory_order_seq_cst);
30 (void)__atomic_store(&c1, &c2, memory_order_seq_cst);
31 (void)__atomic_load(&s1, &s2, memory_order_seq_cst);
32 (void)__atomic_store(&s1, &s2, memory_order_seq_cst);
33 (void)__atomic_load(&i1, &i2, memory_order_seq_cst);
34 (void)__atomic_store(&i1, &i2, memory_order_seq_cst);
35 (void)__atomic_load(&ll1, &ll2, memory_order_seq_cst);
36 (void)__atomic_store(&ll1, &ll2, memory_order_seq_cst);
37 (void)__atomic_load(&a1, &a2, memory_order_seq_cst);
38 (void)__atomic_store(&a1, &a2, memory_order_seq_cst);
39
40 // ARM-LABEL: define{{.*}} void @test1
41 // ARM: = load atomic i8, ptr @c1 seq_cst, align 1
42 // ARM: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
43 // ARM: = load atomic i16, ptr @s1 seq_cst, align 2
44 // ARM: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
45 // ARM: = load atomic i32, ptr @i1 seq_cst, align 4
46 // ARM: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
47 // ARM: = load atomic i64, ptr @ll1 seq_cst, align 8
48 // ARM: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
49 // ARM: call{{.*}} void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
50 // ARM: call{{.*}} void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
51
52 // PPC32-LABEL: define{{.*}} void @test1
53 // PPC32: = load atomic i8, ptr @c1 seq_cst, align 1
54 // PPC32: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
55 // PPC32: = load atomic i16, ptr @s1 seq_cst, align 2
56 // PPC32: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
57 // PPC32: = load atomic i32, ptr @i1 seq_cst, align 4
58 // PPC32: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
59 // PPC32: = load atomic i64, ptr @ll1 seq_cst, align 8
60 // PPC32: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
61 // PPC32: call void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
62 // PPC32: call void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
63
64 // PPC64-LABEL: define{{.*}} void @test1
65 // PPC64: = load atomic i8, ptr @c1 seq_cst, align 1
66 // PPC64: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
67 // PPC64: = load atomic i16, ptr @s1 seq_cst, align 2
68 // PPC64: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
69 // PPC64: = load atomic i32, ptr @i1 seq_cst, align 4
70 // PPC64: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
71 // PPC64: = load atomic i64, ptr @ll1 seq_cst, align 8
72 // PPC64: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
73 // PPC64: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
74 // PPC64: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
75
76 // MIPS32-LABEL: define{{.*}} void @test1
77 // MIPS32: = load atomic i8, ptr @c1 seq_cst, align 1
78 // MIPS32: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
79 // MIPS32: = load atomic i16, ptr @s1 seq_cst, align 2
80 // MIPS32: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
81 // MIPS32: = load atomic i32, ptr @i1 seq_cst, align 4
82 // MIPS32: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
83 // MIPS32: = load atomic i64, ptr @ll1 seq_cst, align 8
84 // MIPS32: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
85 // MIPS32: call void @__atomic_load(i32 noundef signext 100, ptr noundef @a1, ptr noundef @a2
86 // MIPS32: call void @__atomic_store(i32 noundef signext 100, ptr noundef @a1, ptr noundef @a2
87
88 // MIPS64-LABEL: define{{.*}} void @test1
89 // MIPS64: = load atomic i8, ptr @c1 seq_cst, align 1
90 // MIPS64: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
91 // MIPS64: = load atomic i16, ptr @s1 seq_cst, align 2
92 // MIPS64: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
93 // MIPS64: = load atomic i32, ptr @i1 seq_cst, align 4
94 // MIPS64: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
95 // MIPS64: = load atomic i64, ptr @ll1 seq_cst, align 8
96 // MIPS64: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
97 // MIPS64: call void @__atomic_load(i64 noundef zeroext 100, ptr noundef @a1, ptr noundef @a2
98 // MIPS64: call void @__atomic_store(i64 noundef zeroext 100, ptr noundef @a1, ptr noundef @a2
99
100 // SPARC-LABEL: define{{.*}} void @test1
101 // SPARC: = load atomic i8, ptr @c1 seq_cst, align 1
102 // SPARC: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
103 // SPARC: = load atomic i16, ptr @s1 seq_cst, align 2
104 // SPARC: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
105 // SPARC: = load atomic i32, ptr @i1 seq_cst, align 4
106 // SPARC: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
107 // SPARC: load atomic i64, ptr @ll1 seq_cst, align 8
108 // SPARC: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
109 // SPARCV8: call void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
110 // SPARCV8: call void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
111 // SPARCV9: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
112 // SPARCV9: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
113
114 // NVPTX-LABEL: define{{.*}} void @test1
115 // NVPTX: = load atomic i8, ptr @c1 seq_cst, align 1
116 // NVPTX: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
117 // NVPTX: = load atomic i16, ptr @s1 seq_cst, align 2
118 // NVPTX: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
119 // NVPTX: = load atomic i32, ptr @i1 seq_cst, align 4
120 // NVPTX: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
121 // NVPTX: = load atomic i64, ptr @ll1 seq_cst, align 8
122 // NVPTX: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
123 // NVPTX: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
124 // NVPTX: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
125
126 }
127