1 // REQUIRES: riscv-registered-target
2 // RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v \
3 // RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
4
5 #include <riscv_vector.h>
6
7 // CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @_Z3baru15__rvv_int32m1_t
8 vint32m1_t __attribute__((riscv_vector_cc)) bar(vint32m1_t input);
test_vector_cc_attr(vint32m1_t input,int32_t * base,size_t vl)9 vint32m1_t test_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
10 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
11 vint32m1_t ret = bar(input);
12 __riscv_vse32_v_i32m1(base, val, vl);
13 return ret;
14 }
15
16 // CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @_Z3baru15__rvv_int32m1_t
17 [[riscv::vector_cc]] vint32m1_t bar(vint32m1_t input);
test_vector_cc_attr2(vint32m1_t input,int32_t * base,size_t vl)18 vint32m1_t test_vector_cc_attr2(vint32m1_t input, int32_t *base, size_t vl) {
19 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
20 vint32m1_t ret = bar(input);
21 __riscv_vse32_v_i32m1(base, val, vl);
22 return ret;
23 }
24
25 // CHECK-LLVM: call <vscale x 2 x i32> @_Z3bazu15__rvv_int32m1_t
26 vint32m1_t baz(vint32m1_t input);
test_no_vector_cc_attr(vint32m1_t input,int32_t * base,size_t vl)27 vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
28 vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
29 vint32m1_t ret = baz(input);
30 __riscv_vse32_v_i32m1(base, val, vl);
31 return ret;
32 }
33